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[PATCH] spinlock consolidation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / time.c
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1da177e4
LT		 1/* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $
2 * time.c: UltraSparc timer and TOD clock support.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 *
7 * Based largely on code which is:
8 *
9 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
10 */
11
12#include <linux/config.h>
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/time.h>
22#include <linux/timex.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/mc146818rtc.h>
26#include <linux/delay.h>
27#include <linux/profile.h>
28#include <linux/bcd.h>
29#include <linux/jiffies.h>
30#include <linux/cpufreq.h>
31#include <linux/percpu.h>
32#include <linux/profile.h>
33
34#include <asm/oplib.h>
35#include <asm/mostek.h>
36#include <asm/timer.h>
37#include <asm/irq.h>
38#include <asm/io.h>
39#include <asm/sbus.h>
40#include <asm/fhc.h>
41#include <asm/pbm.h>
42#include <asm/ebus.h>
43#include <asm/isa.h>
44#include <asm/starfire.h>
45#include <asm/smp.h>
46#include <asm/sections.h>
47#include <asm/cpudata.h>
48
49DEFINE_SPINLOCK(mostek_lock);
50DEFINE_SPINLOCK(rtc_lock);
ef0299bf 51void __iomem *mstk48t02_regs = NULL;
1da177e4
LT		 52#ifdef CONFIG_PCI
53unsigned long ds1287_regs = 0UL;
54#endif
55
56extern unsigned long wall_jiffies;
57
58u64 jiffies_64 = INITIAL_JIFFIES;
59
60EXPORT_SYMBOL(jiffies_64);
61
ef0299bf
AV		 62static void __iomem *mstk48t08_regs;
63static void __iomem *mstk48t59_regs;
1da177e4
LT		 64
65static int set_rtc_mmss(unsigned long);
66
67static __init unsigned long dummy_get_tick(void)
68{
69 return 0;
70}
71
72static __initdata struct sparc64_tick_ops dummy_tick_ops = {
73 .get_tick = dummy_get_tick,
74};
75
d369ddd2 76struct sparc64_tick_ops *tick_ops __read_mostly = &dummy_tick_ops;
1da177e4
LT		 77
78#define TICK_PRIV_BIT (1UL << 63)
79
80#ifdef CONFIG_SMP
81unsigned long profile_pc(struct pt_regs *regs)
82{
83 unsigned long pc = instruction_pointer(regs);
84
85 if (in_lock_functions(pc))
86 return regs->u_regs[UREG_RETPC];
87 return pc;
88}
89EXPORT_SYMBOL(profile_pc);
90#endif
91
92static void tick_disable_protection(void)
93{
94 /* Set things up so user can access tick register for profiling
95 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
96 * read back of %tick after writing it.
97 */
98 __asm__ __volatile__(
99 " ba,pt %%xcc, 1f\n"
100 " nop\n"
101 " .align 64\n"
102 "1: rd %%tick, %%g2\n"
103 " add %%g2, 6, %%g2\n"
104 " andn %%g2, %0, %%g2\n"
105 " wrpr %%g2, 0, %%tick\n"
106 " rdpr %%tick, %%g0"
107 : /* no outputs */
108 : "r" (TICK_PRIV_BIT)
109 : "g2");
110}
111
112static void tick_init_tick(unsigned long offset)
113{
114 tick_disable_protection();
115
116 __asm__ __volatile__(
117 " rd %%tick, %%g1\n"
118 " andn %%g1, %1, %%g1\n"
119 " ba,pt %%xcc, 1f\n"
120 " add %%g1, %0, %%g1\n"
121 " .align 64\n"
122 "1: wr %%g1, 0x0, %%tick_cmpr\n"
123 " rd %%tick_cmpr, %%g0"
124 : /* no outputs */
125 : "r" (offset), "r" (TICK_PRIV_BIT)
126 : "g1");
127}
128
129static unsigned long tick_get_tick(void)
130{
131 unsigned long ret;
132
133 __asm__ __volatile__("rd %%tick, %0\n\t"
134 "mov %0, %0"
135 : "=r" (ret));
136
137 return ret & ~TICK_PRIV_BIT;
138}
139
140static unsigned long tick_get_compare(void)
141{
142 unsigned long ret;
143
144 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
145 "mov %0, %0"
146 : "=r" (ret));
147
148 return ret;
149}
150
151static unsigned long tick_add_compare(unsigned long adj)
152{
153 unsigned long new_compare;
154
155 /* Workaround for Spitfire Errata (#54 I think??), I discovered
156 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
157 * number 103640.
158 *
159 * On Blackbird writes to %tick_cmpr can fail, the
160 * workaround seems to be to execute the wr instruction
161 * at the start of an I-cache line, and perform a dummy
162 * read back from %tick_cmpr right after writing to it. -DaveM
163 */
164 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
165 "ba,pt %%xcc, 1f\n\t"
166 " add %0, %1, %0\n\t"
167 ".align 64\n"
168 "1:\n\t"
169 "wr %0, 0, %%tick_cmpr\n\t"
170 "rd %%tick_cmpr, %%g0"
171 : "=&r" (new_compare)
172 : "r" (adj));
173
174 return new_compare;
175}
176
177static unsigned long tick_add_tick(unsigned long adj, unsigned long offset)
178{
179 unsigned long new_tick, tmp;
180
181 /* Also need to handle Blackbird bug here too. */
182 __asm__ __volatile__("rd %%tick, %0\n\t"
183 "add %0, %2, %0\n\t"
184 "wrpr %0, 0, %%tick\n\t"
185 "andn %0, %4, %1\n\t"
186 "ba,pt %%xcc, 1f\n\t"
187 " add %1, %3, %1\n\t"
188 ".align 64\n"
189 "1:\n\t"
190 "wr %1, 0, %%tick_cmpr\n\t"
191 "rd %%tick_cmpr, %%g0"
192 : "=&r" (new_tick), "=&r" (tmp)
193 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
194
195 return new_tick;
196}
197
d369ddd2 198static struct sparc64_tick_ops tick_operations __read_mostly = {
1da177e4
LT		 199 .init_tick = tick_init_tick,
200 .get_tick = tick_get_tick,
201 .get_compare = tick_get_compare,
202 .add_tick = tick_add_tick,
203 .add_compare = tick_add_compare,
204 .softint_mask = 1UL << 0,
205};
206
207static void stick_init_tick(unsigned long offset)
208{
209 tick_disable_protection();
210
211 /* Let the user get at STICK too. */
212 __asm__ __volatile__(
213 " rd %%asr24, %%g2\n"
214 " andn %%g2, %0, %%g2\n"
215 " wr %%g2, 0, %%asr24"
216 : /* no outputs */
217 : "r" (TICK_PRIV_BIT)
218 : "g1", "g2");
219
220 __asm__ __volatile__(
221 " rd %%asr24, %%g1\n"
222 " andn %%g1, %1, %%g1\n"
223 " add %%g1, %0, %%g1\n"
224 " wr %%g1, 0x0, %%asr25"
225 : /* no outputs */
226 : "r" (offset), "r" (TICK_PRIV_BIT)
227 : "g1");
228}
229
230static unsigned long stick_get_tick(void)
231{
232 unsigned long ret;
233
234 __asm__ __volatile__("rd %%asr24, %0"
235 : "=r" (ret));
236
237 return ret & ~TICK_PRIV_BIT;
238}
239
240static unsigned long stick_get_compare(void)
241{
242 unsigned long ret;
243
244 __asm__ __volatile__("rd %%asr25, %0"
245 : "=r" (ret));
246
247 return ret;
248}
249
250static unsigned long stick_add_tick(unsigned long adj, unsigned long offset)
251{
252 unsigned long new_tick, tmp;
253
254 __asm__ __volatile__("rd %%asr24, %0\n\t"
255 "add %0, %2, %0\n\t"
256 "wr %0, 0, %%asr24\n\t"
257 "andn %0, %4, %1\n\t"
258 "add %1, %3, %1\n\t"
259 "wr %1, 0, %%asr25"
260 : "=&r" (new_tick), "=&r" (tmp)
261 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
262
263 return new_tick;
264}
265
266static unsigned long stick_add_compare(unsigned long adj)
267{
268 unsigned long new_compare;
269
270 __asm__ __volatile__("rd %%asr25, %0\n\t"
271 "add %0, %1, %0\n\t"
272 "wr %0, 0, %%asr25"
273 : "=&r" (new_compare)
274 : "r" (adj));
275
276 return new_compare;
277}
278
d369ddd2 279static struct sparc64_tick_ops stick_operations __read_mostly = {
1da177e4
LT		 280 .init_tick = stick_init_tick,
281 .get_tick = stick_get_tick,
282 .get_compare = stick_get_compare,
283 .add_tick = stick_add_tick,
284 .add_compare = stick_add_compare,
285 .softint_mask = 1UL << 16,
286};
287
288/* On Hummingbird the STICK/STICK_CMPR register is implemented
289 * in I/O space. There are two 64-bit registers each, the
290 * first holds the low 32-bits of the value and the second holds
291 * the high 32-bits.
292 *
293 * Since STICK is constantly updating, we have to access it carefully.
294 *
295 * The sequence we use to read is:
296 * 1) read low
297 * 2) read high
298 * 3) read low again, if it rolled over increment high by 1
299 *
300 * Writing STICK safely is also tricky:
301 * 1) write low to zero
302 * 2) write high
303 * 3) write low
304 */
305#define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
306#define HBIRD_STICK_ADDR 0x1fe0000f070UL
307
308static unsigned long __hbird_read_stick(void)
309{
310 unsigned long ret, tmp1, tmp2, tmp3;
311 unsigned long addr = HBIRD_STICK_ADDR;
312
313 __asm__ __volatile__("ldxa [%1] %5, %2\n\t"
314 "add %1, 0x8, %1\n\t"
315 "ldxa [%1] %5, %3\n\t"
316 "sub %1, 0x8, %1\n\t"
317 "ldxa [%1] %5, %4\n\t"
318 "cmp %4, %2\n\t"
319 "blu,a,pn %%xcc, 1f\n\t"
320 " add %3, 1, %3\n"
321 "1:\n\t"
322 "sllx %3, 32, %3\n\t"
323 "or %3, %4, %0\n\t"
324 : "=&r" (ret), "=&r" (addr),
325 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
326 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
327
328 return ret;
329}
330
331static unsigned long __hbird_read_compare(void)
332{
333 unsigned long low, high;
334 unsigned long addr = HBIRD_STICKCMP_ADDR;
335
336 __asm__ __volatile__("ldxa [%2] %3, %0\n\t"
337 "add %2, 0x8, %2\n\t"
338 "ldxa [%2] %3, %1"
339 : "=&r" (low), "=&r" (high), "=&r" (addr)
340 : "i" (ASI_PHYS_BYPASS_EC_E), "2" (addr));
341
342 return (high << 32UL) | low;
343}
344
345static void __hbird_write_stick(unsigned long val)
346{
347 unsigned long low = (val & 0xffffffffUL);
348 unsigned long high = (val >> 32UL);
349 unsigned long addr = HBIRD_STICK_ADDR;
350
351 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
352 "add %0, 0x8, %0\n\t"
353 "stxa %3, [%0] %4\n\t"
354 "sub %0, 0x8, %0\n\t"
355 "stxa %2, [%0] %4"
356 : "=&r" (addr)
357 : "0" (addr), "r" (low), "r" (high),
358 "i" (ASI_PHYS_BYPASS_EC_E));
359}
360
361static void __hbird_write_compare(unsigned long val)
362{
363 unsigned long low = (val & 0xffffffffUL);
364 unsigned long high = (val >> 32UL);
365 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
366
367 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
368 "sub %0, 0x8, %0\n\t"
369 "stxa %2, [%0] %4"
370 : "=&r" (addr)
371 : "0" (addr), "r" (low), "r" (high),
372 "i" (ASI_PHYS_BYPASS_EC_E));
373}
374
375static void hbtick_init_tick(unsigned long offset)
376{
377 unsigned long val;
378
379 tick_disable_protection();
380
381 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
382 * XXX into actually sending STICK interrupts. I think because
383 * XXX of how we store %tick_cmpr in head.S this somehow resets the
384 * XXX {TICK + STICK} interrupt mux. -DaveM
385 */
386 __hbird_write_stick(__hbird_read_stick());
387
388 val = __hbird_read_stick() & ~TICK_PRIV_BIT;
389 __hbird_write_compare(val + offset);
390}
391
392static unsigned long hbtick_get_tick(void)
393{
394 return __hbird_read_stick() & ~TICK_PRIV_BIT;
395}
396
397static unsigned long hbtick_get_compare(void)
398{
399 return __hbird_read_compare();
400}
401
402static unsigned long hbtick_add_tick(unsigned long adj, unsigned long offset)
403{
404 unsigned long val;
405
406 val = __hbird_read_stick() + adj;
407 __hbird_write_stick(val);
408
409 val &= ~TICK_PRIV_BIT;
410 __hbird_write_compare(val + offset);
411
412 return val;
413}
414
415static unsigned long hbtick_add_compare(unsigned long adj)
416{
417 unsigned long val = __hbird_read_compare() + adj;
418
419 val &= ~TICK_PRIV_BIT;
420 __hbird_write_compare(val);
421
422 return val;
423}
424
d369ddd2 425static struct sparc64_tick_ops hbtick_operations __read_mostly = {
1da177e4
LT		 426 .init_tick = hbtick_init_tick,
427 .get_tick = hbtick_get_tick,
428 .get_compare = hbtick_get_compare,
429 .add_tick = hbtick_add_tick,
430 .add_compare = hbtick_add_compare,
431 .softint_mask = 1UL << 0,
432};
433
434/* timer_interrupt() needs to keep up the real-time clock,
435 * as well as call the "do_timer()" routine every clocktick
436 *
437 * NOTE: On SUN5 systems the ticker interrupt comes in using 2
438 * interrupts, one at level14 and one with softint bit 0.
439 */
d369ddd2 440unsigned long timer_tick_offset __read_mostly;
1da177e4 441
d369ddd2 442static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
1da177e4
LT		 443
444#define TICK_SIZE (tick_nsec / 1000)
445
446static inline void timer_check_rtc(void)
447{
448 /* last time the cmos clock got updated */
449 static long last_rtc_update;
450
451 /* Determine when to update the Mostek clock. */
b149ee22 452 if (ntp_synced() &&
1da177e4
LT		 453 xtime.tv_sec > last_rtc_update + 660 &&
454 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
455 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
456 if (set_rtc_mmss(xtime.tv_sec) == 0)
457 last_rtc_update = xtime.tv_sec;
458 else
459 last_rtc_update = xtime.tv_sec - 600;
460 /* do it again in 60 s */
461 }
462}
463
464static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
465{
d369ddd2 466 unsigned long ticks, compare, pstate;
1da177e4
LT		 467
468 write_seqlock(&xtime_lock);
469
470 do {
471#ifndef CONFIG_SMP
472 profile_tick(CPU_PROFILING, regs);
473 update_process_times(user_mode(regs));
474#endif
475 do_timer(regs);
476
477 /* Guarantee that the following sequences execute
478 * uninterrupted.
479 */
480 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
481 "wrpr %0, %1, %%pstate"
482 : "=r" (pstate)
483 : "i" (PSTATE_IE));
484
d369ddd2 485 compare = tick_ops->add_compare(timer_tick_offset);
1da177e4
LT		 486 ticks = tick_ops->get_tick();
487
488 /* Restore PSTATE_IE. */
489 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
490 : /* no outputs */
491 : "r" (pstate));
d369ddd2 492 } while (time_after_eq(ticks, compare));
1da177e4
LT		 493
494 timer_check_rtc();
495
496 write_sequnlock(&xtime_lock);
497
498 return IRQ_HANDLED;
499}
500
501#ifdef CONFIG_SMP
502void timer_tick_interrupt(struct pt_regs *regs)
503{
504 write_seqlock(&xtime_lock);
505
506 do_timer(regs);
507
1da177e4
LT		 508 timer_check_rtc();
509
510 write_sequnlock(&xtime_lock);
511}
512#endif
513
514/* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
515static void __init kick_start_clock(void)
516{
ef0299bf 517 void __iomem *regs = mstk48t02_regs;
1da177e4
LT		 518 u8 sec, tmp;
519 int i, count;
520
521 prom_printf("CLOCK: Clock was stopped. Kick start ");
522
523 spin_lock_irq(&mostek_lock);
524
525 /* Turn on the kick start bit to start the oscillator. */
526 tmp = mostek_read(regs + MOSTEK_CREG);
527 tmp |= MSTK_CREG_WRITE;
528 mostek_write(regs + MOSTEK_CREG, tmp);
529 tmp = mostek_read(regs + MOSTEK_SEC);
530 tmp &= ~MSTK_STOP;
531 mostek_write(regs + MOSTEK_SEC, tmp);
532 tmp = mostek_read(regs + MOSTEK_HOUR);
533 tmp |= MSTK_KICK_START;
534 mostek_write(regs + MOSTEK_HOUR, tmp);
535 tmp = mostek_read(regs + MOSTEK_CREG);
536 tmp &= ~MSTK_CREG_WRITE;
537 mostek_write(regs + MOSTEK_CREG, tmp);
538
539 spin_unlock_irq(&mostek_lock);
540
541 /* Delay to allow the clock oscillator to start. */
542 sec = MSTK_REG_SEC(regs);
543 for (i = 0; i < 3; i++) {
544 while (sec == MSTK_REG_SEC(regs))
545 for (count = 0; count < 100000; count++)
546 /* nothing */ ;
547 prom_printf(".");
548 sec = MSTK_REG_SEC(regs);
549 }
550 prom_printf("\n");
551
552 spin_lock_irq(&mostek_lock);
553
554 /* Turn off kick start and set a "valid" time and date. */
555 tmp = mostek_read(regs + MOSTEK_CREG);
556 tmp |= MSTK_CREG_WRITE;
557 mostek_write(regs + MOSTEK_CREG, tmp);
558 tmp = mostek_read(regs + MOSTEK_HOUR);
559 tmp &= ~MSTK_KICK_START;
560 mostek_write(regs + MOSTEK_HOUR, tmp);
561 MSTK_SET_REG_SEC(regs,0);
562 MSTK_SET_REG_MIN(regs,0);
563 MSTK_SET_REG_HOUR(regs,0);
564 MSTK_SET_REG_DOW(regs,5);
565 MSTK_SET_REG_DOM(regs,1);
566 MSTK_SET_REG_MONTH(regs,8);
567 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
568 tmp = mostek_read(regs + MOSTEK_CREG);
569 tmp &= ~MSTK_CREG_WRITE;
570 mostek_write(regs + MOSTEK_CREG, tmp);
571
572 spin_unlock_irq(&mostek_lock);
573
574 /* Ensure the kick start bit is off. If it isn't, turn it off. */
575 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
576 prom_printf("CLOCK: Kick start still on!\n");
577
578 spin_lock_irq(&mostek_lock);
579
580 tmp = mostek_read(regs + MOSTEK_CREG);
581 tmp |= MSTK_CREG_WRITE;
582 mostek_write(regs + MOSTEK_CREG, tmp);
583
584 tmp = mostek_read(regs + MOSTEK_HOUR);
585 tmp &= ~MSTK_KICK_START;
586 mostek_write(regs + MOSTEK_HOUR, tmp);
587
588 tmp = mostek_read(regs + MOSTEK_CREG);
589 tmp &= ~MSTK_CREG_WRITE;
590 mostek_write(regs + MOSTEK_CREG, tmp);
591
592 spin_unlock_irq(&mostek_lock);
593 }
594
595 prom_printf("CLOCK: Kick start procedure successful.\n");
596}
597
598/* Return nonzero if the clock chip battery is low. */
599static int __init has_low_battery(void)
600{
ef0299bf 601 void __iomem *regs = mstk48t02_regs;
1da177e4
LT		 602 u8 data1, data2;
603
604 spin_lock_irq(&mostek_lock);
605
606 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */
607 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
608 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
609 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
610
611 spin_unlock_irq(&mostek_lock);
612
613 return (data1 == data2); /* Was the write blocked? */
614}
615
616/* Probe for the real time clock chip. */
617static void __init set_system_time(void)
618{
619 unsigned int year, mon, day, hour, min, sec;
ef0299bf 620 void __iomem *mregs = mstk48t02_regs;
1da177e4
LT		 621#ifdef CONFIG_PCI
622 unsigned long dregs = ds1287_regs;
623#else
624 unsigned long dregs = 0UL;
625#endif
626 u8 tmp;
627
628 if (!mregs && !dregs) {
629 prom_printf("Something wrong, clock regs not mapped yet.\n");
630 prom_halt();
631 }
632
633 if (mregs) {
634 spin_lock_irq(&mostek_lock);
635
636 /* Traditional Mostek chip. */
637 tmp = mostek_read(mregs + MOSTEK_CREG);
638 tmp |= MSTK_CREG_READ;
639 mostek_write(mregs + MOSTEK_CREG, tmp);
640
641 sec = MSTK_REG_SEC(mregs);
642 min = MSTK_REG_MIN(mregs);
643 hour = MSTK_REG_HOUR(mregs);
644 day = MSTK_REG_DOM(mregs);
645 mon = MSTK_REG_MONTH(mregs);
646 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
647 } else {
648 int i;
649
650 /* Dallas 12887 RTC chip. */
651
652 /* Stolen from arch/i386/kernel/time.c, see there for
653 * credits and descriptive comments.
654 */
655 for (i = 0; i < 1000000; i++) {
656 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
657 break;
658 udelay(10);
659 }
660 for (i = 0; i < 1000000; i++) {
661 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
662 break;
663 udelay(10);
664 }
665 do {
666 sec = CMOS_READ(RTC_SECONDS);
667 min = CMOS_READ(RTC_MINUTES);
668 hour = CMOS_READ(RTC_HOURS);
669 day = CMOS_READ(RTC_DAY_OF_MONTH);
670 mon = CMOS_READ(RTC_MONTH);
671 year = CMOS_READ(RTC_YEAR);
672 } while (sec != CMOS_READ(RTC_SECONDS));
673 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
674 BCD_TO_BIN(sec);
675 BCD_TO_BIN(min);
676 BCD_TO_BIN(hour);
677 BCD_TO_BIN(day);
678 BCD_TO_BIN(mon);
679 BCD_TO_BIN(year);
680 }
681 if ((year += 1900) < 1970)
682 year += 100;
683 }
684
685 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
686 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
687 set_normalized_timespec(&wall_to_monotonic,
688 -xtime.tv_sec, -xtime.tv_nsec);
689
690 if (mregs) {
691 tmp = mostek_read(mregs + MOSTEK_CREG);
692 tmp &= ~MSTK_CREG_READ;
693 mostek_write(mregs + MOSTEK_CREG, tmp);
694
695 spin_unlock_irq(&mostek_lock);
696 }
697}
698
699void __init clock_probe(void)
700{
701 struct linux_prom_registers clk_reg[2];
702 char model[128];
703 int node, busnd = -1, err;
704 unsigned long flags;
705 struct linux_central *cbus;
706#ifdef CONFIG_PCI
707 struct linux_ebus *ebus = NULL;
708 struct sparc_isa_bridge *isa_br = NULL;
709#endif
710 static int invoked;
711
712 if (invoked)
713 return;
714 invoked = 1;
715
716
717 if (this_is_starfire) {
718 /* davem suggests we keep this within the 4M locked kernel image */
719 static char obp_gettod[256];
720 static u32 unix_tod;
721
722 sprintf(obp_gettod, "h# %08x unix-gettod",
723 (unsigned int) (long) &unix_tod);
724 prom_feval(obp_gettod);
725 xtime.tv_sec = unix_tod;
726 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
727 set_normalized_timespec(&wall_to_monotonic,
728 -xtime.tv_sec, -xtime.tv_nsec);
729 return;
730 }
731
732 local_irq_save(flags);
733
734 cbus = central_bus;
735 if (cbus != NULL)
736 busnd = central_bus->child->prom_node;
737
738 /* Check FHC Central then EBUSs then ISA bridges then SBUSs.
739 * That way we handle the presence of multiple properly.
740 *
741 * As a special case, machines with Central must provide the
742 * timer chip there.
743 */
744#ifdef CONFIG_PCI
745 if (ebus_chain != NULL) {
746 ebus = ebus_chain;
747 if (busnd == -1)
748 busnd = ebus->prom_node;
749 }
750 if (isa_chain != NULL) {
751 isa_br = isa_chain;
752 if (busnd == -1)
753 busnd = isa_br->prom_node;
754 }
755#endif
756 if (sbus_root != NULL && busnd == -1)
757 busnd = sbus_root->prom_node;
758
759 if (busnd == -1) {
760 prom_printf("clock_probe: problem, cannot find bus to search.\n");
761 prom_halt();
762 }
763
764 node = prom_getchild(busnd);
765
766 while (1) {
767 if (!node)
768 model[0] = 0;
769 else
770 prom_getstring(node, "model", model, sizeof(model));
771 if (strcmp(model, "mk48t02") &&
772 strcmp(model, "mk48t08") &&
773 strcmp(model, "mk48t59") &&
774 strcmp(model, "m5819") &&
775 strcmp(model, "m5819p") &&
776 strcmp(model, "m5823") &&
777 strcmp(model, "ds1287")) {
778 if (cbus != NULL) {
779 prom_printf("clock_probe: Central bus lacks timer chip.\n");
780 prom_halt();
781 }
782
783 if (node != 0)
784 node = prom_getsibling(node);
785#ifdef CONFIG_PCI
786 while ((node == 0) && ebus != NULL) {
787 ebus = ebus->next;
788 if (ebus != NULL) {
789 busnd = ebus->prom_node;
790 node = prom_getchild(busnd);
791 }
792 }
793 while ((node == 0) && isa_br != NULL) {
794 isa_br = isa_br->next;
795 if (isa_br != NULL) {
796 busnd = isa_br->prom_node;
797 node = prom_getchild(busnd);
798 }
799 }
800#endif
801 if (node == 0) {
802 prom_printf("clock_probe: Cannot find timer chip\n");
803 prom_halt();
804 }
805 continue;
806 }
807
808 err = prom_getproperty(node, "reg", (char *)clk_reg,
809 sizeof(clk_reg));
810 if(err == -1) {
811 prom_printf("clock_probe: Cannot get Mostek reg property\n");
812 prom_halt();
813 }
814
815 if (cbus != NULL) {
816 apply_fhc_ranges(central_bus->child, clk_reg, 1);
817 apply_central_ranges(central_bus, clk_reg, 1);
818 }
819#ifdef CONFIG_PCI
820 else if (ebus != NULL) {
821 struct linux_ebus_device *edev;
822
823 for_each_ebusdev(edev, ebus)
824 if (edev->prom_node == node)
825 break;
826 if (edev == NULL) {
827 if (isa_chain != NULL)
828 goto try_isa_clock;
829 prom_printf("%s: Mostek not probed by EBUS\n",
830 __FUNCTION__);
831 prom_halt();
832 }
833
834 if (!strcmp(model, "ds1287") ||
835 !strcmp(model, "m5819") ||
836 !strcmp(model, "m5819p") ||
837 !strcmp(model, "m5823")) {
838 ds1287_regs = edev->resource[0].start;
839 } else {
ef0299bf 840 mstk48t59_regs = (void __iomem *)
b4bca26c 841 edev->resource[0].start;
1da177e4
LT		 842 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
843 }
844 break;
845 }
846 else if (isa_br != NULL) {
847 struct sparc_isa_device *isadev;
848
849try_isa_clock:
850 for_each_isadev(isadev, isa_br)
851 if (isadev->prom_node == node)
852 break;
853 if (isadev == NULL) {
854 prom_printf("%s: Mostek not probed by ISA\n");
855 prom_halt();
856 }
857 if (!strcmp(model, "ds1287") ||
858 !strcmp(model, "m5819") ||
859 !strcmp(model, "m5819p") ||
860 !strcmp(model, "m5823")) {
861 ds1287_regs = isadev->resource.start;
862 } else {
ef0299bf 863 mstk48t59_regs = (void __iomem *)
b4bca26c 864 isadev->resource.start;
1da177e4
LT		 865 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
866 }
867 break;
868 }
869#endif
870 else {
871 if (sbus_root->num_sbus_ranges) {
872 int nranges = sbus_root->num_sbus_ranges;
873 int rngc;
874
875 for (rngc = 0; rngc < nranges; rngc++)
876 if (clk_reg[0].which_io ==
877 sbus_root->sbus_ranges[rngc].ot_child_space)
878 break;
879 if (rngc == nranges) {
880 prom_printf("clock_probe: Cannot find ranges for "
881 "clock regs.\n");
882 prom_halt();
883 }
884 clk_reg[0].which_io =
885 sbus_root->sbus_ranges[rngc].ot_parent_space;
886 clk_reg[0].phys_addr +=
887 sbus_root->sbus_ranges[rngc].ot_parent_base;
888 }
889 }
890
891 if(model[5] == '0' && model[6] == '2') {
ef0299bf 892 mstk48t02_regs = (void __iomem *)
b4bca26c
DM		 893 (((u64)clk_reg[0].phys_addr) |
894 (((u64)clk_reg[0].which_io)<<32UL));
1da177e4 895 } else if(model[5] == '0' && model[6] == '8') {
ef0299bf 896 mstk48t08_regs = (void __iomem *)
b4bca26c
DM		 897 (((u64)clk_reg[0].phys_addr) |
898 (((u64)clk_reg[0].which_io)<<32UL));
1da177e4
LT		 899 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
900 } else {
ef0299bf 901 mstk48t59_regs = (void __iomem *)
b4bca26c
DM		 902 (((u64)clk_reg[0].phys_addr) |
903 (((u64)clk_reg[0].which_io)<<32UL));
1da177e4
LT		 904 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
905 }
906 break;
907 }
908
b4bca26c 909 if (mstk48t02_regs != NULL) {
1da177e4
LT		 910 /* Report a low battery voltage condition. */
911 if (has_low_battery())
912 prom_printf("NVRAM: Low battery voltage!\n");
913
914 /* Kick start the clock if it is completely stopped. */
915 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
916 kick_start_clock();
917 }
918
919 set_system_time();
920
921 local_irq_restore(flags);
922}
923
924/* This is gets the master TICK_INT timer going. */
925static unsigned long sparc64_init_timers(void)
926{
927 unsigned long clock;
928 int node;
929#ifdef CONFIG_SMP
930 extern void smp_tick_init(void);
931#endif
932
933 if (tlb_type == spitfire) {
934 unsigned long ver, manuf, impl;
935
936 __asm__ __volatile__ ("rdpr %%ver, %0"
937 : "=&r" (ver));
938 manuf = ((ver >> 48) & 0xffff);
939 impl = ((ver >> 32) & 0xffff);
940 if (manuf == 0x17 && impl == 0x13) {
941 /* Hummingbird, aka Ultra-IIe */
942 tick_ops = &hbtick_operations;
943 node = prom_root_node;
944 clock = prom_getint(node, "stick-frequency");
945 } else {
946 tick_ops = &tick_operations;
947 cpu_find_by_instance(0, &node, NULL);
948 clock = prom_getint(node, "clock-frequency");
949 }
950 } else {
951 tick_ops = &stick_operations;
952 node = prom_root_node;
953 clock = prom_getint(node, "stick-frequency");
954 }
955 timer_tick_offset = clock / HZ;
956
957#ifdef CONFIG_SMP
958 smp_tick_init();
959#endif
960
961 return clock;
962}
963
964static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
965{
966 unsigned long pstate;
967 int err;
968
969 /* Register IRQ handler. */
088dd1f8 970 err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
1da177e4
LT		 971 "timer", NULL);
972
973 if (err) {
974 prom_printf("Serious problem, cannot register TICK_INT\n");
975 prom_halt();
976 }
977
978 /* Guarantee that the following sequences execute
979 * uninterrupted.
980 */
981 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
982 "wrpr %0, %1, %%pstate"
983 : "=r" (pstate)
984 : "i" (PSTATE_IE));
985
986 tick_ops->init_tick(timer_tick_offset);
987
988 /* Restore PSTATE_IE. */
989 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
990 : /* no outputs */
991 : "r" (pstate));
992
993 local_irq_enable();
994}
995
996struct freq_table {
997 unsigned long udelay_val_ref;
998 unsigned long clock_tick_ref;
999 unsigned int ref_freq;
1000};
1001static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0, 0 };
1002
1003unsigned long sparc64_get_clock_tick(unsigned int cpu)
1004{
1005 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
1006
1007 if (ft->clock_tick_ref)
1008 return ft->clock_tick_ref;
1009 return cpu_data(cpu).clock_tick;
1010}
1011
1012#ifdef CONFIG_CPU_FREQ
1013
1014static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
1015 void *data)
1016{
1017 struct cpufreq_freqs *freq = data;
1018 unsigned int cpu = freq->cpu;
1019 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
1020
1021 if (!ft->ref_freq) {
1022 ft->ref_freq = freq->old;
1023 ft->udelay_val_ref = cpu_data(cpu).udelay_val;
1024 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
1025 }
1026 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1027 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
1028 (val == CPUFREQ_RESUMECHANGE)) {
1029 cpu_data(cpu).udelay_val =
1030 cpufreq_scale(ft->udelay_val_ref,
1031 ft->ref_freq,
1032 freq->new);
1033 cpu_data(cpu).clock_tick =
1034 cpufreq_scale(ft->clock_tick_ref,
1035 ft->ref_freq,
1036 freq->new);
1037 }
1038
1039 return 0;
1040}
1041
1042static struct notifier_block sparc64_cpufreq_notifier_block = {
1043 .notifier_call = sparc64_cpufreq_notifier
1044};
1045
1046#endif /* CONFIG_CPU_FREQ */
1047
1048static struct time_interpolator sparc64_cpu_interpolator = {
1049 .source = TIME_SOURCE_CPU,
1050 .shift = 16,
1051 .mask = 0xffffffffffffffffLL
1052};
1053
1054/* The quotient formula is taken from the IA64 port. */
1055#define SPARC64_NSEC_PER_CYC_SHIFT 30UL
1056void __init time_init(void)
1057{
1058 unsigned long clock = sparc64_init_timers();
1059
1060 sparc64_cpu_interpolator.frequency = clock;
1061 register_time_interpolator(&sparc64_cpu_interpolator);
1062
1063 /* Now that the interpolator is registered, it is
1064 * safe to start the timer ticking.
1065 */
1066 sparc64_start_timers(timer_interrupt);
1067
1068 timer_ticks_per_nsec_quotient =
1069 (((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +
1070 (clock / 2)) / clock);
1071
1072#ifdef CONFIG_CPU_FREQ
1073 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
1074 CPUFREQ_TRANSITION_NOTIFIER);
1075#endif
1076}
1077
1078unsigned long long sched_clock(void)
1079{
1080 unsigned long ticks = tick_ops->get_tick();
1081
1082 return (ticks * timer_ticks_per_nsec_quotient)
1083 >> SPARC64_NSEC_PER_CYC_SHIFT;
1084}
1085
1086static int set_rtc_mmss(unsigned long nowtime)
1087{
1088 int real_seconds, real_minutes, chip_minutes;
ef0299bf 1089 void __iomem *mregs = mstk48t02_regs;
1da177e4
LT		 1090#ifdef CONFIG_PCI
1091 unsigned long dregs = ds1287_regs;
1092#else
1093 unsigned long dregs = 0UL;
1094#endif
1095 unsigned long flags;
1096 u8 tmp;
1097
1098 /*
1099 * Not having a register set can lead to trouble.
1100 * Also starfire doesn't have a tod clock.
1101 */
1102 if (!mregs && !dregs)
1103 return -1;
1104
1105 if (mregs) {
1106 spin_lock_irqsave(&mostek_lock, flags);
1107
1108 /* Read the current RTC minutes. */
1109 tmp = mostek_read(mregs + MOSTEK_CREG);
1110 tmp |= MSTK_CREG_READ;
1111 mostek_write(mregs + MOSTEK_CREG, tmp);
1112
1113 chip_minutes = MSTK_REG_MIN(mregs);
1114
1115 tmp = mostek_read(mregs + MOSTEK_CREG);
1116 tmp &= ~MSTK_CREG_READ;
1117 mostek_write(mregs + MOSTEK_CREG, tmp);
1118
1119 /*
1120 * since we're only adjusting minutes and seconds,
1121 * don't interfere with hour overflow. This avoids
1122 * messing with unknown time zones but requires your
1123 * RTC not to be off by more than 15 minutes
1124 */
1125 real_seconds = nowtime % 60;
1126 real_minutes = nowtime / 60;
1127 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1128 real_minutes += 30; /* correct for half hour time zone */
1129 real_minutes %= 60;
1130
1131 if (abs(real_minutes - chip_minutes) < 30) {
1132 tmp = mostek_read(mregs + MOSTEK_CREG);
1133 tmp |= MSTK_CREG_WRITE;
1134 mostek_write(mregs + MOSTEK_CREG, tmp);
1135
1136 MSTK_SET_REG_SEC(mregs,real_seconds);
1137 MSTK_SET_REG_MIN(mregs,real_minutes);
1138
1139 tmp = mostek_read(mregs + MOSTEK_CREG);
1140 tmp &= ~MSTK_CREG_WRITE;
1141 mostek_write(mregs + MOSTEK_CREG, tmp);
1142
1143 spin_unlock_irqrestore(&mostek_lock, flags);
1144
1145 return 0;
1146 } else {
1147 spin_unlock_irqrestore(&mostek_lock, flags);
1148
1149 return -1;
1150 }
1151 } else {
1152 int retval = 0;
1153 unsigned char save_control, save_freq_select;
1154
1155 /* Stolen from arch/i386/kernel/time.c, see there for
1156 * credits and descriptive comments.
1157 */
1158 spin_lock_irqsave(&rtc_lock, flags);
1159 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1160 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1161
1162 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1163 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1164
1165 chip_minutes = CMOS_READ(RTC_MINUTES);
1166 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1167 BCD_TO_BIN(chip_minutes);
1168 real_seconds = nowtime % 60;
1169 real_minutes = nowtime / 60;
1170 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1171 real_minutes += 30;
1172 real_minutes %= 60;
1173
1174 if (abs(real_minutes - chip_minutes) < 30) {
1175 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1176 BIN_TO_BCD(real_seconds);
1177 BIN_TO_BCD(real_minutes);
1178 }
1179 CMOS_WRITE(real_seconds,RTC_SECONDS);
1180 CMOS_WRITE(real_minutes,RTC_MINUTES);
1181 } else {
1182 printk(KERN_WARNING
1183 "set_rtc_mmss: can't update from %d to %d\n",
1184 chip_minutes, real_minutes);
1185 retval = -1;
1186 }
1187
1188 CMOS_WRITE(save_control, RTC_CONTROL);
1189 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1190 spin_unlock_irqrestore(&rtc_lock, flags);
1191
1192 return retval;
1193 }
1194}
kernel source for telekom puls (alcatel/mediatek)