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[PATCH] Add sysfs support for the IPMI device interface
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / kernel / pci_iommu.c
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1da177e4
LT		 1/* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
2 * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/mm.h>
4dbc30fb 11#include <linux/delay.h>
1da177e4
LT		 12
13#include <asm/pbm.h>
14
15#include "iommu_common.h"
16
17#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
18 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
19
20/* Accessing IOMMU and Streaming Buffer registers.
21 * REG parameter is a physical address. All registers
22 * are 64-bits in size.
23 */
24#define pci_iommu_read(__reg) \
25({ u64 __ret; \
26 __asm__ __volatile__("ldxa [%1] %2, %0" \
27 : "=r" (__ret) \
28 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
29 : "memory"); \
30 __ret; \
31})
32#define pci_iommu_write(__reg, __val) \
33 __asm__ __volatile__("stxa %0, [%1] %2" \
34 : /* no outputs */ \
35 : "r" (__val), "r" (__reg), \
36 "i" (ASI_PHYS_BYPASS_EC_E))
37
38/* Must be invoked under the IOMMU lock. */
39static void __iommu_flushall(struct pci_iommu *iommu)
40{
41 unsigned long tag;
42 int entry;
43
44 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
45 for (entry = 0; entry < 16; entry++) {
46 pci_iommu_write(tag, 0);
47 tag += 8;
48 }
49
50 /* Ensure completion of previous PIO writes. */
51 (void) pci_iommu_read(iommu->write_complete_reg);
52
53 /* Now update everyone's flush point. */
54 for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
55 iommu->alloc_info[entry].flush =
56 iommu->alloc_info[entry].next;
57 }
58}
59
60#define IOPTE_CONSISTENT(CTX) \
61 (IOPTE_VALID | IOPTE_CACHE | \
62 (((CTX) << 47) & IOPTE_CONTEXT))
63
64#define IOPTE_STREAMING(CTX) \
65 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
66
67/* Existing mappings are never marked invalid, instead they
68 * are pointed to a dummy page.
69 */
70#define IOPTE_IS_DUMMY(iommu, iopte) \
71 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
72
73static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
74{
75 unsigned long val = iopte_val(*iopte);
76
77 val &= ~IOPTE_PAGE;
78 val |= iommu->dummy_page_pa;
79
80 iopte_val(*iopte) = val;
81}
82
83void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize)
84{
85 int i;
86
87 tsbsize /= sizeof(iopte_t);
88
89 for (i = 0; i < tsbsize; i++)
90 iopte_make_dummy(iommu, &iommu->page_table[i]);
91}
92
93static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
94{
95 iopte_t *iopte, *limit, *first;
96 unsigned long cnum, ent, flush_point;
97
98 cnum = 0;
99 while ((1UL << cnum) < npages)
100 cnum++;
101 iopte = (iommu->page_table +
102 (cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
103
104 if (cnum == 0)
105 limit = (iommu->page_table +
106 iommu->lowest_consistent_map);
107 else
108 limit = (iopte +
109 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
110
111 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
112 flush_point = iommu->alloc_info[cnum].flush;
113
114 first = iopte;
115 for (;;) {
116 if (IOPTE_IS_DUMMY(iommu, iopte)) {
117 if ((iopte + (1 << cnum)) >= limit)
118 ent = 0;
119 else
120 ent = ent + 1;
121 iommu->alloc_info[cnum].next = ent;
122 if (ent == flush_point)
123 __iommu_flushall(iommu);
124 break;
125 }
126 iopte += (1 << cnum);
127 ent++;
128 if (iopte >= limit) {
129 iopte = (iommu->page_table +
130 (cnum <<
131 (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
132 ent = 0;
133 }
134 if (ent == flush_point)
135 __iommu_flushall(iommu);
136 if (iopte == first)
137 goto bad;
138 }
139
140 /* I've got your streaming cluster right here buddy boy... */
141 return iopte;
142
143bad:
144 printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
145 npages);
146 return NULL;
147}
148
149static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
150 unsigned long npages, unsigned long ctx)
151{
152 unsigned long cnum, ent;
153
154 cnum = 0;
155 while ((1UL << cnum) < npages)
156 cnum++;
157
158 ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
159 >> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
160
161 /* If the global flush might not have caught this entry,
162 * adjust the flush point such that we will flush before
163 * ever trying to reuse it.
164 */
165#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
166 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
167 iommu->alloc_info[cnum].flush = ent;
168#undef between
169}
170
171/* We allocate consistent mappings from the end of cluster zero. */
172static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
173{
174 iopte_t *iopte;
175
176 iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
177 while (iopte > iommu->page_table) {
178 iopte--;
179 if (IOPTE_IS_DUMMY(iommu, iopte)) {
180 unsigned long tmp = npages;
181
182 while (--tmp) {
183 iopte--;
184 if (!IOPTE_IS_DUMMY(iommu, iopte))
185 break;
186 }
187 if (tmp == 0) {
188 u32 entry = (iopte - iommu->page_table);
189
190 if (entry < iommu->lowest_consistent_map)
191 iommu->lowest_consistent_map = entry;
192 return iopte;
193 }
194 }
195 }
196 return NULL;
197}
198
199/* Allocate and map kernel buffer of size SIZE using consistent mode
200 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
201 * successful and set *DMA_ADDRP to the PCI side dma address.
202 */
203void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
204{
205 struct pcidev_cookie *pcp;
206 struct pci_iommu *iommu;
207 iopte_t *iopte;
208 unsigned long flags, order, first_page, ctx;
209 void *ret;
210 int npages;
211
212 size = IO_PAGE_ALIGN(size);
213 order = get_order(size);
214 if (order >= 10)
215 return NULL;
216
217 first_page = __get_free_pages(GFP_ATOMIC, order);
218 if (first_page == 0UL)
219 return NULL;
220 memset((char *)first_page, 0, PAGE_SIZE << order);
221
222 pcp = pdev->sysdata;
223 iommu = pcp->pbm->iommu;
224
225 spin_lock_irqsave(&iommu->lock, flags);
226 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
227 if (iopte == NULL) {
228 spin_unlock_irqrestore(&iommu->lock, flags);
229 free_pages(first_page, order);
230 return NULL;
231 }
232
233 *dma_addrp = (iommu->page_table_map_base +
234 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
235 ret = (void *) first_page;
236 npages = size >> IO_PAGE_SHIFT;
237 ctx = 0;
238 if (iommu->iommu_ctxflush)
239 ctx = iommu->iommu_cur_ctx++;
240 first_page = __pa(first_page);
241 while (npages--) {
242 iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
243 IOPTE_WRITE |
244 (first_page & IOPTE_PAGE));
245 iopte++;
246 first_page += IO_PAGE_SIZE;
247 }
248
249 {
250 int i;
251 u32 daddr = *dma_addrp;
252
253 npages = size >> IO_PAGE_SHIFT;
254 for (i = 0; i < npages; i++) {
255 pci_iommu_write(iommu->iommu_flush, daddr);
256 daddr += IO_PAGE_SIZE;
257 }
258 }
259
260 spin_unlock_irqrestore(&iommu->lock, flags);
261
262 return ret;
263}
264
265/* Free and unmap a consistent DMA translation. */
266void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
267{
268 struct pcidev_cookie *pcp;
269 struct pci_iommu *iommu;
270 iopte_t *iopte;
271 unsigned long flags, order, npages, i, ctx;
272
273 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
274 pcp = pdev->sysdata;
275 iommu = pcp->pbm->iommu;
276 iopte = iommu->page_table +
277 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
278
279 spin_lock_irqsave(&iommu->lock, flags);
280
281 if ((iopte - iommu->page_table) ==
282 iommu->lowest_consistent_map) {
283 iopte_t *walk = iopte + npages;
284 iopte_t *limit;
285
286 limit = (iommu->page_table +
287 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
288 while (walk < limit) {
289 if (!IOPTE_IS_DUMMY(iommu, walk))
290 break;
291 walk++;
292 }
293 iommu->lowest_consistent_map =
294 (walk - iommu->page_table);
295 }
296
297 /* Data for consistent mappings cannot enter the streaming
298 * buffers, so we only need to update the TSB. We flush
299 * the IOMMU here as well to prevent conflicts with the
300 * streaming mapping deferred tlb flush scheme.
301 */
302
303 ctx = 0;
304 if (iommu->iommu_ctxflush)
305 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
306
307 for (i = 0; i < npages; i++, iopte++)
308 iopte_make_dummy(iommu, iopte);
309
310 if (iommu->iommu_ctxflush) {
311 pci_iommu_write(iommu->iommu_ctxflush, ctx);
312 } else {
313 for (i = 0; i < npages; i++) {
314 u32 daddr = dvma + (i << IO_PAGE_SHIFT);
315
316 pci_iommu_write(iommu->iommu_flush, daddr);
317 }
318 }
319
320 spin_unlock_irqrestore(&iommu->lock, flags);
321
322 order = get_order(size);
323 if (order < 10)
324 free_pages((unsigned long)cpu, order);
325}
326
327/* Map a single buffer at PTR of SZ bytes for PCI DMA
328 * in streaming mode.
329 */
330dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
331{
332 struct pcidev_cookie *pcp;
333 struct pci_iommu *iommu;
334 struct pci_strbuf *strbuf;
335 iopte_t *base;
336 unsigned long flags, npages, oaddr;
337 unsigned long i, base_paddr, ctx;
338 u32 bus_addr, ret;
339 unsigned long iopte_protection;
340
341 pcp = pdev->sysdata;
342 iommu = pcp->pbm->iommu;
343 strbuf = &pcp->pbm->stc;
344
345 if (direction == PCI_DMA_NONE)
346 BUG();
347
348 oaddr = (unsigned long)ptr;
349 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
350 npages >>= IO_PAGE_SHIFT;
351
352 spin_lock_irqsave(&iommu->lock, flags);
353
354 base = alloc_streaming_cluster(iommu, npages);
355 if (base == NULL)
356 goto bad;
357 bus_addr = (iommu->page_table_map_base +
358 ((base - iommu->page_table) << IO_PAGE_SHIFT));
359 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
360 base_paddr = __pa(oaddr & IO_PAGE_MASK);
361 ctx = 0;
362 if (iommu->iommu_ctxflush)
363 ctx = iommu->iommu_cur_ctx++;
364 if (strbuf->strbuf_enabled)
365 iopte_protection = IOPTE_STREAMING(ctx);
366 else
367 iopte_protection = IOPTE_CONSISTENT(ctx);
368 if (direction != PCI_DMA_TODEVICE)
369 iopte_protection |= IOPTE_WRITE;
370
371 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
372 iopte_val(*base) = iopte_protection | base_paddr;
373
374 spin_unlock_irqrestore(&iommu->lock, flags);
375
376 return ret;
377
378bad:
379 spin_unlock_irqrestore(&iommu->lock, flags);
380 return PCI_DMA_ERROR_CODE;
381}
382
4dbc30fb
DM		 383static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages)
384{
385 int limit;
386
387 PCI_STC_FLUSHFLAG_INIT(strbuf);
388 if (strbuf->strbuf_ctxflush &&
389 iommu->iommu_ctxflush) {
390 unsigned long matchreg, flushreg;
391
392 flushreg = strbuf->strbuf_ctxflush;
393 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
394
395 limit = 10000;
396 do {
397 pci_iommu_write(flushreg, ctx);
398 udelay(10);
399 limit--;
400 if (!limit)
401 break;
402 } while(((long)pci_iommu_read(matchreg)) < 0L);
403 if (!limit)
404 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
405 "timeout vaddr[%08x] ctx[%lx]\n",
406 vaddr, ctx);
407 } else {
408 unsigned long i;
409
410 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
411 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
412 }
413
414 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
415 (void) pci_iommu_read(iommu->write_complete_reg);
416
417 limit = 10000;
418 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
419 limit--;
420 if (!limit)
421 break;
422 udelay(10);
423 membar("#LoadLoad");
424 }
425 if (!limit)
426 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
427 "vaddr[%08x] ctx[%lx] npages[%ld]\n",
428 vaddr, ctx, npages);
429}
430
1da177e4
LT		 431/* Unmap a single streaming mode DMA translation. */
432void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
433{
434 struct pcidev_cookie *pcp;
435 struct pci_iommu *iommu;
436 struct pci_strbuf *strbuf;
437 iopte_t *base;
4dbc30fb 438 unsigned long flags, npages, ctx;
1da177e4
LT		 439
440 if (direction == PCI_DMA_NONE)
441 BUG();
442
443 pcp = pdev->sysdata;
444 iommu = pcp->pbm->iommu;
445 strbuf = &pcp->pbm->stc;
446
447 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
448 npages >>= IO_PAGE_SHIFT;
449 base = iommu->page_table +
450 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
451#ifdef DEBUG_PCI_IOMMU
452 if (IOPTE_IS_DUMMY(iommu, base))
453 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
454 bus_addr, sz, __builtin_return_address(0));
455#endif
456 bus_addr &= IO_PAGE_MASK;
457
458 spin_lock_irqsave(&iommu->lock, flags);
459
460 /* Record the context, if any. */
461 ctx = 0;
462 if (iommu->iommu_ctxflush)
463 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
464
465 /* Step 1: Kick data out of streaming buffers if necessary. */
4dbc30fb
DM		 466 if (strbuf->strbuf_enabled)
467 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
1da177e4
LT		 468
469 /* Step 2: Clear out first TSB entry. */
470 iopte_make_dummy(iommu, base);
471
472 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
473 npages, ctx);
474
475 spin_unlock_irqrestore(&iommu->lock, flags);
476}
477
478#define SG_ENT_PHYS_ADDRESS(SG) \
479 (__pa(page_address((SG)->page)) + (SG)->offset)
480
481static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
482 int nused, int nelems, unsigned long iopte_protection)
483{
484 struct scatterlist *dma_sg = sg;
485 struct scatterlist *sg_end = sg + nelems;
486 int i;
487
488 for (i = 0; i < nused; i++) {
489 unsigned long pteval = ~0UL;
490 u32 dma_npages;
491
492 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
493 dma_sg->dma_length +
494 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
495 do {
496 unsigned long offset;
497 signed int len;
498
499 /* If we are here, we know we have at least one
500 * more page to map. So walk forward until we
501 * hit a page crossing, and begin creating new
502 * mappings from that spot.
503 */
504 for (;;) {
505 unsigned long tmp;
506
507 tmp = SG_ENT_PHYS_ADDRESS(sg);
508 len = sg->length;
509 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
510 pteval = tmp & IO_PAGE_MASK;
511 offset = tmp & (IO_PAGE_SIZE - 1UL);
512 break;
513 }
514 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
515 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
516 offset = 0UL;
517 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
518 break;
519 }
520 sg++;
521 }
522
523 pteval = iopte_protection | (pteval & IOPTE_PAGE);
524 while (len > 0) {
525 *iopte++ = __iopte(pteval);
526 pteval += IO_PAGE_SIZE;
527 len -= (IO_PAGE_SIZE - offset);
528 offset = 0;
529 dma_npages--;
530 }
531
532 pteval = (pteval & IOPTE_PAGE) + len;
533 sg++;
534
535 /* Skip over any tail mappings we've fully mapped,
536 * adjusting pteval along the way. Stop when we
537 * detect a page crossing event.
538 */
539 while (sg < sg_end &&
540 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
541 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
542 ((pteval ^
543 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
544 pteval += sg->length;
545 sg++;
546 }
547 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
548 pteval = ~0UL;
549 } while (dma_npages != 0);
550 dma_sg++;
551 }
552}
553
554/* Map a set of buffers described by SGLIST with NELEMS array
555 * elements in streaming mode for PCI DMA.
556 * When making changes here, inspect the assembly output. I was having
557 * hard time to kepp this routine out of using stack slots for holding variables.
558 */
559int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
560{
561 struct pcidev_cookie *pcp;
562 struct pci_iommu *iommu;
563 struct pci_strbuf *strbuf;
564 unsigned long flags, ctx, npages, iopte_protection;
565 iopte_t *base;
566 u32 dma_base;
567 struct scatterlist *sgtmp;
568 int used;
569
570 /* Fast path single entry scatterlists. */
571 if (nelems == 1) {
572 sglist->dma_address =
573 pci_map_single(pdev,
574 (page_address(sglist->page) + sglist->offset),
575 sglist->length, direction);
576 sglist->dma_length = sglist->length;
577 return 1;
578 }
579
580 pcp = pdev->sysdata;
581 iommu = pcp->pbm->iommu;
582 strbuf = &pcp->pbm->stc;
583
584 if (direction == PCI_DMA_NONE)
585 BUG();
586
587 /* Step 1: Prepare scatter list. */
588
589 npages = prepare_sg(sglist, nelems);
590
591 /* Step 2: Allocate a cluster. */
592
593 spin_lock_irqsave(&iommu->lock, flags);
594
595 base = alloc_streaming_cluster(iommu, npages);
596 if (base == NULL)
597 goto bad;
598 dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
599
600 /* Step 3: Normalize DMA addresses. */
601 used = nelems;
602
603 sgtmp = sglist;
604 while (used && sgtmp->dma_length) {
605 sgtmp->dma_address += dma_base;
606 sgtmp++;
607 used--;
608 }
609 used = nelems - used;
610
611 /* Step 4: Choose a context if necessary. */
612 ctx = 0;
613 if (iommu->iommu_ctxflush)
614 ctx = iommu->iommu_cur_ctx++;
615
616 /* Step 5: Create the mappings. */
617 if (strbuf->strbuf_enabled)
618 iopte_protection = IOPTE_STREAMING(ctx);
619 else
620 iopte_protection = IOPTE_CONSISTENT(ctx);
621 if (direction != PCI_DMA_TODEVICE)
622 iopte_protection |= IOPTE_WRITE;
623 fill_sg (base, sglist, used, nelems, iopte_protection);
624#ifdef VERIFY_SG
625 verify_sglist(sglist, nelems, base, npages);
626#endif
627
628 spin_unlock_irqrestore(&iommu->lock, flags);
629
630 return used;
631
632bad:
633 spin_unlock_irqrestore(&iommu->lock, flags);
634 return PCI_DMA_ERROR_CODE;
635}
636
637/* Unmap a set of streaming mode DMA translations. */
638void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
639{
640 struct pcidev_cookie *pcp;
641 struct pci_iommu *iommu;
642 struct pci_strbuf *strbuf;
643 iopte_t *base;
644 unsigned long flags, ctx, i, npages;
645 u32 bus_addr;
646
647 if (direction == PCI_DMA_NONE)
648 BUG();
649
650 pcp = pdev->sysdata;
651 iommu = pcp->pbm->iommu;
652 strbuf = &pcp->pbm->stc;
653
654 bus_addr = sglist->dma_address & IO_PAGE_MASK;
655
656 for (i = 1; i < nelems; i++)
657 if (sglist[i].dma_length == 0)
658 break;
659 i--;
660 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
661
662 base = iommu->page_table +
663 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
664
665#ifdef DEBUG_PCI_IOMMU
666 if (IOPTE_IS_DUMMY(iommu, base))
667 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
668#endif
669
670 spin_lock_irqsave(&iommu->lock, flags);
671
672 /* Record the context, if any. */
673 ctx = 0;
674 if (iommu->iommu_ctxflush)
675 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
676
677 /* Step 1: Kick data out of streaming buffers if necessary. */
4dbc30fb
DM		 678 if (strbuf->strbuf_enabled)
679 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
1da177e4
LT		 680
681 /* Step 2: Clear out first TSB entry. */
682 iopte_make_dummy(iommu, base);
683
684 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
685 npages, ctx);
686
687 spin_unlock_irqrestore(&iommu->lock, flags);
688}
689
690/* Make physical memory consistent for a single
691 * streaming mode DMA translation after a transfer.
692 */
693void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
694{
695 struct pcidev_cookie *pcp;
696 struct pci_iommu *iommu;
697 struct pci_strbuf *strbuf;
698 unsigned long flags, ctx, npages;
699
700 pcp = pdev->sysdata;
701 iommu = pcp->pbm->iommu;
702 strbuf = &pcp->pbm->stc;
703
704 if (!strbuf->strbuf_enabled)
705 return;
706
707 spin_lock_irqsave(&iommu->lock, flags);
708
709 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
710 npages >>= IO_PAGE_SHIFT;
711 bus_addr &= IO_PAGE_MASK;
712
713 /* Step 1: Record the context, if any. */
714 ctx = 0;
715 if (iommu->iommu_ctxflush &&
716 strbuf->strbuf_ctxflush) {
717 iopte_t *iopte;
718
719 iopte = iommu->page_table +
720 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
721 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
722 }
723
724 /* Step 2: Kick data out of streaming buffers. */
4dbc30fb 725 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
1da177e4
LT		 726
727 spin_unlock_irqrestore(&iommu->lock, flags);
728}
729
730/* Make physical memory consistent for a set of streaming
731 * mode DMA translations after a transfer.
732 */
733void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
734{
735 struct pcidev_cookie *pcp;
736 struct pci_iommu *iommu;
737 struct pci_strbuf *strbuf;
4dbc30fb
DM		 738 unsigned long flags, ctx, npages, i;
739 u32 bus_addr;
1da177e4
LT		 740
741 pcp = pdev->sysdata;
742 iommu = pcp->pbm->iommu;
743 strbuf = &pcp->pbm->stc;
744
745 if (!strbuf->strbuf_enabled)
746 return;
747
748 spin_lock_irqsave(&iommu->lock, flags);
749
750 /* Step 1: Record the context, if any. */
751 ctx = 0;
752 if (iommu->iommu_ctxflush &&
753 strbuf->strbuf_ctxflush) {
754 iopte_t *iopte;
755
756 iopte = iommu->page_table +
757 ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
758 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
759 }
760
761 /* Step 2: Kick data out of streaming buffers. */
4dbc30fb
DM		 762 bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
763 for(i = 1; i < nelems; i++)
764 if (!sglist[i].dma_length)
765 break;
766 i--;
767 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
768 - bus_addr) >> IO_PAGE_SHIFT;
769 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
1da177e4
LT		 770
771 spin_unlock_irqrestore(&iommu->lock, flags);
772}
773
774static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
775{
776 struct pci_dev *ali_isa_bridge;
777 u8 val;
778
779 /* ALI sound chips generate 31-bits of DMA, a special register
780 * determines what bit 31 is emitted as.
781 */
782 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
783 PCI_DEVICE_ID_AL_M1533,
784 NULL);
785
786 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
787 if (set_bit)
788 val |= 0x01;
789 else
790 val &= ~0x01;
791 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
792 pci_dev_put(ali_isa_bridge);
793}
794
795int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
796{
797 struct pcidev_cookie *pcp = pdev->sysdata;
798 u64 dma_addr_mask;
799
800 if (pdev == NULL) {
801 dma_addr_mask = 0xffffffff;
802 } else {
803 struct pci_iommu *iommu = pcp->pbm->iommu;
804
805 dma_addr_mask = iommu->dma_addr_mask;
806
807 if (pdev->vendor == PCI_VENDOR_ID_AL &&
808 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
809 device_mask == 0x7fffffff) {
810 ali_sound_dma_hack(pdev,
811 (dma_addr_mask & 0x80000000) != 0);
812 return 1;
813 }
814 }
815
816 if (device_mask >= (1UL << 32UL))
817 return 0;
818
819 return (device_mask & dma_addr_mask) == dma_addr_mask;
820}
kernel source for telekom puls (alcatel/mediatek)