Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * arch/sparc64/mm/init.c |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
1da177e4 LT |
16 | #include <linux/initrd.h> |
17 | #include <linux/swap.h> | |
18 | #include <linux/pagemap.h> | |
c9cf5528 | 19 | #include <linux/poison.h> |
1da177e4 LT |
20 | #include <linux/fs.h> |
21 | #include <linux/seq_file.h> | |
05e14cb3 | 22 | #include <linux/kprobes.h> |
1ac4f5eb | 23 | #include <linux/cache.h> |
13edad7a | 24 | #include <linux/sort.h> |
5cbc3073 | 25 | #include <linux/percpu.h> |
95f72d1e | 26 | #include <linux/memblock.h> |
919ee677 | 27 | #include <linux/mmzone.h> |
5a0e3ad6 | 28 | #include <linux/gfp.h> |
1da177e4 LT |
29 | |
30 | #include <asm/head.h> | |
1da177e4 LT |
31 | #include <asm/page.h> |
32 | #include <asm/pgalloc.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/oplib.h> | |
35 | #include <asm/iommu.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/mmu_context.h> | |
39 | #include <asm/tlbflush.h> | |
40 | #include <asm/dma.h> | |
41 | #include <asm/starfire.h> | |
42 | #include <asm/tlb.h> | |
43 | #include <asm/spitfire.h> | |
44 | #include <asm/sections.h> | |
517af332 | 45 | #include <asm/tsb.h> |
481295f9 | 46 | #include <asm/hypervisor.h> |
372b07bb | 47 | #include <asm/prom.h> |
5cbc3073 | 48 | #include <asm/mdesc.h> |
3d5ae6b6 | 49 | #include <asm/cpudata.h> |
4f70f7a9 | 50 | #include <asm/irq.h> |
1da177e4 | 51 | |
27137e52 | 52 | #include "init_64.h" |
9cc3a1ac DM |
53 | |
54 | unsigned long kern_linear_pte_xor[2] __read_mostly; | |
55 | ||
56 | /* A bitmap, one bit for every 256MB of physical memory. If the bit | |
57 | * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else | |
58 | * if set we should use a 256MB page (via kern_linear_pte_xor[1]). | |
59 | */ | |
60 | unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; | |
61 | ||
d1acb421 | 62 | #ifndef CONFIG_DEBUG_PAGEALLOC |
2d9e2763 DM |
63 | /* A special kernel TSB for 4MB and 256MB linear mappings. |
64 | * Space is allocated for this right after the trap table | |
65 | * in arch/sparc64/kernel/head.S | |
66 | */ | |
67 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 68 | #endif |
d7744a09 | 69 | |
13edad7a DM |
70 | #define MAX_BANKS 32 |
71 | ||
9a2ed5cc DM |
72 | static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata; |
73 | static int pavail_ents __devinitdata; | |
13edad7a DM |
74 | |
75 | static int cmp_p64(const void *a, const void *b) | |
76 | { | |
77 | const struct linux_prom64_registers *x = a, *y = b; | |
78 | ||
79 | if (x->phys_addr > y->phys_addr) | |
80 | return 1; | |
81 | if (x->phys_addr < y->phys_addr) | |
82 | return -1; | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static void __init read_obp_memory(const char *property, | |
87 | struct linux_prom64_registers *regs, | |
88 | int *num_ents) | |
89 | { | |
8d125562 | 90 | phandle node = prom_finddevice("/memory"); |
13edad7a DM |
91 | int prop_size = prom_getproplen(node, property); |
92 | int ents, ret, i; | |
93 | ||
94 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
95 | if (ents > MAX_BANKS) { | |
96 | prom_printf("The machine has more %s property entries than " | |
97 | "this kernel can support (%d).\n", | |
98 | property, MAX_BANKS); | |
99 | prom_halt(); | |
100 | } | |
101 | ||
102 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
103 | if (ret == -1) { | |
104 | prom_printf("Couldn't get %s property from /memory.\n"); | |
105 | prom_halt(); | |
106 | } | |
107 | ||
13edad7a DM |
108 | /* Sanitize what we got from the firmware, by page aligning |
109 | * everything. | |
110 | */ | |
111 | for (i = 0; i < ents; i++) { | |
112 | unsigned long base, size; | |
113 | ||
114 | base = regs[i].phys_addr; | |
115 | size = regs[i].reg_size; | |
10147570 | 116 | |
13edad7a DM |
117 | size &= PAGE_MASK; |
118 | if (base & ~PAGE_MASK) { | |
119 | unsigned long new_base = PAGE_ALIGN(base); | |
120 | ||
121 | size -= new_base - base; | |
122 | if ((long) size < 0L) | |
123 | size = 0UL; | |
124 | base = new_base; | |
125 | } | |
0015d3d6 DM |
126 | if (size == 0UL) { |
127 | /* If it is empty, simply get rid of it. | |
128 | * This simplifies the logic of the other | |
129 | * functions that process these arrays. | |
130 | */ | |
131 | memmove(®s[i], ®s[i + 1], | |
132 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 133 | i--; |
0015d3d6 DM |
134 | ents--; |
135 | continue; | |
486ad10a | 136 | } |
0015d3d6 DM |
137 | regs[i].phys_addr = base; |
138 | regs[i].reg_size = size; | |
486ad10a DM |
139 | } |
140 | ||
141 | *num_ents = ents; | |
142 | ||
c9c10830 | 143 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
144 | cmp_p64, NULL); |
145 | } | |
1da177e4 | 146 | |
d8ed1d43 DM |
147 | unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES / |
148 | sizeof(unsigned long)]; | |
917c3660 | 149 | EXPORT_SYMBOL(sparc64_valid_addr_bitmap); |
1da177e4 | 150 | |
d1112018 | 151 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
152 | unsigned long kern_base __read_mostly; |
153 | unsigned long kern_size __read_mostly; | |
1da177e4 | 154 | |
1da177e4 LT |
155 | /* Initial ramdisk setup */ |
156 | extern unsigned long sparc_ramdisk_image64; | |
157 | extern unsigned int sparc_ramdisk_image; | |
158 | extern unsigned int sparc_ramdisk_size; | |
159 | ||
1ac4f5eb | 160 | struct page *mem_map_zero __read_mostly; |
35802c0b | 161 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 162 | |
0835ae0f DM |
163 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
164 | ||
165 | unsigned long sparc64_kern_pri_context __read_mostly; | |
166 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
167 | unsigned long sparc64_kern_sec_context __read_mostly; | |
168 | ||
64658743 | 169 | int num_kernel_image_mappings; |
1da177e4 | 170 | |
1da177e4 LT |
171 | #ifdef CONFIG_DEBUG_DCFLUSH |
172 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
173 | #ifdef CONFIG_SMP | |
174 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
175 | #endif | |
176 | #endif | |
177 | ||
7a591cfe | 178 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 179 | { |
7a591cfe | 180 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
181 | #ifdef CONFIG_DEBUG_DCFLUSH |
182 | atomic_inc(&dcpage_flushes); | |
183 | #endif | |
184 | ||
185 | #ifdef DCACHE_ALIASING_POSSIBLE | |
186 | __flush_dcache_page(page_address(page), | |
187 | ((tlb_type == spitfire) && | |
188 | page_mapping(page) != NULL)); | |
189 | #else | |
190 | if (page_mapping(page) != NULL && | |
191 | tlb_type == spitfire) | |
192 | __flush_icache_page(__pa(page_address(page))); | |
193 | #endif | |
194 | } | |
195 | ||
196 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
197 | #define PG_dcache_cpu_shift 32UL |
198 | #define PG_dcache_cpu_mask \ | |
199 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
200 | |
201 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 202 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 203 | |
d979f179 | 204 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
205 | { |
206 | unsigned long mask = this_cpu; | |
48b0e548 DM |
207 | unsigned long non_cpu_bits; |
208 | ||
209 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
210 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
211 | ||
1da177e4 LT |
212 | __asm__ __volatile__("1:\n\t" |
213 | "ldx [%2], %%g7\n\t" | |
214 | "and %%g7, %1, %%g1\n\t" | |
215 | "or %%g1, %0, %%g1\n\t" | |
216 | "casx [%2], %%g7, %%g1\n\t" | |
217 | "cmp %%g7, %%g1\n\t" | |
218 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 219 | " nop" |
1da177e4 LT |
220 | : /* no outputs */ |
221 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
222 | : "g1", "g7"); | |
223 | } | |
224 | ||
d979f179 | 225 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
226 | { |
227 | unsigned long mask = (1UL << PG_dcache_dirty); | |
228 | ||
229 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
230 | "1:\n\t" | |
231 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 232 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
233 | "and %%g1, %3, %%g1\n\t" |
234 | "cmp %%g1, %0\n\t" | |
235 | "bne,pn %%icc, 2f\n\t" | |
236 | " andn %%g7, %1, %%g1\n\t" | |
237 | "casx [%2], %%g7, %%g1\n\t" | |
238 | "cmp %%g7, %%g1\n\t" | |
239 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 240 | " nop\n" |
1da177e4 LT |
241 | "2:" |
242 | : /* no outputs */ | |
243 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
244 | "i" (PG_dcache_cpu_mask), |
245 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
246 | : "g1", "g7"); |
247 | } | |
248 | ||
517af332 DM |
249 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
250 | { | |
251 | unsigned long tsb_addr = (unsigned long) ent; | |
252 | ||
3b3ab2eb | 253 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
254 | tsb_addr = __pa(tsb_addr); |
255 | ||
256 | __tsb_insert(tsb_addr, tag, pte); | |
257 | } | |
258 | ||
c4bce90e DM |
259 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
260 | unsigned long _PAGE_SZBITS __read_mostly; | |
261 | ||
ff9aefbf | 262 | static void flush_dcache(unsigned long pfn) |
1da177e4 | 263 | { |
ff9aefbf | 264 | struct page *page; |
7a591cfe | 265 | |
ff9aefbf | 266 | page = pfn_to_page(pfn); |
1a78cedb | 267 | if (page) { |
7a591cfe | 268 | unsigned long pg_flags; |
7a591cfe | 269 | |
ff9aefbf SR |
270 | pg_flags = page->flags; |
271 | if (pg_flags & (1UL << PG_dcache_dirty)) { | |
7a591cfe DM |
272 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & |
273 | PG_dcache_cpu_mask); | |
274 | int this_cpu = get_cpu(); | |
275 | ||
276 | /* This is just to optimize away some function calls | |
277 | * in the SMP case. | |
278 | */ | |
279 | if (cpu == this_cpu) | |
280 | flush_dcache_page_impl(page); | |
281 | else | |
282 | smp_flush_dcache_page_impl(page, cpu); | |
283 | ||
284 | clear_dcache_dirty_cpu(page, cpu); | |
285 | ||
286 | put_cpu(); | |
287 | } | |
1da177e4 | 288 | } |
ff9aefbf SR |
289 | } |
290 | ||
4b3073e1 | 291 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
ff9aefbf SR |
292 | { |
293 | struct mm_struct *mm; | |
294 | struct tsb *tsb; | |
295 | unsigned long tag, flags; | |
296 | unsigned long tsb_index, tsb_hash_shift; | |
4b3073e1 | 297 | pte_t pte = *ptep; |
ff9aefbf SR |
298 | |
299 | if (tlb_type != hypervisor) { | |
300 | unsigned long pfn = pte_pfn(pte); | |
301 | ||
302 | if (pfn_valid(pfn)) | |
303 | flush_dcache(pfn); | |
304 | } | |
bd40791e DM |
305 | |
306 | mm = vma->vm_mm; | |
7a1ac526 | 307 | |
dcc1e8dd DM |
308 | tsb_index = MM_TSB_BASE; |
309 | tsb_hash_shift = PAGE_SHIFT; | |
310 | ||
7a1ac526 DM |
311 | spin_lock_irqsave(&mm->context.lock, flags); |
312 | ||
dcc1e8dd DM |
313 | #ifdef CONFIG_HUGETLB_PAGE |
314 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) { | |
315 | if ((tlb_type == hypervisor && | |
316 | (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || | |
317 | (tlb_type != hypervisor && | |
318 | (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) { | |
319 | tsb_index = MM_TSB_HUGE; | |
320 | tsb_hash_shift = HPAGE_SHIFT; | |
321 | } | |
322 | } | |
323 | #endif | |
324 | ||
325 | tsb = mm->context.tsb_block[tsb_index].tsb; | |
326 | tsb += ((address >> tsb_hash_shift) & | |
327 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
74ae9987 DM |
328 | tag = (address >> 22UL); |
329 | tsb_insert(tsb, tag, pte_val(pte)); | |
7a1ac526 DM |
330 | |
331 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
332 | } |
333 | ||
334 | void flush_dcache_page(struct page *page) | |
335 | { | |
a9546f59 DM |
336 | struct address_space *mapping; |
337 | int this_cpu; | |
1da177e4 | 338 | |
7a591cfe DM |
339 | if (tlb_type == hypervisor) |
340 | return; | |
341 | ||
a9546f59 DM |
342 | /* Do not bother with the expensive D-cache flush if it |
343 | * is merely the zero page. The 'bigcore' testcase in GDB | |
344 | * causes this case to run millions of times. | |
345 | */ | |
346 | if (page == ZERO_PAGE(0)) | |
347 | return; | |
348 | ||
349 | this_cpu = get_cpu(); | |
350 | ||
351 | mapping = page_mapping(page); | |
1da177e4 | 352 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 353 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 354 | if (dirty) { |
a9546f59 DM |
355 | int dirty_cpu = dcache_dirty_cpu(page); |
356 | ||
1da177e4 LT |
357 | if (dirty_cpu == this_cpu) |
358 | goto out; | |
359 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
360 | } | |
361 | set_dcache_dirty(page, this_cpu); | |
362 | } else { | |
363 | /* We could delay the flush for the !page_mapping | |
364 | * case too. But that case is for exec env/arg | |
365 | * pages and those are %99 certainly going to get | |
366 | * faulted into the tlb (and thus flushed) anyways. | |
367 | */ | |
368 | flush_dcache_page_impl(page); | |
369 | } | |
370 | ||
371 | out: | |
372 | put_cpu(); | |
373 | } | |
917c3660 | 374 | EXPORT_SYMBOL(flush_dcache_page); |
1da177e4 | 375 | |
05e14cb3 | 376 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 377 | { |
a43fe0e7 | 378 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
379 | if (tlb_type == spitfire) { |
380 | unsigned long kaddr; | |
381 | ||
a94aa253 DM |
382 | /* This code only runs on Spitfire cpus so this is |
383 | * why we can assume _PAGE_PADDR_4U. | |
384 | */ | |
385 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
386 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
387 | ||
388 | if (kaddr >= PAGE_OFFSET) | |
389 | paddr = kaddr & mask; | |
390 | else { | |
391 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
392 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
393 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
394 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
395 | ||
396 | paddr = pte_val(*ptep) & mask; | |
397 | } | |
398 | __flush_icache_page(paddr); | |
399 | } | |
1da177e4 LT |
400 | } |
401 | } | |
917c3660 | 402 | EXPORT_SYMBOL(flush_icache_range); |
1da177e4 | 403 | |
1da177e4 LT |
404 | void mmu_info(struct seq_file *m) |
405 | { | |
406 | if (tlb_type == cheetah) | |
407 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
408 | else if (tlb_type == cheetah_plus) | |
409 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
410 | else if (tlb_type == spitfire) | |
411 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
412 | else if (tlb_type == hypervisor) |
413 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
414 | else |
415 | seq_printf(m, "MMU Type\t: ???\n"); | |
416 | ||
417 | #ifdef CONFIG_DEBUG_DCFLUSH | |
418 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
419 | atomic_read(&dcpage_flushes)); | |
420 | #ifdef CONFIG_SMP | |
421 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
422 | atomic_read(&dcpage_flushes_xcall)); | |
423 | #endif /* CONFIG_SMP */ | |
424 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
425 | } | |
426 | ||
a94aa253 DM |
427 | struct linux_prom_translation prom_trans[512] __read_mostly; |
428 | unsigned int prom_trans_ents __read_mostly; | |
429 | ||
1da177e4 LT |
430 | unsigned long kern_locked_tte_data; |
431 | ||
c9c10830 DM |
432 | /* The obp translations are saved based on 8k pagesize, since obp can |
433 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 434 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 435 | */ |
5085b4a5 DM |
436 | static inline int in_obp_range(unsigned long vaddr) |
437 | { | |
438 | return (vaddr >= LOW_OBP_ADDRESS && | |
439 | vaddr < HI_OBP_ADDRESS); | |
440 | } | |
441 | ||
c9c10830 | 442 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 443 | { |
c9c10830 | 444 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 445 | |
c9c10830 DM |
446 | if (x->virt > y->virt) |
447 | return 1; | |
448 | if (x->virt < y->virt) | |
449 | return -1; | |
450 | return 0; | |
405599bd DM |
451 | } |
452 | ||
c9c10830 | 453 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 454 | static void __init read_obp_translations(void) |
405599bd | 455 | { |
c9c10830 | 456 | int n, node, ents, first, last, i; |
1da177e4 LT |
457 | |
458 | node = prom_finddevice("/virtual-memory"); | |
459 | n = prom_getproplen(node, "translations"); | |
405599bd | 460 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 461 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
462 | prom_halt(); |
463 | } | |
405599bd DM |
464 | if (unlikely(n > sizeof(prom_trans))) { |
465 | prom_printf("prom_mappings: Size %Zd is too big.\n", n); | |
1da177e4 LT |
466 | prom_halt(); |
467 | } | |
405599bd | 468 | |
b206fc4c | 469 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
470 | (char *)&prom_trans[0], |
471 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 472 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
473 | prom_halt(); |
474 | } | |
9ad98c5b | 475 | |
b206fc4c | 476 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 477 | |
c9c10830 DM |
478 | ents = n; |
479 | ||
480 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
481 | cmp_ptrans, NULL); | |
482 | ||
483 | /* Now kick out all the non-OBP entries. */ | |
484 | for (i = 0; i < ents; i++) { | |
485 | if (in_obp_range(prom_trans[i].virt)) | |
486 | break; | |
487 | } | |
488 | first = i; | |
489 | for (; i < ents; i++) { | |
490 | if (!in_obp_range(prom_trans[i].virt)) | |
491 | break; | |
492 | } | |
493 | last = i; | |
494 | ||
495 | for (i = 0; i < (last - first); i++) { | |
496 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
497 | struct linux_prom_translation *dest = &prom_trans[i]; | |
498 | ||
499 | *dest = *src; | |
500 | } | |
501 | for (; i < ents; i++) { | |
502 | struct linux_prom_translation *dest = &prom_trans[i]; | |
503 | dest->virt = dest->size = dest->data = 0x0UL; | |
504 | } | |
505 | ||
506 | prom_trans_ents = last - first; | |
507 | ||
508 | if (tlb_type == spitfire) { | |
509 | /* Clear diag TTE bits. */ | |
510 | for (i = 0; i < prom_trans_ents; i++) | |
511 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
512 | } | |
f4142cba DM |
513 | |
514 | /* Force execute bit on. */ | |
515 | for (i = 0; i < prom_trans_ents; i++) | |
516 | prom_trans[i].data |= (tlb_type == hypervisor ? | |
517 | _PAGE_EXEC_4V : _PAGE_EXEC_4U); | |
405599bd | 518 | } |
1da177e4 | 519 | |
d82ace7d DM |
520 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
521 | unsigned long pte, | |
522 | unsigned long mmu) | |
523 | { | |
7db35f31 DM |
524 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
525 | ||
526 | if (ret != 0) { | |
12e126ad | 527 | prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: " |
7db35f31 | 528 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
529 | prom_halt(); |
530 | } | |
d82ace7d DM |
531 | } |
532 | ||
c4bce90e DM |
533 | static unsigned long kern_large_tte(unsigned long paddr); |
534 | ||
898cf0ec | 535 | static void __init remap_kernel(void) |
405599bd DM |
536 | { |
537 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 538 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 539 | |
1da177e4 | 540 | tte_vaddr = (unsigned long) KERNBASE; |
bff06d55 | 541 | phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
c4bce90e | 542 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
543 | |
544 | kern_locked_tte_data = tte_data; | |
545 | ||
d82ace7d DM |
546 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
547 | if (tlb_type == hypervisor) { | |
64658743 | 548 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
549 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
550 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
551 | tte_vaddr += 0x400000; |
552 | tte_data += 0x400000; | |
d82ace7d DM |
553 | } |
554 | } else { | |
64658743 DM |
555 | for (i = 0; i < num_kernel_image_mappings; i++) { |
556 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
557 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
558 | tte_vaddr += 0x400000; | |
559 | tte_data += 0x400000; | |
d82ace7d | 560 | } |
64658743 | 561 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 562 | } |
0835ae0f DM |
563 | if (tlb_type == cheetah_plus) { |
564 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
565 | CTX_CHEETAH_PLUS_NUC); | |
566 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
567 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
568 | } | |
405599bd | 569 | } |
1da177e4 | 570 | |
405599bd | 571 | |
c9c10830 | 572 | static void __init inherit_prom_mappings(void) |
9ad98c5b | 573 | { |
405599bd | 574 | /* Now fixup OBP's idea about where we really are mapped. */ |
3c62a2d3 | 575 | printk("Remapping the kernel... "); |
405599bd | 576 | remap_kernel(); |
3c62a2d3 | 577 | printk("done.\n"); |
1da177e4 LT |
578 | } |
579 | ||
1da177e4 LT |
580 | void prom_world(int enter) |
581 | { | |
1da177e4 LT |
582 | if (!enter) |
583 | set_fs((mm_segment_t) { get_thread_current_ds() }); | |
584 | ||
3487d1d4 | 585 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
586 | } |
587 | ||
1da177e4 LT |
588 | void __flush_dcache_range(unsigned long start, unsigned long end) |
589 | { | |
590 | unsigned long va; | |
591 | ||
592 | if (tlb_type == spitfire) { | |
593 | int n = 0; | |
594 | ||
595 | for (va = start; va < end; va += 32) { | |
596 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
597 | if (++n >= 512) | |
598 | break; | |
599 | } | |
a43fe0e7 | 600 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
601 | start = __pa(start); |
602 | end = __pa(end); | |
603 | for (va = start; va < end; va += 32) | |
604 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
605 | "membar #Sync" | |
606 | : /* no outputs */ | |
607 | : "r" (va), | |
608 | "i" (ASI_DCACHE_INVALIDATE)); | |
609 | } | |
610 | } | |
917c3660 | 611 | EXPORT_SYMBOL(__flush_dcache_range); |
1da177e4 | 612 | |
85f1e1f6 DM |
613 | /* get_new_mmu_context() uses "cache + 1". */ |
614 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
615 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
616 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) | |
617 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
618 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
619 | ||
1da177e4 LT |
620 | /* Caller does TLB context flushing on local CPU if necessary. |
621 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
622 | * | |
623 | * We must be careful about boundary cases so that we never | |
624 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
625 | * version of zero (and thus NO_CONTEXT would not be caught | |
626 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
627 | * |
628 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
629 | */ |
630 | void get_new_mmu_context(struct mm_struct *mm) | |
631 | { | |
632 | unsigned long ctx, new_ctx; | |
633 | unsigned long orig_pgsz_bits; | |
a77754b4 | 634 | unsigned long flags; |
a0663a79 | 635 | int new_version; |
1da177e4 | 636 | |
a77754b4 | 637 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
1da177e4 LT |
638 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
639 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
640 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 641 | new_version = 0; |
1da177e4 LT |
642 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
643 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
644 | if (new_ctx >= ctx) { | |
645 | int i; | |
646 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
647 | CTX_FIRST_VERSION; | |
648 | if (new_ctx == 1) | |
649 | new_ctx = CTX_FIRST_VERSION; | |
650 | ||
651 | /* Don't call memset, for 16 entries that's just | |
652 | * plain silly... | |
653 | */ | |
654 | mmu_context_bmap[0] = 3; | |
655 | mmu_context_bmap[1] = 0; | |
656 | mmu_context_bmap[2] = 0; | |
657 | mmu_context_bmap[3] = 0; | |
658 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
659 | mmu_context_bmap[i + 0] = 0; | |
660 | mmu_context_bmap[i + 1] = 0; | |
661 | mmu_context_bmap[i + 2] = 0; | |
662 | mmu_context_bmap[i + 3] = 0; | |
663 | } | |
a0663a79 | 664 | new_version = 1; |
1da177e4 LT |
665 | goto out; |
666 | } | |
667 | } | |
668 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
669 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
670 | out: | |
671 | tlb_context_cache = new_ctx; | |
672 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
a77754b4 | 673 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
a0663a79 DM |
674 | |
675 | if (unlikely(new_version)) | |
676 | smp_new_mmu_context_version(); | |
1da177e4 LT |
677 | } |
678 | ||
919ee677 DM |
679 | static int numa_enabled = 1; |
680 | static int numa_debug; | |
681 | ||
682 | static int __init early_numa(char *p) | |
1da177e4 | 683 | { |
919ee677 DM |
684 | if (!p) |
685 | return 0; | |
686 | ||
687 | if (strstr(p, "off")) | |
688 | numa_enabled = 0; | |
d1112018 | 689 | |
919ee677 DM |
690 | if (strstr(p, "debug")) |
691 | numa_debug = 1; | |
d1112018 | 692 | |
919ee677 | 693 | return 0; |
d1112018 | 694 | } |
919ee677 DM |
695 | early_param("numa", early_numa); |
696 | ||
697 | #define numadbg(f, a...) \ | |
698 | do { if (numa_debug) \ | |
699 | printk(KERN_INFO f, ## a); \ | |
700 | } while (0) | |
d1112018 | 701 | |
4e82c9a6 DM |
702 | static void __init find_ramdisk(unsigned long phys_base) |
703 | { | |
704 | #ifdef CONFIG_BLK_DEV_INITRD | |
705 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
706 | unsigned long ramdisk_image; | |
707 | ||
708 | /* Older versions of the bootloader only supported a | |
709 | * 32-bit physical address for the ramdisk image | |
710 | * location, stored at sparc_ramdisk_image. Newer | |
711 | * SILO versions set sparc_ramdisk_image to zero and | |
712 | * provide a full 64-bit physical address at | |
713 | * sparc_ramdisk_image64. | |
714 | */ | |
715 | ramdisk_image = sparc_ramdisk_image; | |
716 | if (!ramdisk_image) | |
717 | ramdisk_image = sparc_ramdisk_image64; | |
718 | ||
719 | /* Another bootloader quirk. The bootloader normalizes | |
720 | * the physical address to KERNBASE, so we have to | |
721 | * factor that back out and add in the lowest valid | |
722 | * physical page address to get the true physical address. | |
723 | */ | |
724 | ramdisk_image -= KERNBASE; | |
725 | ramdisk_image += phys_base; | |
726 | ||
919ee677 DM |
727 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
728 | ramdisk_image, sparc_ramdisk_size); | |
729 | ||
4e82c9a6 DM |
730 | initrd_start = ramdisk_image; |
731 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 | 732 | |
95f72d1e | 733 | memblock_reserve(initrd_start, sparc_ramdisk_size); |
d45100f7 DM |
734 | |
735 | initrd_start += PAGE_OFFSET; | |
736 | initrd_end += PAGE_OFFSET; | |
4e82c9a6 DM |
737 | } |
738 | #endif | |
739 | } | |
740 | ||
919ee677 DM |
741 | struct node_mem_mask { |
742 | unsigned long mask; | |
743 | unsigned long val; | |
919ee677 DM |
744 | }; |
745 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
746 | static int num_node_masks; | |
747 | ||
748 | int numa_cpu_lookup_table[NR_CPUS]; | |
749 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
750 | ||
751 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
919ee677 DM |
752 | |
753 | struct mdesc_mblock { | |
754 | u64 base; | |
755 | u64 size; | |
756 | u64 offset; /* RA-to-PA */ | |
757 | }; | |
758 | static struct mdesc_mblock *mblocks; | |
759 | static int num_mblocks; | |
760 | ||
761 | static unsigned long ra_to_pa(unsigned long addr) | |
762 | { | |
763 | int i; | |
764 | ||
765 | for (i = 0; i < num_mblocks; i++) { | |
766 | struct mdesc_mblock *m = &mblocks[i]; | |
767 | ||
768 | if (addr >= m->base && | |
769 | addr < (m->base + m->size)) { | |
770 | addr += m->offset; | |
771 | break; | |
772 | } | |
773 | } | |
774 | return addr; | |
775 | } | |
776 | ||
777 | static int find_node(unsigned long addr) | |
778 | { | |
779 | int i; | |
780 | ||
781 | addr = ra_to_pa(addr); | |
782 | for (i = 0; i < num_node_masks; i++) { | |
783 | struct node_mem_mask *p = &node_masks[i]; | |
784 | ||
785 | if ((addr & p->mask) == p->val) | |
786 | return i; | |
787 | } | |
788 | return -1; | |
789 | } | |
790 | ||
f9b18db3 | 791 | static u64 memblock_nid_range(u64 start, u64 end, int *nid) |
919ee677 DM |
792 | { |
793 | *nid = find_node(start); | |
794 | start += PAGE_SIZE; | |
795 | while (start < end) { | |
796 | int n = find_node(start); | |
797 | ||
798 | if (n != *nid) | |
799 | break; | |
800 | start += PAGE_SIZE; | |
801 | } | |
802 | ||
c918dcce DM |
803 | if (start > end) |
804 | start = end; | |
805 | ||
919ee677 DM |
806 | return start; |
807 | } | |
808 | #else | |
f9b18db3 | 809 | static u64 memblock_nid_range(u64 start, u64 end, int *nid) |
919ee677 DM |
810 | { |
811 | *nid = 0; | |
812 | return end; | |
813 | } | |
814 | #endif | |
815 | ||
816 | /* This must be invoked after performing all of the necessary | |
2a4814df | 817 | * memblock_set_node() calls for 'nid'. We need to be able to get |
919ee677 | 818 | * correct data from get_pfn_range_for_nid(). |
f1cfdb55 | 819 | */ |
919ee677 DM |
820 | static void __init allocate_node_data(int nid) |
821 | { | |
625d693e | 822 | unsigned long paddr, start_pfn, end_pfn; |
919ee677 DM |
823 | struct pglist_data *p; |
824 | ||
825 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
9d1e2492 | 826 | paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); |
919ee677 DM |
827 | if (!paddr) { |
828 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
829 | prom_halt(); | |
830 | } | |
831 | NODE_DATA(nid) = __va(paddr); | |
832 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
833 | ||
625d693e | 834 | NODE_DATA(nid)->node_id = nid; |
919ee677 DM |
835 | #endif |
836 | ||
837 | p = NODE_DATA(nid); | |
838 | ||
839 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
840 | p->node_start_pfn = start_pfn; | |
841 | p->node_spanned_pages = end_pfn - start_pfn; | |
919ee677 DM |
842 | } |
843 | ||
844 | static void init_node_masks_nonnuma(void) | |
d1112018 | 845 | { |
1da177e4 LT |
846 | int i; |
847 | ||
919ee677 | 848 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 849 | |
919ee677 DM |
850 | node_masks[0].mask = node_masks[0].val = 0; |
851 | num_node_masks = 1; | |
d1112018 | 852 | |
919ee677 DM |
853 | for (i = 0; i < NR_CPUS; i++) |
854 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 855 | |
fb1fece5 | 856 | cpumask_setall(&numa_cpumask_lookup_table[0]); |
919ee677 DM |
857 | } |
858 | ||
859 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
860 | struct pglist_data *node_data[MAX_NUMNODES]; | |
861 | ||
862 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
863 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
864 | EXPORT_SYMBOL(node_data); | |
865 | ||
866 | struct mdesc_mlgroup { | |
867 | u64 node; | |
868 | u64 latency; | |
869 | u64 match; | |
870 | u64 mask; | |
871 | }; | |
872 | static struct mdesc_mlgroup *mlgroups; | |
873 | static int num_mlgroups; | |
874 | ||
875 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, | |
876 | u32 cfg_handle) | |
877 | { | |
878 | u64 arc; | |
879 | ||
880 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
881 | u64 target = mdesc_arc_target(md, arc); | |
882 | const u64 *val; | |
883 | ||
884 | val = mdesc_get_property(md, target, | |
885 | "cfg-handle", NULL); | |
886 | if (val && *val == cfg_handle) | |
887 | return 0; | |
888 | } | |
889 | return -ENODEV; | |
890 | } | |
891 | ||
892 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
893 | u32 cfg_handle) | |
894 | { | |
895 | u64 arc, candidate, best_latency = ~(u64)0; | |
896 | ||
897 | candidate = MDESC_NODE_NULL; | |
898 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
899 | u64 target = mdesc_arc_target(md, arc); | |
900 | const char *name = mdesc_node_name(md, target); | |
901 | const u64 *val; | |
902 | ||
903 | if (strcmp(name, "pio-latency-group")) | |
904 | continue; | |
905 | ||
906 | val = mdesc_get_property(md, target, "latency", NULL); | |
907 | if (!val) | |
908 | continue; | |
909 | ||
910 | if (*val < best_latency) { | |
911 | candidate = target; | |
912 | best_latency = *val; | |
913 | } | |
914 | } | |
915 | ||
916 | if (candidate == MDESC_NODE_NULL) | |
917 | return -ENODEV; | |
918 | ||
919 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
920 | } | |
921 | ||
922 | int of_node_to_nid(struct device_node *dp) | |
923 | { | |
924 | const struct linux_prom64_registers *regs; | |
925 | struct mdesc_handle *md; | |
926 | u32 cfg_handle; | |
927 | int count, nid; | |
928 | u64 grp; | |
929 | ||
072bd413 DM |
930 | /* This is the right thing to do on currently supported |
931 | * SUN4U NUMA platforms as well, as the PCI controller does | |
932 | * not sit behind any particular memory controller. | |
933 | */ | |
919ee677 DM |
934 | if (!mlgroups) |
935 | return -1; | |
936 | ||
937 | regs = of_get_property(dp, "reg", NULL); | |
938 | if (!regs) | |
939 | return -1; | |
940 | ||
941 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
942 | ||
943 | md = mdesc_grab(); | |
944 | ||
945 | count = 0; | |
946 | nid = -1; | |
947 | mdesc_for_each_node_by_name(md, grp, "group") { | |
948 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
949 | nid = count; | |
950 | break; | |
951 | } | |
952 | count++; | |
953 | } | |
954 | ||
955 | mdesc_release(md); | |
956 | ||
957 | return nid; | |
958 | } | |
959 | ||
01c45381 | 960 | static void __init add_node_ranges(void) |
919ee677 | 961 | { |
08b84798 | 962 | struct memblock_region *reg; |
919ee677 | 963 | |
08b84798 BH |
964 | for_each_memblock(memory, reg) { |
965 | unsigned long size = reg->size; | |
919ee677 DM |
966 | unsigned long start, end; |
967 | ||
08b84798 | 968 | start = reg->base; |
919ee677 DM |
969 | end = start + size; |
970 | while (start < end) { | |
971 | unsigned long this_end; | |
972 | int nid; | |
973 | ||
35a1f0bd | 974 | this_end = memblock_nid_range(start, end, &nid); |
919ee677 | 975 | |
2a4814df | 976 | numadbg("Setting memblock NUMA node nid[%d] " |
919ee677 DM |
977 | "start[%lx] end[%lx]\n", |
978 | nid, start, this_end); | |
979 | ||
2a4814df | 980 | memblock_set_node(start, this_end - start, nid); |
919ee677 DM |
981 | start = this_end; |
982 | } | |
983 | } | |
984 | } | |
985 | ||
986 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
987 | { | |
988 | unsigned long paddr; | |
989 | int count = 0; | |
990 | u64 node; | |
991 | ||
992 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
993 | count++; | |
994 | if (!count) | |
995 | return -ENOENT; | |
996 | ||
95f72d1e | 997 | paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), |
919ee677 DM |
998 | SMP_CACHE_BYTES); |
999 | if (!paddr) | |
1000 | return -ENOMEM; | |
1001 | ||
1002 | mlgroups = __va(paddr); | |
1003 | num_mlgroups = count; | |
1004 | ||
1005 | count = 0; | |
1006 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1007 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1008 | const u64 *val; | |
1009 | ||
1010 | m->node = node; | |
1011 | ||
1012 | val = mdesc_get_property(md, node, "latency", NULL); | |
1013 | m->latency = *val; | |
1014 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1015 | m->match = *val; | |
1016 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1017 | m->mask = *val; | |
1018 | ||
90181136 SR |
1019 | numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " |
1020 | "match[%llx] mask[%llx]\n", | |
919ee677 DM |
1021 | count - 1, m->node, m->latency, m->match, m->mask); |
1022 | } | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1028 | { | |
1029 | unsigned long paddr; | |
1030 | int count = 0; | |
1031 | u64 node; | |
1032 | ||
1033 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1034 | count++; | |
1035 | if (!count) | |
1036 | return -ENOENT; | |
1037 | ||
95f72d1e | 1038 | paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), |
919ee677 DM |
1039 | SMP_CACHE_BYTES); |
1040 | if (!paddr) | |
1041 | return -ENOMEM; | |
1042 | ||
1043 | mblocks = __va(paddr); | |
1044 | num_mblocks = count; | |
1045 | ||
1046 | count = 0; | |
1047 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1048 | struct mdesc_mblock *m = &mblocks[count++]; | |
1049 | const u64 *val; | |
1050 | ||
1051 | val = mdesc_get_property(md, node, "base", NULL); | |
1052 | m->base = *val; | |
1053 | val = mdesc_get_property(md, node, "size", NULL); | |
1054 | m->size = *val; | |
1055 | val = mdesc_get_property(md, node, | |
1056 | "address-congruence-offset", NULL); | |
1057 | m->offset = *val; | |
1058 | ||
90181136 | 1059 | numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", |
919ee677 DM |
1060 | count - 1, m->base, m->size, m->offset); |
1061 | } | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1067 | u64 grp, cpumask_t *mask) | |
1068 | { | |
1069 | u64 arc; | |
1070 | ||
fb1fece5 | 1071 | cpumask_clear(mask); |
919ee677 DM |
1072 | |
1073 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1074 | u64 target = mdesc_arc_target(md, arc); | |
1075 | const char *name = mdesc_node_name(md, target); | |
1076 | const u64 *id; | |
1077 | ||
1078 | if (strcmp(name, "cpu")) | |
1079 | continue; | |
1080 | id = mdesc_get_property(md, target, "id", NULL); | |
e305cb8f | 1081 | if (*id < nr_cpu_ids) |
fb1fece5 | 1082 | cpumask_set_cpu(*id, mask); |
919ee677 DM |
1083 | } |
1084 | } | |
1085 | ||
1086 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1087 | { | |
1088 | int i; | |
1089 | ||
1090 | for (i = 0; i < num_mlgroups; i++) { | |
1091 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1092 | if (m->node == node) | |
1093 | return m; | |
1094 | } | |
1095 | return NULL; | |
1096 | } | |
1097 | ||
1098 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, | |
1099 | int index) | |
1100 | { | |
1101 | struct mdesc_mlgroup *candidate = NULL; | |
1102 | u64 arc, best_latency = ~(u64)0; | |
1103 | struct node_mem_mask *n; | |
1104 | ||
1105 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1106 | u64 target = mdesc_arc_target(md, arc); | |
1107 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1108 | if (!m) | |
1109 | continue; | |
1110 | if (m->latency < best_latency) { | |
1111 | candidate = m; | |
1112 | best_latency = m->latency; | |
1113 | } | |
1114 | } | |
1115 | if (!candidate) | |
1116 | return -ENOENT; | |
1117 | ||
1118 | if (num_node_masks != index) { | |
1119 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1120 | "index[%d] != num_node_masks[%d]\n", | |
1121 | index, num_node_masks); | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | ||
1125 | n = &node_masks[num_node_masks++]; | |
1126 | ||
1127 | n->mask = candidate->mask; | |
1128 | n->val = candidate->match; | |
1da177e4 | 1129 | |
90181136 | 1130 | numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n", |
919ee677 | 1131 | index, n->mask, n->val, candidate->latency); |
1da177e4 | 1132 | |
919ee677 DM |
1133 | return 0; |
1134 | } | |
1135 | ||
1136 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1137 | int index) | |
1138 | { | |
1139 | cpumask_t mask; | |
1140 | int cpu; | |
1141 | ||
1142 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1143 | ||
fb1fece5 | 1144 | for_each_cpu(cpu, &mask) |
919ee677 | 1145 | numa_cpu_lookup_table[cpu] = index; |
fb1fece5 | 1146 | cpumask_copy(&numa_cpumask_lookup_table[index], &mask); |
919ee677 DM |
1147 | |
1148 | if (numa_debug) { | |
1149 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
fb1fece5 | 1150 | for_each_cpu(cpu, &mask) |
919ee677 DM |
1151 | printk("%d ", cpu); |
1152 | printk("]\n"); | |
1153 | } | |
1154 | ||
1155 | return numa_attach_mlgroup(md, grp, index); | |
1156 | } | |
1157 | ||
1158 | static int __init numa_parse_mdesc(void) | |
1159 | { | |
1160 | struct mdesc_handle *md = mdesc_grab(); | |
1161 | int i, err, count; | |
1162 | u64 node; | |
1163 | ||
1164 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1165 | if (node == MDESC_NODE_NULL) { | |
1166 | mdesc_release(md); | |
1167 | return -ENOENT; | |
1168 | } | |
1169 | ||
1170 | err = grab_mblocks(md); | |
1171 | if (err < 0) | |
1172 | goto out; | |
1173 | ||
1174 | err = grab_mlgroups(md); | |
1175 | if (err < 0) | |
1176 | goto out; | |
1177 | ||
1178 | count = 0; | |
1179 | mdesc_for_each_node_by_name(md, node, "group") { | |
1180 | err = numa_parse_mdesc_group(md, node, count); | |
1181 | if (err < 0) | |
1182 | break; | |
1183 | count++; | |
1184 | } | |
1185 | ||
1186 | add_node_ranges(); | |
1187 | ||
1188 | for (i = 0; i < num_node_masks; i++) { | |
1189 | allocate_node_data(i); | |
1190 | node_set_online(i); | |
1191 | } | |
1192 | ||
1193 | err = 0; | |
1194 | out: | |
1195 | mdesc_release(md); | |
1196 | return err; | |
1197 | } | |
1198 | ||
072bd413 DM |
1199 | static int __init numa_parse_jbus(void) |
1200 | { | |
1201 | unsigned long cpu, index; | |
1202 | ||
1203 | /* NUMA node id is encoded in bits 36 and higher, and there is | |
1204 | * a 1-to-1 mapping from CPU ID to NUMA node ID. | |
1205 | */ | |
1206 | index = 0; | |
1207 | for_each_present_cpu(cpu) { | |
1208 | numa_cpu_lookup_table[cpu] = index; | |
fb1fece5 | 1209 | cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); |
072bd413 DM |
1210 | node_masks[index].mask = ~((1UL << 36UL) - 1UL); |
1211 | node_masks[index].val = cpu << 36UL; | |
1212 | ||
1213 | index++; | |
1214 | } | |
1215 | num_node_masks = index; | |
1216 | ||
1217 | add_node_ranges(); | |
1218 | ||
1219 | for (index = 0; index < num_node_masks; index++) { | |
1220 | allocate_node_data(index); | |
1221 | node_set_online(index); | |
1222 | } | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
919ee677 DM |
1227 | static int __init numa_parse_sun4u(void) |
1228 | { | |
072bd413 DM |
1229 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1230 | unsigned long ver; | |
1231 | ||
1232 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
1233 | if ((ver >> 32UL) == __JALAPENO_ID || | |
1234 | (ver >> 32UL) == __SERRANO_ID) | |
1235 | return numa_parse_jbus(); | |
1236 | } | |
919ee677 DM |
1237 | return -1; |
1238 | } | |
1239 | ||
1240 | static int __init bootmem_init_numa(void) | |
1241 | { | |
1242 | int err = -1; | |
1243 | ||
1244 | numadbg("bootmem_init_numa()\n"); | |
1245 | ||
1246 | if (numa_enabled) { | |
1247 | if (tlb_type == hypervisor) | |
1248 | err = numa_parse_mdesc(); | |
1249 | else | |
1250 | err = numa_parse_sun4u(); | |
1251 | } | |
1252 | return err; | |
1253 | } | |
1254 | ||
1255 | #else | |
1da177e4 | 1256 | |
919ee677 DM |
1257 | static int bootmem_init_numa(void) |
1258 | { | |
1259 | return -1; | |
1260 | } | |
1261 | ||
1262 | #endif | |
1263 | ||
1264 | static void __init bootmem_init_nonnuma(void) | |
1265 | { | |
95f72d1e YL |
1266 | unsigned long top_of_ram = memblock_end_of_DRAM(); |
1267 | unsigned long total_ram = memblock_phys_mem_size(); | |
919ee677 DM |
1268 | |
1269 | numadbg("bootmem_init_nonnuma()\n"); | |
1270 | ||
1271 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1272 | top_of_ram, total_ram); | |
1273 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1274 | (top_of_ram - total_ram) >> 20); | |
1275 | ||
1276 | init_node_masks_nonnuma(); | |
2a4814df | 1277 | memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0); |
919ee677 | 1278 | allocate_node_data(0); |
919ee677 DM |
1279 | node_set_online(0); |
1280 | } | |
1281 | ||
919ee677 DM |
1282 | static unsigned long __init bootmem_init(unsigned long phys_base) |
1283 | { | |
1284 | unsigned long end_pfn; | |
919ee677 | 1285 | |
95f72d1e | 1286 | end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; |
919ee677 DM |
1287 | max_pfn = max_low_pfn = end_pfn; |
1288 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1289 | ||
1290 | if (bootmem_init_numa() < 0) | |
1291 | bootmem_init_nonnuma(); | |
1292 | ||
625d693e DM |
1293 | /* Dump memblock with node info. */ |
1294 | memblock_dump_all(); | |
919ee677 | 1295 | |
625d693e | 1296 | /* XXX cpu notifier XXX */ |
d1112018 | 1297 | |
625d693e | 1298 | sparse_memory_present_with_active_regions(MAX_NUMNODES); |
d1112018 DM |
1299 | sparse_init(); |
1300 | ||
1da177e4 LT |
1301 | return end_pfn; |
1302 | } | |
1303 | ||
9cc3a1ac DM |
1304 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1305 | static int pall_ents __initdata; | |
1306 | ||
56425306 | 1307 | #ifdef CONFIG_DEBUG_PAGEALLOC |
896aef43 SR |
1308 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
1309 | unsigned long pend, pgprot_t prot) | |
56425306 DM |
1310 | { |
1311 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1312 | unsigned long vend = PAGE_OFFSET + pend; | |
1313 | unsigned long alloc_bytes = 0UL; | |
1314 | ||
1315 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1316 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1317 | vstart, vend); |
1318 | prom_halt(); | |
1319 | } | |
1320 | ||
1321 | while (vstart < vend) { | |
1322 | unsigned long this_end, paddr = __pa(vstart); | |
1323 | pgd_t *pgd = pgd_offset_k(vstart); | |
1324 | pud_t *pud; | |
1325 | pmd_t *pmd; | |
1326 | pte_t *pte; | |
1327 | ||
1328 | pud = pud_offset(pgd, vstart); | |
1329 | if (pud_none(*pud)) { | |
1330 | pmd_t *new; | |
1331 | ||
1332 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1333 | alloc_bytes += PAGE_SIZE; | |
1334 | pud_populate(&init_mm, pud, new); | |
1335 | } | |
1336 | ||
1337 | pmd = pmd_offset(pud, vstart); | |
1338 | if (!pmd_present(*pmd)) { | |
1339 | pte_t *new; | |
1340 | ||
1341 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1342 | alloc_bytes += PAGE_SIZE; | |
1343 | pmd_populate_kernel(&init_mm, pmd, new); | |
1344 | } | |
1345 | ||
1346 | pte = pte_offset_kernel(pmd, vstart); | |
1347 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1348 | if (this_end > vend) | |
1349 | this_end = vend; | |
1350 | ||
1351 | while (vstart < this_end) { | |
1352 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1353 | ||
1354 | vstart += PAGE_SIZE; | |
1355 | paddr += PAGE_SIZE; | |
1356 | pte++; | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | return alloc_bytes; | |
1361 | } | |
1362 | ||
56425306 | 1363 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac DM |
1364 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1365 | ||
1366 | static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) | |
1367 | { | |
1368 | const unsigned long shift_256MB = 28; | |
1369 | const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL); | |
1370 | const unsigned long size_256MB = (1UL << shift_256MB); | |
1371 | ||
1372 | while (start < end) { | |
1373 | long remains; | |
1374 | ||
f7c00338 DM |
1375 | remains = end - start; |
1376 | if (remains < size_256MB) | |
1377 | break; | |
1378 | ||
9cc3a1ac DM |
1379 | if (start & mask_256MB) { |
1380 | start = (start + size_256MB) & ~mask_256MB; | |
1381 | continue; | |
1382 | } | |
1383 | ||
9cc3a1ac DM |
1384 | while (remains >= size_256MB) { |
1385 | unsigned long index = start >> shift_256MB; | |
1386 | ||
1387 | __set_bit(index, kpte_linear_bitmap); | |
1388 | ||
1389 | start += size_256MB; | |
1390 | remains -= size_256MB; | |
1391 | } | |
1392 | } | |
1393 | } | |
56425306 | 1394 | |
8f361453 | 1395 | static void __init init_kpte_bitmap(void) |
56425306 | 1396 | { |
9cc3a1ac | 1397 | unsigned long i; |
13edad7a DM |
1398 | |
1399 | for (i = 0; i < pall_ents; i++) { | |
56425306 DM |
1400 | unsigned long phys_start, phys_end; |
1401 | ||
13edad7a DM |
1402 | phys_start = pall[i].phys_addr; |
1403 | phys_end = phys_start + pall[i].reg_size; | |
9cc3a1ac DM |
1404 | |
1405 | mark_kpte_bitmap(phys_start, phys_end); | |
8f361453 DM |
1406 | } |
1407 | } | |
9cc3a1ac | 1408 | |
8f361453 DM |
1409 | static void __init kernel_physical_mapping_init(void) |
1410 | { | |
9cc3a1ac | 1411 | #ifdef CONFIG_DEBUG_PAGEALLOC |
8f361453 DM |
1412 | unsigned long i, mem_alloced = 0UL; |
1413 | ||
1414 | for (i = 0; i < pall_ents; i++) { | |
1415 | unsigned long phys_start, phys_end; | |
1416 | ||
1417 | phys_start = pall[i].phys_addr; | |
1418 | phys_end = phys_start + pall[i].reg_size; | |
1419 | ||
56425306 DM |
1420 | mem_alloced += kernel_map_range(phys_start, phys_end, |
1421 | PAGE_KERNEL); | |
56425306 DM |
1422 | } |
1423 | ||
1424 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1425 | mem_alloced); | |
1426 | ||
1427 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1428 | flushi(&kvmap_linear_patch[0]); | |
1429 | ||
1430 | __flush_tlb_all(); | |
9cc3a1ac | 1431 | #endif |
56425306 DM |
1432 | } |
1433 | ||
9cc3a1ac | 1434 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1435 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1436 | { | |
1437 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1438 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1439 | ||
1440 | kernel_map_range(phys_start, phys_end, | |
1441 | (enable ? PAGE_KERNEL : __pgprot(0))); | |
1442 | ||
74bf4312 DM |
1443 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1444 | PAGE_OFFSET + phys_end); | |
1445 | ||
56425306 DM |
1446 | /* we should perform an IPI and flush all tlbs, |
1447 | * but that can deadlock->flush only current cpu. | |
1448 | */ | |
1449 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1450 | PAGE_OFFSET + phys_end); | |
1451 | } | |
1452 | #endif | |
1453 | ||
10147570 DM |
1454 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1455 | { | |
0836a0eb DM |
1456 | int i; |
1457 | ||
13edad7a DM |
1458 | for (i = 0; i < pavail_ents; i++) { |
1459 | if (pavail[i].reg_size >= size) | |
1460 | return pavail[i].phys_addr; | |
0836a0eb DM |
1461 | } |
1462 | ||
13edad7a | 1463 | return ~0UL; |
0836a0eb DM |
1464 | } |
1465 | ||
517af332 DM |
1466 | static void __init tsb_phys_patch(void) |
1467 | { | |
d257d5da | 1468 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1469 | struct tsb_phys_patch_entry *p; |
1470 | ||
d257d5da DM |
1471 | pquad = &__tsb_ldquad_phys_patch; |
1472 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1473 | unsigned long addr = pquad->addr; | |
1474 | ||
1475 | if (tlb_type == hypervisor) | |
1476 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1477 | else | |
1478 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1479 | wmb(); | |
1480 | __asm__ __volatile__("flush %0" | |
1481 | : /* no outputs */ | |
1482 | : "r" (addr)); | |
1483 | ||
1484 | pquad++; | |
1485 | } | |
1486 | ||
517af332 DM |
1487 | p = &__tsb_phys_patch; |
1488 | while (p < &__tsb_phys_patch_end) { | |
1489 | unsigned long addr = p->addr; | |
1490 | ||
1491 | *(unsigned int *) addr = p->insn; | |
1492 | wmb(); | |
1493 | __asm__ __volatile__("flush %0" | |
1494 | : /* no outputs */ | |
1495 | : "r" (addr)); | |
1496 | ||
1497 | p++; | |
1498 | } | |
1499 | } | |
1500 | ||
490384e7 | 1501 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1502 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1503 | #define NUM_KTSB_DESCR 2 | |
1504 | #else | |
1505 | #define NUM_KTSB_DESCR 1 | |
1506 | #endif | |
1507 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 DM |
1508 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
1509 | ||
9076d0e7 DM |
1510 | static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) |
1511 | { | |
1512 | pa >>= KTSB_PHYS_SHIFT; | |
1513 | ||
1514 | while (start < end) { | |
1515 | unsigned int *ia = (unsigned int *)(unsigned long)*start; | |
1516 | ||
1517 | ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10); | |
1518 | __asm__ __volatile__("flush %0" : : "r" (ia)); | |
1519 | ||
1520 | ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff); | |
1521 | __asm__ __volatile__("flush %0" : : "r" (ia + 1)); | |
1522 | ||
1523 | start++; | |
1524 | } | |
1525 | } | |
1526 | ||
1527 | static void ktsb_phys_patch(void) | |
1528 | { | |
1529 | extern unsigned int __swapper_tsb_phys_patch; | |
1530 | extern unsigned int __swapper_tsb_phys_patch_end; | |
9076d0e7 DM |
1531 | unsigned long ktsb_pa; |
1532 | ||
1533 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); | |
1534 | patch_one_ktsb_phys(&__swapper_tsb_phys_patch, | |
1535 | &__swapper_tsb_phys_patch_end, ktsb_pa); | |
1536 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
0785a8e8 DM |
1537 | { |
1538 | extern unsigned int __swapper_4m_tsb_phys_patch; | |
1539 | extern unsigned int __swapper_4m_tsb_phys_patch_end; | |
9076d0e7 DM |
1540 | ktsb_pa = (kern_base + |
1541 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1542 | patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, | |
1543 | &__swapper_4m_tsb_phys_patch_end, ktsb_pa); | |
0785a8e8 | 1544 | } |
9076d0e7 DM |
1545 | #endif |
1546 | } | |
1547 | ||
490384e7 DM |
1548 | static void __init sun4v_ktsb_init(void) |
1549 | { | |
1550 | unsigned long ktsb_pa; | |
1551 | ||
d7744a09 | 1552 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1553 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1554 | ||
1555 | switch (PAGE_SIZE) { | |
1556 | case 8 * 1024: | |
1557 | default: | |
1558 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1559 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1560 | break; | |
1561 | ||
1562 | case 64 * 1024: | |
1563 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1564 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1565 | break; | |
1566 | ||
1567 | case 512 * 1024: | |
1568 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1569 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1570 | break; | |
1571 | ||
1572 | case 4 * 1024 * 1024: | |
1573 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1574 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1575 | break; | |
6cb79b3f | 1576 | } |
490384e7 | 1577 | |
3f19a84e | 1578 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1579 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1580 | ktsb_descr[0].ctx_idx = 0; | |
1581 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1582 | ktsb_descr[0].resv = 0; | |
1583 | ||
d1acb421 | 1584 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 DM |
1585 | /* Second KTSB for 4MB/256MB mappings. */ |
1586 | ktsb_pa = (kern_base + | |
1587 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1588 | ||
1589 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1590 | ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB | | |
1591 | HV_PGSZ_MASK_256MB); | |
1592 | ktsb_descr[1].assoc = 1; | |
1593 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1594 | ktsb_descr[1].ctx_idx = 0; | |
1595 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1596 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1597 | #endif |
490384e7 DM |
1598 | } |
1599 | ||
1600 | void __cpuinit sun4v_ktsb_register(void) | |
1601 | { | |
7db35f31 | 1602 | unsigned long pa, ret; |
490384e7 DM |
1603 | |
1604 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1605 | ||
7db35f31 DM |
1606 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
1607 | if (ret != 0) { | |
1608 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
1609 | "errors with %lx\n", pa, ret); | |
1610 | prom_halt(); | |
1611 | } | |
490384e7 DM |
1612 | } |
1613 | ||
1da177e4 LT |
1614 | /* paging_init() sets up the page tables */ |
1615 | ||
1da177e4 | 1616 | static unsigned long last_valid_pfn; |
56425306 | 1617 | pgd_t swapper_pg_dir[2048]; |
1da177e4 | 1618 | |
c4bce90e DM |
1619 | static void sun4u_pgprot_init(void); |
1620 | static void sun4v_pgprot_init(void); | |
1621 | ||
1da177e4 LT |
1622 | void __init paging_init(void) |
1623 | { | |
919ee677 | 1624 | unsigned long end_pfn, shift, phys_base; |
0836a0eb DM |
1625 | unsigned long real_end, i; |
1626 | ||
22adb358 DM |
1627 | /* These build time checkes make sure that the dcache_dirty_cpu() |
1628 | * page->flags usage will work. | |
1629 | * | |
1630 | * When a page gets marked as dcache-dirty, we store the | |
1631 | * cpu number starting at bit 32 in the page->flags. Also, | |
1632 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
1633 | * in 13-bit signed-immediate instruction fields. | |
1634 | */ | |
9223b419 CL |
1635 | |
1636 | /* | |
1637 | * Page flags must not reach into upper 32 bits that are used | |
1638 | * for the cpu number | |
1639 | */ | |
1640 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
1641 | ||
1642 | /* | |
1643 | * The bit fields placed in the high range must not reach below | |
1644 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
1645 | * at the 32 bit boundary. | |
1646 | */ | |
22adb358 | 1647 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
1648 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
1649 | ||
22adb358 DM |
1650 | BUILD_BUG_ON(NR_CPUS > 4096); |
1651 | ||
481295f9 DM |
1652 | kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
1653 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; | |
1654 | ||
d7744a09 | 1655 | /* Invalidate both kernel TSBs. */ |
8b234274 | 1656 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 1657 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 1658 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 1659 | #endif |
8b234274 | 1660 | |
c4bce90e DM |
1661 | if (tlb_type == hypervisor) |
1662 | sun4v_pgprot_init(); | |
1663 | else | |
1664 | sun4u_pgprot_init(); | |
1665 | ||
d257d5da | 1666 | if (tlb_type == cheetah_plus || |
9076d0e7 | 1667 | tlb_type == hypervisor) { |
517af332 | 1668 | tsb_phys_patch(); |
9076d0e7 DM |
1669 | ktsb_phys_patch(); |
1670 | } | |
517af332 | 1671 | |
490384e7 | 1672 | if (tlb_type == hypervisor) { |
d257d5da | 1673 | sun4v_patch_tlb_handlers(); |
490384e7 DM |
1674 | sun4v_ktsb_init(); |
1675 | } | |
d257d5da | 1676 | |
a94a172d DM |
1677 | /* Find available physical memory... |
1678 | * | |
1679 | * Read it twice in order to work around a bug in openfirmware. | |
1680 | * The call to grab this table itself can cause openfirmware to | |
1681 | * allocate memory, which in turn can take away some space from | |
1682 | * the list of available memory. Reading it twice makes sure | |
1683 | * we really do get the final value. | |
1684 | */ | |
1685 | read_obp_translations(); | |
1686 | read_obp_memory("reg", &pall[0], &pall_ents); | |
1687 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
13edad7a | 1688 | read_obp_memory("available", &pavail[0], &pavail_ents); |
0836a0eb DM |
1689 | |
1690 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 1691 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 1692 | phys_base = min(phys_base, pavail[i].phys_addr); |
95f72d1e | 1693 | memblock_add(pavail[i].phys_addr, pavail[i].reg_size); |
3b2a7e23 DM |
1694 | } |
1695 | ||
95f72d1e | 1696 | memblock_reserve(kern_base, kern_size); |
0836a0eb | 1697 | |
4e82c9a6 DM |
1698 | find_ramdisk(phys_base); |
1699 | ||
95f72d1e | 1700 | memblock_enforce_memory_limit(cmdline_memory_size); |
25b0c659 | 1701 | |
1aadc056 | 1702 | memblock_allow_resize(); |
95f72d1e | 1703 | memblock_dump_all(); |
3b2a7e23 | 1704 | |
1da177e4 LT |
1705 | set_bit(0, mmu_context_bmap); |
1706 | ||
2bdb3cb2 DM |
1707 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
1708 | ||
1da177e4 | 1709 | real_end = (unsigned long)_end; |
64658743 DM |
1710 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22); |
1711 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", | |
1712 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
1713 | |
1714 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
1715 | * work. |
1716 | */ | |
1717 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
1718 | ||
56425306 | 1719 | memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); |
1da177e4 LT |
1720 | |
1721 | /* Now can init the kernel/bad page tables. */ | |
1722 | pud_set(pud_offset(&swapper_pg_dir[0], 0), | |
56425306 | 1723 | swapper_low_pmd_dir + (shift / sizeof(pgd_t))); |
1da177e4 | 1724 | |
c9c10830 | 1725 | inherit_prom_mappings(); |
5085b4a5 | 1726 | |
8f361453 DM |
1727 | init_kpte_bitmap(); |
1728 | ||
a8b900d8 DM |
1729 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
1730 | setup_tba(); | |
1da177e4 | 1731 | |
c9c10830 | 1732 | __flush_tlb_all(); |
9ad98c5b | 1733 | |
490384e7 DM |
1734 | if (tlb_type == hypervisor) |
1735 | sun4v_ktsb_register(); | |
1736 | ||
ad072004 | 1737 | prom_build_devicetree(); |
b696fdc2 | 1738 | of_populate_present_mask(); |
b99c6ebe DM |
1739 | #ifndef CONFIG_SMP |
1740 | of_fill_in_cpu_data(); | |
1741 | #endif | |
ad072004 | 1742 | |
890db403 | 1743 | if (tlb_type == hypervisor) { |
4a283339 | 1744 | sun4v_mdesc_init(); |
6ac5c610 | 1745 | mdesc_populate_present_mask(cpu_all_mask); |
b99c6ebe DM |
1746 | #ifndef CONFIG_SMP |
1747 | mdesc_fill_in_cpu_data(cpu_all_mask); | |
1748 | #endif | |
890db403 | 1749 | } |
4a283339 | 1750 | |
4f70f7a9 DM |
1751 | /* Once the OF device tree and MDESC have been setup, we know |
1752 | * the list of possible cpus. Therefore we can allocate the | |
1753 | * IRQ stacks. | |
1754 | */ | |
1755 | for_each_possible_cpu(i) { | |
1756 | /* XXX Use node local allocations... XXX */ | |
95f72d1e YL |
1757 | softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
1758 | hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); | |
4f70f7a9 DM |
1759 | } |
1760 | ||
2bdb3cb2 | 1761 | /* Setup bootmem... */ |
919ee677 | 1762 | last_valid_pfn = end_pfn = bootmem_init(phys_base); |
d1112018 | 1763 | |
919ee677 | 1764 | #ifndef CONFIG_NEED_MULTIPLE_NODES |
17b0e199 | 1765 | max_mapnr = last_valid_pfn; |
919ee677 | 1766 | #endif |
56425306 | 1767 | kernel_physical_mapping_init(); |
56425306 | 1768 | |
1da177e4 | 1769 | { |
919ee677 | 1770 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 1771 | |
919ee677 | 1772 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 1773 | |
919ee677 | 1774 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 1775 | |
919ee677 | 1776 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
1777 | } |
1778 | ||
3c62a2d3 | 1779 | printk("Booting Linux...\n"); |
1da177e4 LT |
1780 | } |
1781 | ||
9a2ed5cc | 1782 | int __devinit page_in_phys_avail(unsigned long paddr) |
919ee677 DM |
1783 | { |
1784 | int i; | |
1785 | ||
1786 | paddr &= PAGE_MASK; | |
1787 | ||
1788 | for (i = 0; i < pavail_ents; i++) { | |
1789 | unsigned long start, end; | |
1790 | ||
1791 | start = pavail[i].phys_addr; | |
1792 | end = start + pavail[i].reg_size; | |
1793 | ||
1794 | if (paddr >= start && paddr < end) | |
1795 | return 1; | |
1796 | } | |
1797 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
1798 | return 1; | |
1799 | #ifdef CONFIG_BLK_DEV_INITRD | |
1800 | if (paddr >= __pa(initrd_start) && | |
1801 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
1802 | return 1; | |
1803 | #endif | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; | |
1809 | static int pavail_rescan_ents __initdata; | |
1810 | ||
1811 | /* Certain OBP calls, such as fetching "available" properties, can | |
1812 | * claim physical memory. So, along with initializing the valid | |
1813 | * address bitmap, what we do here is refetch the physical available | |
1814 | * memory list again, and make sure it provides at least as much | |
1815 | * memory as 'pavail' does. | |
1816 | */ | |
d8ed1d43 | 1817 | static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap) |
1da177e4 | 1818 | { |
1da177e4 LT |
1819 | int i; |
1820 | ||
13edad7a | 1821 | read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); |
1da177e4 | 1822 | |
13edad7a | 1823 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 LT |
1824 | unsigned long old_start, old_end; |
1825 | ||
13edad7a | 1826 | old_start = pavail[i].phys_addr; |
919ee677 | 1827 | old_end = old_start + pavail[i].reg_size; |
1da177e4 LT |
1828 | while (old_start < old_end) { |
1829 | int n; | |
1830 | ||
c2a5a46b | 1831 | for (n = 0; n < pavail_rescan_ents; n++) { |
1da177e4 LT |
1832 | unsigned long new_start, new_end; |
1833 | ||
13edad7a DM |
1834 | new_start = pavail_rescan[n].phys_addr; |
1835 | new_end = new_start + | |
1836 | pavail_rescan[n].reg_size; | |
1da177e4 LT |
1837 | |
1838 | if (new_start <= old_start && | |
1839 | new_end >= (old_start + PAGE_SIZE)) { | |
d8ed1d43 | 1840 | set_bit(old_start >> 22, bitmap); |
1da177e4 LT |
1841 | goto do_next_page; |
1842 | } | |
1843 | } | |
919ee677 DM |
1844 | |
1845 | prom_printf("mem_init: Lost memory in pavail\n"); | |
1846 | prom_printf("mem_init: OLD start[%lx] size[%lx]\n", | |
1847 | pavail[i].phys_addr, | |
1848 | pavail[i].reg_size); | |
1849 | prom_printf("mem_init: NEW start[%lx] size[%lx]\n", | |
1850 | pavail_rescan[i].phys_addr, | |
1851 | pavail_rescan[i].reg_size); | |
1852 | prom_printf("mem_init: Cannot continue, aborting.\n"); | |
1853 | prom_halt(); | |
1da177e4 LT |
1854 | |
1855 | do_next_page: | |
1856 | old_start += PAGE_SIZE; | |
1857 | } | |
1858 | } | |
1859 | } | |
1860 | ||
d8ed1d43 DM |
1861 | static void __init patch_tlb_miss_handler_bitmap(void) |
1862 | { | |
1863 | extern unsigned int valid_addr_bitmap_insn[]; | |
1864 | extern unsigned int valid_addr_bitmap_patch[]; | |
1865 | ||
1866 | valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1]; | |
1867 | mb(); | |
1868 | valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0]; | |
1869 | flushi(&valid_addr_bitmap_insn[0]); | |
1870 | } | |
1871 | ||
1da177e4 LT |
1872 | void __init mem_init(void) |
1873 | { | |
1874 | unsigned long codepages, datapages, initpages; | |
1875 | unsigned long addr, last; | |
1da177e4 LT |
1876 | |
1877 | addr = PAGE_OFFSET + kern_base; | |
1878 | last = PAGE_ALIGN(kern_size) + addr; | |
1879 | while (addr < last) { | |
1880 | set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); | |
1881 | addr += PAGE_SIZE; | |
1882 | } | |
1883 | ||
d8ed1d43 DM |
1884 | setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap); |
1885 | patch_tlb_miss_handler_bitmap(); | |
1da177e4 | 1886 | |
1da177e4 LT |
1887 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
1888 | ||
919ee677 | 1889 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
d8ed1d43 DM |
1890 | { |
1891 | int i; | |
1892 | for_each_online_node(i) { | |
1893 | if (NODE_DATA(i)->node_spanned_pages != 0) { | |
1894 | totalram_pages += | |
1895 | free_all_bootmem_node(NODE_DATA(i)); | |
1896 | } | |
919ee677 | 1897 | } |
625d693e | 1898 | totalram_pages += free_low_memory_core_early(MAX_NUMNODES); |
919ee677 DM |
1899 | } |
1900 | #else | |
1901 | totalram_pages = free_all_bootmem(); | |
1902 | #endif | |
1903 | ||
f1cfdb55 DM |
1904 | /* We subtract one to account for the mem_map_zero page |
1905 | * allocated below. | |
1906 | */ | |
919ee677 DM |
1907 | totalram_pages -= 1; |
1908 | num_physpages = totalram_pages; | |
1da177e4 LT |
1909 | |
1910 | /* | |
1911 | * Set up the zero page, mark it reserved, so that page count | |
1912 | * is not manipulated when freeing the page from user ptes. | |
1913 | */ | |
1914 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
1915 | if (mem_map_zero == NULL) { | |
1916 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
1917 | prom_halt(); | |
1918 | } | |
1919 | SetPageReserved(mem_map_zero); | |
1920 | ||
1921 | codepages = (((unsigned long) _etext) - ((unsigned long) _start)); | |
1922 | codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; | |
1923 | datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); | |
1924 | datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; | |
1925 | initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); | |
1926 | initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; | |
1927 | ||
96177299 | 1928 | printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", |
1da177e4 LT |
1929 | nr_free_pages() << (PAGE_SHIFT-10), |
1930 | codepages << (PAGE_SHIFT-10), | |
1931 | datapages << (PAGE_SHIFT-10), | |
1932 | initpages << (PAGE_SHIFT-10), | |
1933 | PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); | |
1934 | ||
1935 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
1936 | cheetah_ecache_flush_init(); | |
1937 | } | |
1938 | ||
898cf0ec | 1939 | void free_initmem(void) |
1da177e4 LT |
1940 | { |
1941 | unsigned long addr, initend; | |
f2b60794 DM |
1942 | int do_free = 1; |
1943 | ||
1944 | /* If the physical memory maps were trimmed by kernel command | |
1945 | * line options, don't even try freeing this initmem stuff up. | |
1946 | * The kernel image could have been in the trimmed out region | |
1947 | * and if so the freeing below will free invalid page structs. | |
1948 | */ | |
1949 | if (cmdline_memory_size) | |
1950 | do_free = 0; | |
1da177e4 LT |
1951 | |
1952 | /* | |
1953 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
1954 | */ | |
1955 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
1956 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
1957 | for (; addr < initend; addr += PAGE_SIZE) { | |
1958 | unsigned long page; | |
1959 | struct page *p; | |
1960 | ||
1961 | page = (addr + | |
1962 | ((unsigned long) __va(kern_base)) - | |
1963 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 1964 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 | 1965 | |
f2b60794 DM |
1966 | if (do_free) { |
1967 | p = virt_to_page(page); | |
1968 | ||
1969 | ClearPageReserved(p); | |
1970 | init_page_count(p); | |
1971 | __free_page(p); | |
1972 | num_physpages++; | |
1973 | totalram_pages++; | |
1974 | } | |
1da177e4 LT |
1975 | } |
1976 | } | |
1977 | ||
1978 | #ifdef CONFIG_BLK_DEV_INITRD | |
1979 | void free_initrd_mem(unsigned long start, unsigned long end) | |
1980 | { | |
1981 | if (start < end) | |
1982 | printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); | |
1983 | for (; start < end; start += PAGE_SIZE) { | |
1984 | struct page *p = virt_to_page(start); | |
1985 | ||
1986 | ClearPageReserved(p); | |
7835e98b | 1987 | init_page_count(p); |
1da177e4 LT |
1988 | __free_page(p); |
1989 | num_physpages++; | |
1990 | totalram_pages++; | |
1991 | } | |
1992 | } | |
1993 | #endif | |
c4bce90e | 1994 | |
c4bce90e DM |
1995 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
1996 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
1997 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
1998 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
1999 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2000 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2001 | ||
2002 | pgprot_t PAGE_KERNEL __read_mostly; | |
2003 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2004 | ||
2005 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2006 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2007 | |
2008 | pgprot_t PAGE_SHARED __read_mostly; | |
2009 | EXPORT_SYMBOL(PAGE_SHARED); | |
2010 | ||
c4bce90e DM |
2011 | unsigned long pg_iobits __read_mostly; |
2012 | ||
2013 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2014 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2015 | |
c4bce90e | 2016 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2017 | EXPORT_SYMBOL(_PAGE_E); |
2018 | ||
c4bce90e | 2019 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2020 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2021 | |
46644c24 | 2022 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
46644c24 DM |
2023 | unsigned long vmemmap_table[VMEMMAP_SIZE]; |
2024 | ||
2025 | int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node) | |
2026 | { | |
2027 | unsigned long vstart = (unsigned long) start; | |
2028 | unsigned long vend = (unsigned long) (start + nr); | |
2029 | unsigned long phys_start = (vstart - VMEMMAP_BASE); | |
2030 | unsigned long phys_end = (vend - VMEMMAP_BASE); | |
2031 | unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK; | |
2032 | unsigned long end = VMEMMAP_ALIGN(phys_end); | |
2033 | unsigned long pte_base; | |
2034 | ||
2035 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2036 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2037 | _PAGE_P_4U | _PAGE_W_4U); | |
2038 | if (tlb_type == hypervisor) | |
2039 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2040 | _PAGE_CP_4V | _PAGE_CV_4V | | |
2041 | _PAGE_P_4V | _PAGE_W_4V); | |
2042 | ||
2043 | for (; addr < end; addr += VMEMMAP_CHUNK) { | |
2044 | unsigned long *vmem_pp = | |
2045 | vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT); | |
2046 | void *block; | |
2047 | ||
2048 | if (!(*vmem_pp & _PAGE_VALID)) { | |
2049 | block = vmemmap_alloc_block(1UL << 22, node); | |
2050 | if (!block) | |
2051 | return -ENOMEM; | |
2052 | ||
2053 | *vmem_pp = pte_base | __pa(block); | |
2054 | ||
2055 | printk(KERN_INFO "[%p-%p] page_structs=%lu " | |
2056 | "node=%d entry=%lu/%lu\n", start, block, nr, | |
2057 | node, | |
2058 | addr >> VMEMMAP_CHUNK_SHIFT, | |
33cd9dfa | 2059 | VMEMMAP_SIZE); |
46644c24 DM |
2060 | } |
2061 | } | |
2062 | return 0; | |
2063 | } | |
2064 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
2065 | ||
c4bce90e DM |
2066 | static void prot_init_common(unsigned long page_none, |
2067 | unsigned long page_shared, | |
2068 | unsigned long page_copy, | |
2069 | unsigned long page_readonly, | |
2070 | unsigned long page_exec_bit) | |
2071 | { | |
2072 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2073 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2074 | |
2075 | protection_map[0x0] = __pgprot(page_none); | |
2076 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2077 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2078 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2079 | protection_map[0x4] = __pgprot(page_readonly); | |
2080 | protection_map[0x5] = __pgprot(page_readonly); | |
2081 | protection_map[0x6] = __pgprot(page_copy); | |
2082 | protection_map[0x7] = __pgprot(page_copy); | |
2083 | protection_map[0x8] = __pgprot(page_none); | |
2084 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2085 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2086 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2087 | protection_map[0xc] = __pgprot(page_readonly); | |
2088 | protection_map[0xd] = __pgprot(page_readonly); | |
2089 | protection_map[0xe] = __pgprot(page_shared); | |
2090 | protection_map[0xf] = __pgprot(page_shared); | |
2091 | } | |
2092 | ||
2093 | static void __init sun4u_pgprot_init(void) | |
2094 | { | |
2095 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2096 | unsigned long page_exec_bit; | |
2097 | ||
2098 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2099 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2100 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2101 | _PAGE_EXEC_4U); | |
2102 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2103 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2104 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2105 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
c4bce90e DM |
2106 | |
2107 | _PAGE_IE = _PAGE_IE_4U; | |
2108 | _PAGE_E = _PAGE_E_4U; | |
2109 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2110 | ||
2111 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2112 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2113 | ||
d1acb421 DM |
2114 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2115 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ | |
af1ee569 | 2116 | 0xfffff80000000000UL; |
d1acb421 | 2117 | #else |
9cc3a1ac | 2118 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
af1ee569 | 2119 | 0xfffff80000000000UL; |
d1acb421 | 2120 | #endif |
9cc3a1ac DM |
2121 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2122 | _PAGE_P_4U | _PAGE_W_4U); | |
2123 | ||
2124 | /* XXX Should use 256MB on Panther. XXX */ | |
2125 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
c4bce90e DM |
2126 | |
2127 | _PAGE_SZBITS = _PAGE_SZBITS_4U; | |
2128 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | | |
2129 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2130 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2131 | ||
2132 | ||
2133 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2134 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2135 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2136 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2137 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2138 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2139 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2140 | ||
2141 | page_exec_bit = _PAGE_EXEC_4U; | |
2142 | ||
2143 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2144 | page_exec_bit); | |
2145 | } | |
2146 | ||
2147 | static void __init sun4v_pgprot_init(void) | |
2148 | { | |
2149 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2150 | unsigned long page_exec_bit; | |
2151 | ||
2152 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
2153 | _PAGE_CACHE_4V | _PAGE_P_4V | | |
2154 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | | |
2155 | _PAGE_EXEC_4V); | |
2156 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
c4bce90e DM |
2157 | |
2158 | _PAGE_IE = _PAGE_IE_4V; | |
2159 | _PAGE_E = _PAGE_E_4V; | |
2160 | _PAGE_CACHE = _PAGE_CACHE_4V; | |
2161 | ||
d1acb421 DM |
2162 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2163 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
af1ee569 | 2164 | 0xfffff80000000000UL; |
d1acb421 | 2165 | #else |
9cc3a1ac | 2166 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
af1ee569 | 2167 | 0xfffff80000000000UL; |
d1acb421 | 2168 | #endif |
9cc3a1ac DM |
2169 | kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2170 | _PAGE_P_4V | _PAGE_W_4V); | |
2171 | ||
d1acb421 DM |
2172 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2173 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
af1ee569 | 2174 | 0xfffff80000000000UL; |
d1acb421 | 2175 | #else |
9cc3a1ac | 2176 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ |
af1ee569 | 2177 | 0xfffff80000000000UL; |
d1acb421 | 2178 | #endif |
9cc3a1ac DM |
2179 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2180 | _PAGE_P_4V | _PAGE_W_4V); | |
c4bce90e DM |
2181 | |
2182 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | | |
2183 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2184 | ||
2185 | _PAGE_SZBITS = _PAGE_SZBITS_4V; | |
2186 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | | |
2187 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2188 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2189 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2190 | ||
2191 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; | |
2192 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2193 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); | |
2194 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2195 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2196 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2197 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2198 | ||
2199 | page_exec_bit = _PAGE_EXEC_4V; | |
2200 | ||
2201 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2202 | page_exec_bit); | |
2203 | } | |
2204 | ||
2205 | unsigned long pte_sz_bits(unsigned long sz) | |
2206 | { | |
2207 | if (tlb_type == hypervisor) { | |
2208 | switch (sz) { | |
2209 | case 8 * 1024: | |
2210 | default: | |
2211 | return _PAGE_SZ8K_4V; | |
2212 | case 64 * 1024: | |
2213 | return _PAGE_SZ64K_4V; | |
2214 | case 512 * 1024: | |
2215 | return _PAGE_SZ512K_4V; | |
2216 | case 4 * 1024 * 1024: | |
2217 | return _PAGE_SZ4MB_4V; | |
6cb79b3f | 2218 | } |
c4bce90e DM |
2219 | } else { |
2220 | switch (sz) { | |
2221 | case 8 * 1024: | |
2222 | default: | |
2223 | return _PAGE_SZ8K_4U; | |
2224 | case 64 * 1024: | |
2225 | return _PAGE_SZ64K_4U; | |
2226 | case 512 * 1024: | |
2227 | return _PAGE_SZ512K_4U; | |
2228 | case 4 * 1024 * 1024: | |
2229 | return _PAGE_SZ4MB_4U; | |
6cb79b3f | 2230 | } |
c4bce90e DM |
2231 | } |
2232 | } | |
2233 | ||
2234 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2235 | { | |
2236 | pte_t pte; | |
cf627156 DM |
2237 | |
2238 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2239 | pte_val(pte) |= (((unsigned long)space) << 32); |
2240 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2241 | |
cf627156 | 2242 | return pte; |
c4bce90e DM |
2243 | } |
2244 | ||
2245 | static unsigned long kern_large_tte(unsigned long paddr) | |
2246 | { | |
2247 | unsigned long val; | |
2248 | ||
2249 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2250 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2251 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2252 | if (tlb_type == hypervisor) | |
2253 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2254 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | | |
2255 | _PAGE_EXEC_4V | _PAGE_W_4V); | |
2256 | ||
2257 | return val | paddr; | |
2258 | } | |
2259 | ||
c4bce90e DM |
2260 | /* If not locked, zap it. */ |
2261 | void __flush_tlb_all(void) | |
2262 | { | |
2263 | unsigned long pstate; | |
2264 | int i; | |
2265 | ||
2266 | __asm__ __volatile__("flushw\n\t" | |
2267 | "rdpr %%pstate, %0\n\t" | |
2268 | "wrpr %0, %1, %%pstate" | |
2269 | : "=r" (pstate) | |
2270 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2271 | if (tlb_type == hypervisor) { |
2272 | sun4v_mmu_demap_all(); | |
2273 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2274 | for (i = 0; i < 64; i++) { |
2275 | /* Spitfire Errata #32 workaround */ | |
2276 | /* NOTE: Always runs on spitfire, so no | |
2277 | * cheetah+ page size encodings. | |
2278 | */ | |
2279 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2280 | "flush %%g6" | |
2281 | : /* No outputs */ | |
2282 | : "r" (0), | |
2283 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2284 | ||
2285 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2286 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2287 | "membar #Sync" | |
2288 | : /* no outputs */ | |
2289 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2290 | spitfire_put_dtlb_data(i, 0x0UL); | |
2291 | } | |
2292 | ||
2293 | /* Spitfire Errata #32 workaround */ | |
2294 | /* NOTE: Always runs on spitfire, so no | |
2295 | * cheetah+ page size encodings. | |
2296 | */ | |
2297 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2298 | "flush %%g6" | |
2299 | : /* No outputs */ | |
2300 | : "r" (0), | |
2301 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2302 | ||
2303 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2304 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2305 | "membar #Sync" | |
2306 | : /* no outputs */ | |
2307 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2308 | spitfire_put_itlb_data(i, 0x0UL); | |
2309 | } | |
2310 | } | |
2311 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2312 | cheetah_flush_dtlb_all(); | |
2313 | cheetah_flush_itlb_all(); | |
2314 | } | |
2315 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2316 | : : "r" (pstate)); | |
2317 | } |