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powerpc: Use HAVE_MEMBLOCK_NODE_MAP
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc / mm / init_64.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
1da177e4
LT		 16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
c9cf5528 19#include <linux/poison.h>
1da177e4
LT		 20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
5cbc3073 25#include <linux/percpu.h>
95f72d1e 26#include <linux/memblock.h>
919ee677 27#include <linux/mmzone.h>
5a0e3ad6 28#include <linux/gfp.h>
1da177e4
LT		 29
30#include <asm/head.h>
31#include <asm/system.h>
32#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
517af332 46#include <asm/tsb.h>
481295f9 47#include <asm/hypervisor.h>
372b07bb 48#include <asm/prom.h>
5cbc3073 49#include <asm/mdesc.h>
3d5ae6b6 50#include <asm/cpudata.h>
4f70f7a9 51#include <asm/irq.h>
1da177e4 52
27137e52 53#include "init_64.h"
9cc3a1ac
DM		 54
55unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57/* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
d1acb421 63#ifndef CONFIG_DEBUG_PAGEALLOC
2d9e2763
DM		 64/* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 69#endif
d7744a09 70
13edad7a
DM		 71#define MAX_BANKS 32
72
9a2ed5cc
DM		 73static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
74static int pavail_ents __devinitdata;
13edad7a
DM		 75
76static int cmp_p64(const void *a, const void *b)
77{
78 const struct linux_prom64_registers *x = a, *y = b;
79
80 if (x->phys_addr > y->phys_addr)
81 return 1;
82 if (x->phys_addr < y->phys_addr)
83 return -1;
84 return 0;
85}
86
87static void __init read_obp_memory(const char *property,
88 struct linux_prom64_registers *regs,
89 int *num_ents)
90{
8d125562 91 phandle node = prom_finddevice("/memory");
13edad7a
DM		 92 int prop_size = prom_getproplen(node, property);
93 int ents, ret, i;
94
95 ents = prop_size / sizeof(struct linux_prom64_registers);
96 if (ents > MAX_BANKS) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
99 property, MAX_BANKS);
100 prom_halt();
101 }
102
103 ret = prom_getproperty(node, property, (char *) regs, prop_size);
104 if (ret == -1) {
105 prom_printf("Couldn't get %s property from /memory.\n");
106 prom_halt();
107 }
108
13edad7a
DM		 109 /* Sanitize what we got from the firmware, by page aligning
110 * everything.
111 */
112 for (i = 0; i < ents; i++) {
113 unsigned long base, size;
114
115 base = regs[i].phys_addr;
116 size = regs[i].reg_size;
10147570 117
13edad7a
DM		 118 size &= PAGE_MASK;
119 if (base & ~PAGE_MASK) {
120 unsigned long new_base = PAGE_ALIGN(base);
121
122 size -= new_base - base;
123 if ((long) size < 0L)
124 size = 0UL;
125 base = new_base;
126 }
0015d3d6
DM		 127 if (size == 0UL) {
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
131 */
132 memmove(&regs[i], &regs[i + 1],
133 (ents - i - 1) * sizeof(regs[0]));
486ad10a 134 i--;
0015d3d6
DM		 135 ents--;
136 continue;
486ad10a 137 }
0015d3d6
DM		 138 regs[i].phys_addr = base;
139 regs[i].reg_size = size;
486ad10a
DM		 140 }
141
142 *num_ents = ents;
143
c9c10830 144 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 145 cmp_p64, NULL);
146}
1da177e4 147
d8ed1d43
DM		 148unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
149 sizeof(unsigned long)];
917c3660 150EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
1da177e4 151
d1112018 152/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 153unsigned long kern_base __read_mostly;
154unsigned long kern_size __read_mostly;
1da177e4 155
1da177e4
LT		 156/* Initial ramdisk setup */
157extern unsigned long sparc_ramdisk_image64;
158extern unsigned int sparc_ramdisk_image;
159extern unsigned int sparc_ramdisk_size;
160
1ac4f5eb 161struct page *mem_map_zero __read_mostly;
35802c0b 162EXPORT_SYMBOL(mem_map_zero);
1da177e4 163
0835ae0f
DM		 164unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166unsigned long sparc64_kern_pri_context __read_mostly;
167unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168unsigned long sparc64_kern_sec_context __read_mostly;
169
64658743 170int num_kernel_image_mappings;
1da177e4 171
1da177e4
LT		 172#ifdef CONFIG_DEBUG_DCFLUSH
173atomic_t dcpage_flushes = ATOMIC_INIT(0);
174#ifdef CONFIG_SMP
175atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176#endif
177#endif
178
7a591cfe 179inline void flush_dcache_page_impl(struct page *page)
1da177e4 180{
7a591cfe 181 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 182#ifdef CONFIG_DEBUG_DCFLUSH
183 atomic_inc(&dcpage_flushes);
184#endif
185
186#ifdef DCACHE_ALIASING_POSSIBLE
187 __flush_dcache_page(page_address(page),
188 ((tlb_type == spitfire) &&
189 page_mapping(page) != NULL));
190#else
191 if (page_mapping(page) != NULL &&
192 tlb_type == spitfire)
193 __flush_icache_page(__pa(page_address(page)));
194#endif
195}
196
197#define PG_dcache_dirty PG_arch_1
22adb358
DM		 198#define PG_dcache_cpu_shift 32UL
199#define PG_dcache_cpu_mask \
200 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 201
202#define dcache_dirty_cpu(page) \
48b0e548 203 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 204
d979f179 205static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 206{
207 unsigned long mask = this_cpu;
48b0e548
DM		 208 unsigned long non_cpu_bits;
209
210 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
1da177e4
LT		 213 __asm__ __volatile__("1:\n\t"
214 "ldx [%2], %%g7\n\t"
215 "and %%g7, %1, %%g1\n\t"
216 "or %%g1, %0, %%g1\n\t"
217 "casx [%2], %%g7, %%g1\n\t"
218 "cmp %%g7, %%g1\n\t"
219 "bne,pn %%xcc, 1b\n\t"
b445e26c 220 " nop"
1da177e4
LT		 221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224}
225
d979f179 226static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 227{
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
48b0e548 233 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "bne,pn %%xcc, 1b\n\t"
b445e26c 241 " nop\n"
1da177e4
LT		 242 "2:"
243 : /* no outputs */
244 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 245 "i" (PG_dcache_cpu_mask),
246 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 247 : "g1", "g7");
248}
249
517af332
DM		 250static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251{
252 unsigned long tsb_addr = (unsigned long) ent;
253
3b3ab2eb 254 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 255 tsb_addr = __pa(tsb_addr);
256
257 __tsb_insert(tsb_addr, tag, pte);
258}
259
c4bce90e
DM		 260unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
261unsigned long _PAGE_SZBITS __read_mostly;
262
ff9aefbf 263static void flush_dcache(unsigned long pfn)
1da177e4 264{
ff9aefbf 265 struct page *page;
7a591cfe 266
ff9aefbf 267 page = pfn_to_page(pfn);
1a78cedb 268 if (page) {
7a591cfe 269 unsigned long pg_flags;
7a591cfe 270
ff9aefbf
SR		 271 pg_flags = page->flags;
272 if (pg_flags & (1UL << PG_dcache_dirty)) {
7a591cfe
DM		 273 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
274 PG_dcache_cpu_mask);
275 int this_cpu = get_cpu();
276
277 /* This is just to optimize away some function calls
278 * in the SMP case.
279 */
280 if (cpu == this_cpu)
281 flush_dcache_page_impl(page);
282 else
283 smp_flush_dcache_page_impl(page, cpu);
284
285 clear_dcache_dirty_cpu(page, cpu);
286
287 put_cpu();
288 }
1da177e4 289 }
ff9aefbf
SR		 290}
291
4b3073e1 292void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
ff9aefbf
SR		 293{
294 struct mm_struct *mm;
295 struct tsb *tsb;
296 unsigned long tag, flags;
297 unsigned long tsb_index, tsb_hash_shift;
4b3073e1 298 pte_t pte = *ptep;
ff9aefbf
SR		 299
300 if (tlb_type != hypervisor) {
301 unsigned long pfn = pte_pfn(pte);
302
303 if (pfn_valid(pfn))
304 flush_dcache(pfn);
305 }
bd40791e
DM		 306
307 mm = vma->vm_mm;
7a1ac526 308
dcc1e8dd
DM		 309 tsb_index = MM_TSB_BASE;
310 tsb_hash_shift = PAGE_SHIFT;
311
7a1ac526
DM		 312 spin_lock_irqsave(&mm->context.lock, flags);
313
dcc1e8dd
DM		 314#ifdef CONFIG_HUGETLB_PAGE
315 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
316 if ((tlb_type == hypervisor &&
317 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
318 (tlb_type != hypervisor &&
319 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
320 tsb_index = MM_TSB_HUGE;
321 tsb_hash_shift = HPAGE_SHIFT;
322 }
323 }
324#endif
325
326 tsb = mm->context.tsb_block[tsb_index].tsb;
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 331
332 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 333}
334
335void flush_dcache_page(struct page *page)
336{
a9546f59
DM		 337 struct address_space *mapping;
338 int this_cpu;
1da177e4 339
7a591cfe
DM		 340 if (tlb_type == hypervisor)
341 return;
342
a9546f59
DM		 343 /* Do not bother with the expensive D-cache flush if it
344 * is merely the zero page. The 'bigcore' testcase in GDB
345 * causes this case to run millions of times.
346 */
347 if (page == ZERO_PAGE(0))
348 return;
349
350 this_cpu = get_cpu();
351
352 mapping = page_mapping(page);
1da177e4 353 if (mapping && !mapping_mapped(mapping)) {
a9546f59 354 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 355 if (dirty) {
a9546f59
DM		 356 int dirty_cpu = dcache_dirty_cpu(page);
357
1da177e4
LT		 358 if (dirty_cpu == this_cpu)
359 goto out;
360 smp_flush_dcache_page_impl(page, dirty_cpu);
361 }
362 set_dcache_dirty(page, this_cpu);
363 } else {
364 /* We could delay the flush for the !page_mapping
365 * case too. But that case is for exec env/arg
366 * pages and those are %99 certainly going to get
367 * faulted into the tlb (and thus flushed) anyways.
368 */
369 flush_dcache_page_impl(page);
370 }
371
372out:
373 put_cpu();
374}
917c3660 375EXPORT_SYMBOL(flush_dcache_page);
1da177e4 376
05e14cb3 377void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 378{
a43fe0e7 379 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 380 if (tlb_type == spitfire) {
381 unsigned long kaddr;
382
a94aa253
DM		 383 /* This code only runs on Spitfire cpus so this is
384 * why we can assume _PAGE_PADDR_4U.
385 */
386 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
387 unsigned long paddr, mask = _PAGE_PADDR_4U;
388
389 if (kaddr >= PAGE_OFFSET)
390 paddr = kaddr & mask;
391 else {
392 pgd_t *pgdp = pgd_offset_k(kaddr);
393 pud_t *pudp = pud_offset(pgdp, kaddr);
394 pmd_t *pmdp = pmd_offset(pudp, kaddr);
395 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
396
397 paddr = pte_val(*ptep) & mask;
398 }
399 __flush_icache_page(paddr);
400 }
1da177e4
LT		 401 }
402}
917c3660 403EXPORT_SYMBOL(flush_icache_range);
1da177e4 404
1da177e4
LT		 405void mmu_info(struct seq_file *m)
406{
407 if (tlb_type == cheetah)
408 seq_printf(m, "MMU Type\t: Cheetah\n");
409 else if (tlb_type == cheetah_plus)
410 seq_printf(m, "MMU Type\t: Cheetah+\n");
411 else if (tlb_type == spitfire)
412 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 413 else if (tlb_type == hypervisor)
414 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 415 else
416 seq_printf(m, "MMU Type\t: ???\n");
417
418#ifdef CONFIG_DEBUG_DCFLUSH
419 seq_printf(m, "DCPageFlushes\t: %d\n",
420 atomic_read(&dcpage_flushes));
421#ifdef CONFIG_SMP
422 seq_printf(m, "DCPageFlushesXC\t: %d\n",
423 atomic_read(&dcpage_flushes_xcall));
424#endif /* CONFIG_SMP */
425#endif /* CONFIG_DEBUG_DCFLUSH */
426}
427
a94aa253
DM		 428struct linux_prom_translation prom_trans[512] __read_mostly;
429unsigned int prom_trans_ents __read_mostly;
430
1da177e4
LT		 431unsigned long kern_locked_tte_data;
432
c9c10830
DM		 433/* The obp translations are saved based on 8k pagesize, since obp can
434 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 435 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 436 */
5085b4a5
DM		 437static inline int in_obp_range(unsigned long vaddr)
438{
439 return (vaddr >= LOW_OBP_ADDRESS &&
440 vaddr < HI_OBP_ADDRESS);
441}
442
c9c10830 443static int cmp_ptrans(const void *a, const void *b)
405599bd 444{
c9c10830 445 const struct linux_prom_translation *x = a, *y = b;
405599bd 446
c9c10830
DM		 447 if (x->virt > y->virt)
448 return 1;
449 if (x->virt < y->virt)
450 return -1;
451 return 0;
405599bd
DM		 452}
453
c9c10830 454/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 455static void __init read_obp_translations(void)
405599bd 456{
c9c10830 457 int n, node, ents, first, last, i;
1da177e4
LT		 458
459 node = prom_finddevice("/virtual-memory");
460 n = prom_getproplen(node, "translations");
405599bd 461 if (unlikely(n == 0 || n == -1)) {
b206fc4c 462 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 463 prom_halt();
464 }
405599bd
DM		 465 if (unlikely(n > sizeof(prom_trans))) {
466 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 467 prom_halt();
468 }
405599bd 469
b206fc4c 470 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 471 (char *)&prom_trans[0],
472 sizeof(prom_trans))) == -1) {
b206fc4c 473 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 474 prom_halt();
475 }
9ad98c5b 476
b206fc4c 477 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 478
c9c10830
DM		 479 ents = n;
480
481 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
482 cmp_ptrans, NULL);
483
484 /* Now kick out all the non-OBP entries. */
485 for (i = 0; i < ents; i++) {
486 if (in_obp_range(prom_trans[i].virt))
487 break;
488 }
489 first = i;
490 for (; i < ents; i++) {
491 if (!in_obp_range(prom_trans[i].virt))
492 break;
493 }
494 last = i;
495
496 for (i = 0; i < (last - first); i++) {
497 struct linux_prom_translation *src = &prom_trans[i + first];
498 struct linux_prom_translation *dest = &prom_trans[i];
499
500 *dest = *src;
501 }
502 for (; i < ents; i++) {
503 struct linux_prom_translation *dest = &prom_trans[i];
504 dest->virt = dest->size = dest->data = 0x0UL;
505 }
506
507 prom_trans_ents = last - first;
508
509 if (tlb_type == spitfire) {
510 /* Clear diag TTE bits. */
511 for (i = 0; i < prom_trans_ents; i++)
512 prom_trans[i].data &= ~0x0003fe0000000000UL;
513 }
f4142cba
DM		 514
515 /* Force execute bit on. */
516 for (i = 0; i < prom_trans_ents; i++)
517 prom_trans[i].data |= (tlb_type == hypervisor ?
518 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
405599bd 519}
1da177e4 520
d82ace7d
DM		 521static void __init hypervisor_tlb_lock(unsigned long vaddr,
522 unsigned long pte,
523 unsigned long mmu)
524{
7db35f31
DM		 525 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
526
527 if (ret != 0) {
12e126ad 528 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
7db35f31 529 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 530 prom_halt();
531 }
d82ace7d
DM		 532}
533
c4bce90e
DM		 534static unsigned long kern_large_tte(unsigned long paddr);
535
898cf0ec 536static void __init remap_kernel(void)
405599bd
DM		 537{
538 unsigned long phys_page, tte_vaddr, tte_data;
64658743 539 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 540
1da177e4 541 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 542 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 543 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 544
545 kern_locked_tte_data = tte_data;
546
d82ace7d
DM		 547 /* Now lock us into the TLBs via Hypervisor or OBP. */
548 if (tlb_type == hypervisor) {
64658743 549 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 550 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
551 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 552 tte_vaddr += 0x400000;
553 tte_data += 0x400000;
d82ace7d
DM		 554 }
555 } else {
64658743
DM		 556 for (i = 0; i < num_kernel_image_mappings; i++) {
557 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
558 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
559 tte_vaddr += 0x400000;
560 tte_data += 0x400000;
d82ace7d 561 }
64658743 562 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 563 }
0835ae0f
DM		 564 if (tlb_type == cheetah_plus) {
565 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
566 CTX_CHEETAH_PLUS_NUC);
567 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
568 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
569 }
405599bd 570}
1da177e4 571
405599bd 572
c9c10830 573static void __init inherit_prom_mappings(void)
9ad98c5b 574{
405599bd 575 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 576 printk("Remapping the kernel... ");
405599bd 577 remap_kernel();
3c62a2d3 578 printk("done.\n");
1da177e4
LT		 579}
580
1da177e4
LT		 581void prom_world(int enter)
582{
1da177e4
LT		 583 if (!enter)
584 set_fs((mm_segment_t) { get_thread_current_ds() });
585
3487d1d4 586 __asm__ __volatile__("flushw");
1da177e4
LT		 587}
588
1da177e4
LT		 589void __flush_dcache_range(unsigned long start, unsigned long end)
590{
591 unsigned long va;
592
593 if (tlb_type == spitfire) {
594 int n = 0;
595
596 for (va = start; va < end; va += 32) {
597 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
598 if (++n >= 512)
599 break;
600 }
a43fe0e7 601 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 602 start = __pa(start);
603 end = __pa(end);
604 for (va = start; va < end; va += 32)
605 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
606 "membar #Sync"
607 : /* no outputs */
608 : "r" (va),
609 "i" (ASI_DCACHE_INVALIDATE));
610 }
611}
917c3660 612EXPORT_SYMBOL(__flush_dcache_range);
1da177e4 613
85f1e1f6
DM		 614/* get_new_mmu_context() uses "cache + 1". */
615DEFINE_SPINLOCK(ctx_alloc_lock);
616unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
617#define MAX_CTX_NR (1UL << CTX_NR_BITS)
618#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
619DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
620
1da177e4
LT		 621/* Caller does TLB context flushing on local CPU if necessary.
622 * The caller also ensures that CTX_VALID(mm->context) is false.
623 *
624 * We must be careful about boundary cases so that we never
625 * let the user have CTX 0 (nucleus) or we ever use a CTX
626 * version of zero (and thus NO_CONTEXT would not be caught
627 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 628 *
629 * Always invoked with interrupts disabled.
1da177e4
LT		 630 */
631void get_new_mmu_context(struct mm_struct *mm)
632{
633 unsigned long ctx, new_ctx;
634 unsigned long orig_pgsz_bits;
a77754b4 635 unsigned long flags;
a0663a79 636 int new_version;
1da177e4 637
a77754b4 638 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 639 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
640 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
641 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 642 new_version = 0;
1da177e4
LT		 643 if (new_ctx >= (1 << CTX_NR_BITS)) {
644 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
645 if (new_ctx >= ctx) {
646 int i;
647 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
648 CTX_FIRST_VERSION;
649 if (new_ctx == 1)
650 new_ctx = CTX_FIRST_VERSION;
651
652 /* Don't call memset, for 16 entries that's just
653 * plain silly...
654 */
655 mmu_context_bmap[0] = 3;
656 mmu_context_bmap[1] = 0;
657 mmu_context_bmap[2] = 0;
658 mmu_context_bmap[3] = 0;
659 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
660 mmu_context_bmap[i + 0] = 0;
661 mmu_context_bmap[i + 1] = 0;
662 mmu_context_bmap[i + 2] = 0;
663 mmu_context_bmap[i + 3] = 0;
664 }
a0663a79 665 new_version = 1;
1da177e4
LT		 666 goto out;
667 }
668 }
669 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
670 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
671out:
672 tlb_context_cache = new_ctx;
673 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 674 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 675
676 if (unlikely(new_version))
677 smp_new_mmu_context_version();
1da177e4
LT		 678}
679
919ee677
DM		 680static int numa_enabled = 1;
681static int numa_debug;
682
683static int __init early_numa(char *p)
1da177e4 684{
919ee677
DM		 685 if (!p)
686 return 0;
687
688 if (strstr(p, "off"))
689 numa_enabled = 0;
d1112018 690
919ee677
DM		 691 if (strstr(p, "debug"))
692 numa_debug = 1;
d1112018 693
919ee677 694 return 0;
d1112018 695}
919ee677
DM		 696early_param("numa", early_numa);
697
698#define numadbg(f, a...) \
699do { if (numa_debug) \
700 printk(KERN_INFO f, ## a); \
701} while (0)
d1112018 702
4e82c9a6
DM		 703static void __init find_ramdisk(unsigned long phys_base)
704{
705#ifdef CONFIG_BLK_DEV_INITRD
706 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
707 unsigned long ramdisk_image;
708
709 /* Older versions of the bootloader only supported a
710 * 32-bit physical address for the ramdisk image
711 * location, stored at sparc_ramdisk_image. Newer
712 * SILO versions set sparc_ramdisk_image to zero and
713 * provide a full 64-bit physical address at
714 * sparc_ramdisk_image64.
715 */
716 ramdisk_image = sparc_ramdisk_image;
717 if (!ramdisk_image)
718 ramdisk_image = sparc_ramdisk_image64;
719
720 /* Another bootloader quirk. The bootloader normalizes
721 * the physical address to KERNBASE, so we have to
722 * factor that back out and add in the lowest valid
723 * physical page address to get the true physical address.
724 */
725 ramdisk_image -= KERNBASE;
726 ramdisk_image += phys_base;
727
919ee677
DM		 728 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
729 ramdisk_image, sparc_ramdisk_size);
730
4e82c9a6
DM		 731 initrd_start = ramdisk_image;
732 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23 733
95f72d1e 734 memblock_reserve(initrd_start, sparc_ramdisk_size);
d45100f7
DM		 735
736 initrd_start += PAGE_OFFSET;
737 initrd_end += PAGE_OFFSET;
4e82c9a6
DM		 738 }
739#endif
740}
741
919ee677
DM		 742struct node_mem_mask {
743 unsigned long mask;
744 unsigned long val;
745 unsigned long bootmem_paddr;
746};
747static struct node_mem_mask node_masks[MAX_NUMNODES];
748static int num_node_masks;
749
750int numa_cpu_lookup_table[NR_CPUS];
751cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
752
753#ifdef CONFIG_NEED_MULTIPLE_NODES
919ee677
DM		 754
755struct mdesc_mblock {
756 u64 base;
757 u64 size;
758 u64 offset; /* RA-to-PA */
759};
760static struct mdesc_mblock *mblocks;
761static int num_mblocks;
762
763static unsigned long ra_to_pa(unsigned long addr)
764{
765 int i;
766
767 for (i = 0; i < num_mblocks; i++) {
768 struct mdesc_mblock *m = &mblocks[i];
769
770 if (addr >= m->base &&
771 addr < (m->base + m->size)) {
772 addr += m->offset;
773 break;
774 }
775 }
776 return addr;
777}
778
779static int find_node(unsigned long addr)
780{
781 int i;
782
783 addr = ra_to_pa(addr);
784 for (i = 0; i < num_node_masks; i++) {
785 struct node_mem_mask *p = &node_masks[i];
786
787 if ((addr & p->mask) == p->val)
788 return i;
789 }
790 return -1;
791}
792
f9b18db3 793static u64 memblock_nid_range(u64 start, u64 end, int *nid)
919ee677
DM		 794{
795 *nid = find_node(start);
796 start += PAGE_SIZE;
797 while (start < end) {
798 int n = find_node(start);
799
800 if (n != *nid)
801 break;
802 start += PAGE_SIZE;
803 }
804
c918dcce
DM		 805 if (start > end)
806 start = end;
807
919ee677
DM		 808 return start;
809}
810#else
f9b18db3 811static u64 memblock_nid_range(u64 start, u64 end, int *nid)
919ee677
DM		 812{
813 *nid = 0;
814 return end;
815}
816#endif
817
818/* This must be invoked after performing all of the necessary
819 * add_active_range() calls for 'nid'. We need to be able to get
820 * correct data from get_pfn_range_for_nid().
f1cfdb55 821 */
919ee677
DM		 822static void __init allocate_node_data(int nid)
823{
824 unsigned long paddr, num_pages, start_pfn, end_pfn;
825 struct pglist_data *p;
826
827#ifdef CONFIG_NEED_MULTIPLE_NODES
9d1e2492 828 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
919ee677
DM		 829 if (!paddr) {
830 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
831 prom_halt();
832 }
833 NODE_DATA(nid) = __va(paddr);
834 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
835
b61bfa3c 836 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
919ee677
DM		 837#endif
838
839 p = NODE_DATA(nid);
840
841 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
842 p->node_start_pfn = start_pfn;
843 p->node_spanned_pages = end_pfn - start_pfn;
844
845 if (p->node_spanned_pages) {
846 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
847
9d1e2492 848 paddr = memblock_alloc_try_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid);
919ee677
DM		 849 if (!paddr) {
850 prom_printf("Cannot allocate bootmap for nid[%d]\n",
851 nid);
852 prom_halt();
853 }
854 node_masks[nid].bootmem_paddr = paddr;
855 }
856}
857
858static void init_node_masks_nonnuma(void)
d1112018 859{
1da177e4
LT		 860 int i;
861
919ee677 862 numadbg("Initializing tables for non-numa.\n");
6fc5bae7 863
919ee677
DM		 864 node_masks[0].mask = node_masks[0].val = 0;
865 num_node_masks = 1;
d1112018 866
919ee677
DM		 867 for (i = 0; i < NR_CPUS; i++)
868 numa_cpu_lookup_table[i] = 0;
1da177e4 869
fb1fece5 870 cpumask_setall(&numa_cpumask_lookup_table[0]);
919ee677
DM		 871}
872
873#ifdef CONFIG_NEED_MULTIPLE_NODES
874struct pglist_data *node_data[MAX_NUMNODES];
875
876EXPORT_SYMBOL(numa_cpu_lookup_table);
877EXPORT_SYMBOL(numa_cpumask_lookup_table);
878EXPORT_SYMBOL(node_data);
879
880struct mdesc_mlgroup {
881 u64 node;
882 u64 latency;
883 u64 match;
884 u64 mask;
885};
886static struct mdesc_mlgroup *mlgroups;
887static int num_mlgroups;
888
889static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
890 u32 cfg_handle)
891{
892 u64 arc;
893
894 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
895 u64 target = mdesc_arc_target(md, arc);
896 const u64 *val;
897
898 val = mdesc_get_property(md, target,
899 "cfg-handle", NULL);
900 if (val && *val == cfg_handle)
901 return 0;
902 }
903 return -ENODEV;
904}
905
906static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
907 u32 cfg_handle)
908{
909 u64 arc, candidate, best_latency = ~(u64)0;
910
911 candidate = MDESC_NODE_NULL;
912 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
913 u64 target = mdesc_arc_target(md, arc);
914 const char *name = mdesc_node_name(md, target);
915 const u64 *val;
916
917 if (strcmp(name, "pio-latency-group"))
918 continue;
919
920 val = mdesc_get_property(md, target, "latency", NULL);
921 if (!val)
922 continue;
923
924 if (*val < best_latency) {
925 candidate = target;
926 best_latency = *val;
927 }
928 }
929
930 if (candidate == MDESC_NODE_NULL)
931 return -ENODEV;
932
933 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
934}
935
936int of_node_to_nid(struct device_node *dp)
937{
938 const struct linux_prom64_registers *regs;
939 struct mdesc_handle *md;
940 u32 cfg_handle;
941 int count, nid;
942 u64 grp;
943
072bd413
DM		 944 /* This is the right thing to do on currently supported
945 * SUN4U NUMA platforms as well, as the PCI controller does
946 * not sit behind any particular memory controller.
947 */
919ee677
DM		 948 if (!mlgroups)
949 return -1;
950
951 regs = of_get_property(dp, "reg", NULL);
952 if (!regs)
953 return -1;
954
955 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
956
957 md = mdesc_grab();
958
959 count = 0;
960 nid = -1;
961 mdesc_for_each_node_by_name(md, grp, "group") {
962 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
963 nid = count;
964 break;
965 }
966 count++;
967 }
968
969 mdesc_release(md);
970
971 return nid;
972}
973
01c45381 974static void __init add_node_ranges(void)
919ee677 975{
08b84798 976 struct memblock_region *reg;
919ee677 977
08b84798
BH		 978 for_each_memblock(memory, reg) {
979 unsigned long size = reg->size;
919ee677
DM		 980 unsigned long start, end;
981
08b84798 982 start = reg->base;
919ee677
DM		 983 end = start + size;
984 while (start < end) {
985 unsigned long this_end;
986 int nid;
987
35a1f0bd 988 this_end = memblock_nid_range(start, end, &nid);
919ee677
DM		 989
990 numadbg("Adding active range nid[%d] "
991 "start[%lx] end[%lx]\n",
992 nid, start, this_end);
993
994 add_active_range(nid,
995 start >> PAGE_SHIFT,
996 this_end >> PAGE_SHIFT);
997
998 start = this_end;
999 }
1000 }
1001}
1002
1003static int __init grab_mlgroups(struct mdesc_handle *md)
1004{
1005 unsigned long paddr;
1006 int count = 0;
1007 u64 node;
1008
1009 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1010 count++;
1011 if (!count)
1012 return -ENOENT;
1013
95f72d1e 1014 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
919ee677
DM		 1015 SMP_CACHE_BYTES);
1016 if (!paddr)
1017 return -ENOMEM;
1018
1019 mlgroups = __va(paddr);
1020 num_mlgroups = count;
1021
1022 count = 0;
1023 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1024 struct mdesc_mlgroup *m = &mlgroups[count++];
1025 const u64 *val;
1026
1027 m->node = node;
1028
1029 val = mdesc_get_property(md, node, "latency", NULL);
1030 m->latency = *val;
1031 val = mdesc_get_property(md, node, "address-match", NULL);
1032 m->match = *val;
1033 val = mdesc_get_property(md, node, "address-mask", NULL);
1034 m->mask = *val;
1035
90181136
SR		 1036 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1037 "match[%llx] mask[%llx]\n",
919ee677
DM		 1038 count - 1, m->node, m->latency, m->match, m->mask);
1039 }
1040
1041 return 0;
1042}
1043
1044static int __init grab_mblocks(struct mdesc_handle *md)
1045{
1046 unsigned long paddr;
1047 int count = 0;
1048 u64 node;
1049
1050 mdesc_for_each_node_by_name(md, node, "mblock")
1051 count++;
1052 if (!count)
1053 return -ENOENT;
1054
95f72d1e 1055 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
919ee677
DM		 1056 SMP_CACHE_BYTES);
1057 if (!paddr)
1058 return -ENOMEM;
1059
1060 mblocks = __va(paddr);
1061 num_mblocks = count;
1062
1063 count = 0;
1064 mdesc_for_each_node_by_name(md, node, "mblock") {
1065 struct mdesc_mblock *m = &mblocks[count++];
1066 const u64 *val;
1067
1068 val = mdesc_get_property(md, node, "base", NULL);
1069 m->base = *val;
1070 val = mdesc_get_property(md, node, "size", NULL);
1071 m->size = *val;
1072 val = mdesc_get_property(md, node,
1073 "address-congruence-offset", NULL);
1074 m->offset = *val;
1075
90181136 1076 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
919ee677
DM		 1077 count - 1, m->base, m->size, m->offset);
1078 }
1079
1080 return 0;
1081}
1082
1083static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1084 u64 grp, cpumask_t *mask)
1085{
1086 u64 arc;
1087
fb1fece5 1088 cpumask_clear(mask);
919ee677
DM		 1089
1090 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1091 u64 target = mdesc_arc_target(md, arc);
1092 const char *name = mdesc_node_name(md, target);
1093 const u64 *id;
1094
1095 if (strcmp(name, "cpu"))
1096 continue;
1097 id = mdesc_get_property(md, target, "id", NULL);
e305cb8f 1098 if (*id < nr_cpu_ids)
fb1fece5 1099 cpumask_set_cpu(*id, mask);
919ee677
DM		 1100 }
1101}
1102
1103static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1104{
1105 int i;
1106
1107 for (i = 0; i < num_mlgroups; i++) {
1108 struct mdesc_mlgroup *m = &mlgroups[i];
1109 if (m->node == node)
1110 return m;
1111 }
1112 return NULL;
1113}
1114
1115static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1116 int index)
1117{
1118 struct mdesc_mlgroup *candidate = NULL;
1119 u64 arc, best_latency = ~(u64)0;
1120 struct node_mem_mask *n;
1121
1122 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1123 u64 target = mdesc_arc_target(md, arc);
1124 struct mdesc_mlgroup *m = find_mlgroup(target);
1125 if (!m)
1126 continue;
1127 if (m->latency < best_latency) {
1128 candidate = m;
1129 best_latency = m->latency;
1130 }
1131 }
1132 if (!candidate)
1133 return -ENOENT;
1134
1135 if (num_node_masks != index) {
1136 printk(KERN_ERR "Inconsistent NUMA state, "
1137 "index[%d] != num_node_masks[%d]\n",
1138 index, num_node_masks);
1139 return -EINVAL;
1140 }
1141
1142 n = &node_masks[num_node_masks++];
1143
1144 n->mask = candidate->mask;
1145 n->val = candidate->match;
1da177e4 1146
90181136 1147 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
919ee677 1148 index, n->mask, n->val, candidate->latency);
1da177e4 1149
919ee677
DM		 1150 return 0;
1151}
1152
1153static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1154 int index)
1155{
1156 cpumask_t mask;
1157 int cpu;
1158
1159 numa_parse_mdesc_group_cpus(md, grp, &mask);
1160
fb1fece5 1161 for_each_cpu(cpu, &mask)
919ee677 1162 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1163 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
919ee677
DM		 1164
1165 if (numa_debug) {
1166 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
fb1fece5 1167 for_each_cpu(cpu, &mask)
919ee677
DM		 1168 printk("%d ", cpu);
1169 printk("]\n");
1170 }
1171
1172 return numa_attach_mlgroup(md, grp, index);
1173}
1174
1175static int __init numa_parse_mdesc(void)
1176{
1177 struct mdesc_handle *md = mdesc_grab();
1178 int i, err, count;
1179 u64 node;
1180
1181 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1182 if (node == MDESC_NODE_NULL) {
1183 mdesc_release(md);
1184 return -ENOENT;
1185 }
1186
1187 err = grab_mblocks(md);
1188 if (err < 0)
1189 goto out;
1190
1191 err = grab_mlgroups(md);
1192 if (err < 0)
1193 goto out;
1194
1195 count = 0;
1196 mdesc_for_each_node_by_name(md, node, "group") {
1197 err = numa_parse_mdesc_group(md, node, count);
1198 if (err < 0)
1199 break;
1200 count++;
1201 }
1202
1203 add_node_ranges();
1204
1205 for (i = 0; i < num_node_masks; i++) {
1206 allocate_node_data(i);
1207 node_set_online(i);
1208 }
1209
1210 err = 0;
1211out:
1212 mdesc_release(md);
1213 return err;
1214}
1215
072bd413
DM		 1216static int __init numa_parse_jbus(void)
1217{
1218 unsigned long cpu, index;
1219
1220 /* NUMA node id is encoded in bits 36 and higher, and there is
1221 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1222 */
1223 index = 0;
1224 for_each_present_cpu(cpu) {
1225 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1226 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
072bd413
DM		 1227 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1228 node_masks[index].val = cpu << 36UL;
1229
1230 index++;
1231 }
1232 num_node_masks = index;
1233
1234 add_node_ranges();
1235
1236 for (index = 0; index < num_node_masks; index++) {
1237 allocate_node_data(index);
1238 node_set_online(index);
1239 }
1240
1241 return 0;
1242}
1243
919ee677
DM		 1244static int __init numa_parse_sun4u(void)
1245{
072bd413
DM		 1246 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1247 unsigned long ver;
1248
1249 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1250 if ((ver >> 32UL) == __JALAPENO_ID ||
1251 (ver >> 32UL) == __SERRANO_ID)
1252 return numa_parse_jbus();
1253 }
919ee677
DM		 1254 return -1;
1255}
1256
1257static int __init bootmem_init_numa(void)
1258{
1259 int err = -1;
1260
1261 numadbg("bootmem_init_numa()\n");
1262
1263 if (numa_enabled) {
1264 if (tlb_type == hypervisor)
1265 err = numa_parse_mdesc();
1266 else
1267 err = numa_parse_sun4u();
1268 }
1269 return err;
1270}
1271
1272#else
1da177e4 1273
919ee677
DM		 1274static int bootmem_init_numa(void)
1275{
1276 return -1;
1277}
1278
1279#endif
1280
1281static void __init bootmem_init_nonnuma(void)
1282{
95f72d1e
YL		 1283 unsigned long top_of_ram = memblock_end_of_DRAM();
1284 unsigned long total_ram = memblock_phys_mem_size();
08b84798 1285 struct memblock_region *reg;
919ee677
DM		 1286
1287 numadbg("bootmem_init_nonnuma()\n");
1288
1289 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1290 top_of_ram, total_ram);
1291 printk(KERN_INFO "Memory hole size: %ldMB\n",
1292 (top_of_ram - total_ram) >> 20);
1293
1294 init_node_masks_nonnuma();
1295
08b84798 1296 for_each_memblock(memory, reg) {
919ee677
DM		 1297 unsigned long start_pfn, end_pfn;
1298
08b84798 1299 if (!reg->size)
919ee677 1300 continue;
1da177e4 1301
c7fc2de0
YL		 1302 start_pfn = memblock_region_memory_base_pfn(reg);
1303 end_pfn = memblock_region_memory_end_pfn(reg);
919ee677
DM		 1304 add_active_range(0, start_pfn, end_pfn);
1305 }
d1112018 1306
919ee677
DM		 1307 allocate_node_data(0);
1308
1309 node_set_online(0);
1310}
1311
1312static void __init reserve_range_in_node(int nid, unsigned long start,
1313 unsigned long end)
1314{
1315 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1316 nid, start, end);
1317 while (start < end) {
1318 unsigned long this_end;
1319 int n;
1320
35a1f0bd 1321 this_end = memblock_nid_range(start, end, &n);
919ee677
DM		 1322 if (n == nid) {
1323 numadbg(" MATCH reserving range [%lx:%lx]\n",
1324 start, this_end);
1325 reserve_bootmem_node(NODE_DATA(nid), start,
1326 (this_end - start), BOOTMEM_DEFAULT);
1327 } else
1328 numadbg(" NO MATCH, advancing start to %lx\n",
1329 this_end);
1330
1331 start = this_end;
d1112018 1332 }
919ee677
DM		 1333}
1334
1335static void __init trim_reserved_in_node(int nid)
1336{
08b84798 1337 struct memblock_region *reg;
919ee677
DM		 1338
1339 numadbg(" trim_reserved_in_node(%d)\n", nid);
1340
08b84798
BH		 1341 for_each_memblock(reserved, reg)
1342 reserve_range_in_node(nid, reg->base, reg->base + reg->size);
919ee677
DM		 1343}
1344
1345static void __init bootmem_init_one_node(int nid)
1346{
1347 struct pglist_data *p;
1348
1349 numadbg("bootmem_init_one_node(%d)\n", nid);
1350
1351 p = NODE_DATA(nid);
1352
1353 if (p->node_spanned_pages) {
1354 unsigned long paddr = node_masks[nid].bootmem_paddr;
1355 unsigned long end_pfn;
1356
1357 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1358
1359 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1360 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1361
1362 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1363 p->node_start_pfn, end_pfn);
1364
1365 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1366 nid, end_pfn);
1367 free_bootmem_with_active_regions(nid, end_pfn);
1368
1369 trim_reserved_in_node(nid);
1370
1371 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1372 nid);
1373 sparse_memory_present_with_active_regions(nid);
1374 }
1375}
1376
1377static unsigned long __init bootmem_init(unsigned long phys_base)
1378{
1379 unsigned long end_pfn;
1380 int nid;
1381
95f72d1e 1382 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
919ee677
DM		 1383 max_pfn = max_low_pfn = end_pfn;
1384 min_low_pfn = (phys_base >> PAGE_SHIFT);
1385
1386 if (bootmem_init_numa() < 0)
1387 bootmem_init_nonnuma();
1388
1389 /* XXX cpu notifier XXX */
1390
1391 for_each_online_node(nid)
1392 bootmem_init_one_node(nid);
d1112018
DM		 1393
1394 sparse_init();
1395
1da177e4
LT		 1396 return end_pfn;
1397}
1398
9cc3a1ac
DM		 1399static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1400static int pall_ents __initdata;
1401
56425306 1402#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 1403static unsigned long __ref kernel_map_range(unsigned long pstart,
1404 unsigned long pend, pgprot_t prot)
56425306
DM		 1405{
1406 unsigned long vstart = PAGE_OFFSET + pstart;
1407 unsigned long vend = PAGE_OFFSET + pend;
1408 unsigned long alloc_bytes = 0UL;
1409
1410 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1411 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1412 vstart, vend);
1413 prom_halt();
1414 }
1415
1416 while (vstart < vend) {
1417 unsigned long this_end, paddr = __pa(vstart);
1418 pgd_t *pgd = pgd_offset_k(vstart);
1419 pud_t *pud;
1420 pmd_t *pmd;
1421 pte_t *pte;
1422
1423 pud = pud_offset(pgd, vstart);
1424 if (pud_none(*pud)) {
1425 pmd_t *new;
1426
1427 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1428 alloc_bytes += PAGE_SIZE;
1429 pud_populate(&init_mm, pud, new);
1430 }
1431
1432 pmd = pmd_offset(pud, vstart);
1433 if (!pmd_present(*pmd)) {
1434 pte_t *new;
1435
1436 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1437 alloc_bytes += PAGE_SIZE;
1438 pmd_populate_kernel(&init_mm, pmd, new);
1439 }
1440
1441 pte = pte_offset_kernel(pmd, vstart);
1442 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1443 if (this_end > vend)
1444 this_end = vend;
1445
1446 while (vstart < this_end) {
1447 pte_val(*pte) = (paddr | pgprot_val(prot));
1448
1449 vstart += PAGE_SIZE;
1450 paddr += PAGE_SIZE;
1451 pte++;
1452 }
1453 }
1454
1455 return alloc_bytes;
1456}
1457
56425306 1458extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1459#endif /* CONFIG_DEBUG_PAGEALLOC */
1460
1461static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1462{
1463 const unsigned long shift_256MB = 28;
1464 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1465 const unsigned long size_256MB = (1UL << shift_256MB);
1466
1467 while (start < end) {
1468 long remains;
1469
f7c00338
DM		 1470 remains = end - start;
1471 if (remains < size_256MB)
1472 break;
1473
9cc3a1ac
DM		 1474 if (start & mask_256MB) {
1475 start = (start + size_256MB) & ~mask_256MB;
1476 continue;
1477 }
1478
9cc3a1ac
DM		 1479 while (remains >= size_256MB) {
1480 unsigned long index = start >> shift_256MB;
1481
1482 __set_bit(index, kpte_linear_bitmap);
1483
1484 start += size_256MB;
1485 remains -= size_256MB;
1486 }
1487 }
1488}
56425306 1489
8f361453 1490static void __init init_kpte_bitmap(void)
56425306 1491{
9cc3a1ac 1492 unsigned long i;
13edad7a
DM		 1493
1494 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1495 unsigned long phys_start, phys_end;
1496
13edad7a
DM		 1497 phys_start = pall[i].phys_addr;
1498 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1499
1500 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 1501 }
1502}
9cc3a1ac 1503
8f361453
DM		 1504static void __init kernel_physical_mapping_init(void)
1505{
9cc3a1ac 1506#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 1507 unsigned long i, mem_alloced = 0UL;
1508
1509 for (i = 0; i < pall_ents; i++) {
1510 unsigned long phys_start, phys_end;
1511
1512 phys_start = pall[i].phys_addr;
1513 phys_end = phys_start + pall[i].reg_size;
1514
56425306
DM		 1515 mem_alloced += kernel_map_range(phys_start, phys_end,
1516 PAGE_KERNEL);
56425306
DM		 1517 }
1518
1519 printk("Allocated %ld bytes for kernel page tables.\n",
1520 mem_alloced);
1521
1522 kvmap_linear_patch[0] = 0x01000000; /* nop */
1523 flushi(&kvmap_linear_patch[0]);
1524
1525 __flush_tlb_all();
9cc3a1ac 1526#endif
56425306
DM		 1527}
1528
9cc3a1ac 1529#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1530void kernel_map_pages(struct page *page, int numpages, int enable)
1531{
1532 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1533 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1534
1535 kernel_map_range(phys_start, phys_end,
1536 (enable ? PAGE_KERNEL : __pgprot(0)));
1537
74bf4312
DM		 1538 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1539 PAGE_OFFSET + phys_end);
1540
56425306
DM		 1541 /* we should perform an IPI and flush all tlbs,
1542 * but that can deadlock->flush only current cpu.
1543 */
1544 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1545 PAGE_OFFSET + phys_end);
1546}
1547#endif
1548
10147570
DM		 1549unsigned long __init find_ecache_flush_span(unsigned long size)
1550{
0836a0eb
DM		 1551 int i;
1552
13edad7a
DM		 1553 for (i = 0; i < pavail_ents; i++) {
1554 if (pavail[i].reg_size >= size)
1555 return pavail[i].phys_addr;
0836a0eb
DM		 1556 }
1557
13edad7a 1558 return ~0UL;
0836a0eb
DM		 1559}
1560
517af332
DM		 1561static void __init tsb_phys_patch(void)
1562{
d257d5da 1563 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1564 struct tsb_phys_patch_entry *p;
1565
d257d5da
DM		 1566 pquad = &__tsb_ldquad_phys_patch;
1567 while (pquad < &__tsb_ldquad_phys_patch_end) {
1568 unsigned long addr = pquad->addr;
1569
1570 if (tlb_type == hypervisor)
1571 *(unsigned int *) addr = pquad->sun4v_insn;
1572 else
1573 *(unsigned int *) addr = pquad->sun4u_insn;
1574 wmb();
1575 __asm__ __volatile__("flush %0"
1576 : /* no outputs */
1577 : "r" (addr));
1578
1579 pquad++;
1580 }
1581
517af332
DM		 1582 p = &__tsb_phys_patch;
1583 while (p < &__tsb_phys_patch_end) {
1584 unsigned long addr = p->addr;
1585
1586 *(unsigned int *) addr = p->insn;
1587 wmb();
1588 __asm__ __volatile__("flush %0"
1589 : /* no outputs */
1590 : "r" (addr));
1591
1592 p++;
1593 }
1594}
1595
490384e7 1596/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1597#ifndef CONFIG_DEBUG_PAGEALLOC
1598#define NUM_KTSB_DESCR 2
1599#else
1600#define NUM_KTSB_DESCR 1
1601#endif
1602static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1603extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1604
9076d0e7
DM		 1605static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1606{
1607 pa >>= KTSB_PHYS_SHIFT;
1608
1609 while (start < end) {
1610 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1611
1612 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1613 __asm__ __volatile__("flush %0" : : "r" (ia));
1614
1615 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1616 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1617
1618 start++;
1619 }
1620}
1621
1622static void ktsb_phys_patch(void)
1623{
1624 extern unsigned int __swapper_tsb_phys_patch;
1625 extern unsigned int __swapper_tsb_phys_patch_end;
9076d0e7
DM		 1626 unsigned long ktsb_pa;
1627
1628 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1629 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1630 &__swapper_tsb_phys_patch_end, ktsb_pa);
1631#ifndef CONFIG_DEBUG_PAGEALLOC
0785a8e8
DM		 1632 {
1633 extern unsigned int __swapper_4m_tsb_phys_patch;
1634 extern unsigned int __swapper_4m_tsb_phys_patch_end;
9076d0e7
DM		 1635 ktsb_pa = (kern_base +
1636 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1637 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1638 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
0785a8e8 1639 }
9076d0e7
DM		 1640#endif
1641}
1642
490384e7
DM		 1643static void __init sun4v_ktsb_init(void)
1644{
1645 unsigned long ktsb_pa;
1646
d7744a09 1647 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1648 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1649
1650 switch (PAGE_SIZE) {
1651 case 8 * 1024:
1652 default:
1653 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1654 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1655 break;
1656
1657 case 64 * 1024:
1658 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1659 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1660 break;
1661
1662 case 512 * 1024:
1663 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1664 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1665 break;
1666
1667 case 4 * 1024 * 1024:
1668 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1669 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1670 break;
6cb79b3f 1671 }
490384e7 1672
3f19a84e 1673 ktsb_descr[0].assoc = 1;
490384e7
DM		 1674 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1675 ktsb_descr[0].ctx_idx = 0;
1676 ktsb_descr[0].tsb_base = ktsb_pa;
1677 ktsb_descr[0].resv = 0;
1678
d1acb421 1679#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1680 /* Second KTSB for 4MB/256MB mappings. */
1681 ktsb_pa = (kern_base +
1682 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1683
1684 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1685 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1686 HV_PGSZ_MASK_256MB);
1687 ktsb_descr[1].assoc = 1;
1688 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1689 ktsb_descr[1].ctx_idx = 0;
1690 ktsb_descr[1].tsb_base = ktsb_pa;
1691 ktsb_descr[1].resv = 0;
d1acb421 1692#endif
490384e7
DM		 1693}
1694
1695void __cpuinit sun4v_ktsb_register(void)
1696{
7db35f31 1697 unsigned long pa, ret;
490384e7
DM		 1698
1699 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1700
7db35f31
DM		 1701 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1702 if (ret != 0) {
1703 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1704 "errors with %lx\n", pa, ret);
1705 prom_halt();
1706 }
490384e7
DM		 1707}
1708
1da177e4
LT		 1709/* paging_init() sets up the page tables */
1710
1da177e4 1711static unsigned long last_valid_pfn;
56425306 1712pgd_t swapper_pg_dir[2048];
1da177e4 1713
c4bce90e
DM		 1714static void sun4u_pgprot_init(void);
1715static void sun4v_pgprot_init(void);
1716
1da177e4
LT		 1717void __init paging_init(void)
1718{
919ee677 1719 unsigned long end_pfn, shift, phys_base;
0836a0eb
DM		 1720 unsigned long real_end, i;
1721
22adb358
DM		 1722 /* These build time checkes make sure that the dcache_dirty_cpu()
1723 * page->flags usage will work.
1724 *
1725 * When a page gets marked as dcache-dirty, we store the
1726 * cpu number starting at bit 32 in the page->flags. Also,
1727 * functions like clear_dcache_dirty_cpu use the cpu mask
1728 * in 13-bit signed-immediate instruction fields.
1729 */
9223b419
CL		 1730
1731 /*
1732 * Page flags must not reach into upper 32 bits that are used
1733 * for the cpu number
1734 */
1735 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1736
1737 /*
1738 * The bit fields placed in the high range must not reach below
1739 * the 32 bit boundary. Otherwise we cannot place the cpu field
1740 * at the 32 bit boundary.
1741 */
22adb358 1742 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
9223b419
CL		 1743 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1744
22adb358
DM		 1745 BUILD_BUG_ON(NR_CPUS > 4096);
1746
481295f9
DM		 1747 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1748 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1749
d7744a09 1750 /* Invalidate both kernel TSBs. */
8b234274 1751 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1752#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1753 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1754#endif
8b234274 1755
c4bce90e
DM		 1756 if (tlb_type == hypervisor)
1757 sun4v_pgprot_init();
1758 else
1759 sun4u_pgprot_init();
1760
d257d5da 1761 if (tlb_type == cheetah_plus ||
9076d0e7 1762 tlb_type == hypervisor) {
517af332 1763 tsb_phys_patch();
9076d0e7
DM		 1764 ktsb_phys_patch();
1765 }
517af332 1766
490384e7 1767 if (tlb_type == hypervisor) {
d257d5da 1768 sun4v_patch_tlb_handlers();
490384e7
DM		 1769 sun4v_ktsb_init();
1770 }
d257d5da 1771
a94a172d
DM		 1772 /* Find available physical memory...
1773 *
1774 * Read it twice in order to work around a bug in openfirmware.
1775 * The call to grab this table itself can cause openfirmware to
1776 * allocate memory, which in turn can take away some space from
1777 * the list of available memory. Reading it twice makes sure
1778 * we really do get the final value.
1779 */
1780 read_obp_translations();
1781 read_obp_memory("reg", &pall[0], &pall_ents);
1782 read_obp_memory("available", &pavail[0], &pavail_ents);
13edad7a 1783 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1784
1785 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1786 for (i = 0; i < pavail_ents; i++) {
13edad7a 1787 phys_base = min(phys_base, pavail[i].phys_addr);
95f72d1e 1788 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
3b2a7e23
DM		 1789 }
1790
95f72d1e 1791 memblock_reserve(kern_base, kern_size);
0836a0eb 1792
4e82c9a6
DM		 1793 find_ramdisk(phys_base);
1794
95f72d1e 1795 memblock_enforce_memory_limit(cmdline_memory_size);
25b0c659 1796
1aadc056 1797 memblock_allow_resize();
95f72d1e 1798 memblock_dump_all();
3b2a7e23 1799
1da177e4
LT		 1800 set_bit(0, mmu_context_bmap);
1801
2bdb3cb2
DM		 1802 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1803
1da177e4 1804 real_end = (unsigned long)_end;
64658743
DM		 1805 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1806 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1807 num_kernel_image_mappings);
2bdb3cb2
DM		 1808
1809 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1810 * work.
1811 */
1812 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1813
56425306 1814 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1815
1816 /* Now can init the kernel/bad page tables. */
1817 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1818 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1819
c9c10830 1820 inherit_prom_mappings();
5085b4a5 1821
8f361453
DM		 1822 init_kpte_bitmap();
1823
a8b900d8
DM		 1824 /* Ok, we can use our TLB miss and window trap handlers safely. */
1825 setup_tba();
1da177e4 1826
c9c10830 1827 __flush_tlb_all();
9ad98c5b 1828
490384e7
DM		 1829 if (tlb_type == hypervisor)
1830 sun4v_ktsb_register();
1831
ad072004 1832 prom_build_devicetree();
b696fdc2 1833 of_populate_present_mask();
b99c6ebe
DM		 1834#ifndef CONFIG_SMP
1835 of_fill_in_cpu_data();
1836#endif
ad072004 1837
890db403 1838 if (tlb_type == hypervisor) {
4a283339 1839 sun4v_mdesc_init();
6ac5c610 1840 mdesc_populate_present_mask(cpu_all_mask);
b99c6ebe
DM		 1841#ifndef CONFIG_SMP
1842 mdesc_fill_in_cpu_data(cpu_all_mask);
1843#endif
890db403 1844 }
4a283339 1845
4f70f7a9
DM		 1846 /* Once the OF device tree and MDESC have been setup, we know
1847 * the list of possible cpus. Therefore we can allocate the
1848 * IRQ stacks.
1849 */
1850 for_each_possible_cpu(i) {
1851 /* XXX Use node local allocations... XXX */
95f72d1e
YL		 1852 softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
1853 hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
4f70f7a9
DM		 1854 }
1855
2bdb3cb2 1856 /* Setup bootmem... */
919ee677 1857 last_valid_pfn = end_pfn = bootmem_init(phys_base);
d1112018 1858
919ee677 1859#ifndef CONFIG_NEED_MULTIPLE_NODES
17b0e199 1860 max_mapnr = last_valid_pfn;
919ee677 1861#endif
56425306 1862 kernel_physical_mapping_init();
56425306 1863
1da177e4 1864 {
919ee677 1865 unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 1866
919ee677 1867 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1da177e4 1868
919ee677 1869 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1da177e4 1870
919ee677 1871 free_area_init_nodes(max_zone_pfns);
1da177e4
LT		 1872 }
1873
3c62a2d3 1874 printk("Booting Linux...\n");
1da177e4
LT		 1875}
1876
9a2ed5cc 1877int __devinit page_in_phys_avail(unsigned long paddr)
919ee677
DM		 1878{
1879 int i;
1880
1881 paddr &= PAGE_MASK;
1882
1883 for (i = 0; i < pavail_ents; i++) {
1884 unsigned long start, end;
1885
1886 start = pavail[i].phys_addr;
1887 end = start + pavail[i].reg_size;
1888
1889 if (paddr >= start && paddr < end)
1890 return 1;
1891 }
1892 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1893 return 1;
1894#ifdef CONFIG_BLK_DEV_INITRD
1895 if (paddr >= __pa(initrd_start) &&
1896 paddr < __pa(PAGE_ALIGN(initrd_end)))
1897 return 1;
1898#endif
1899
1900 return 0;
1901}
1902
1903static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1904static int pavail_rescan_ents __initdata;
1905
1906/* Certain OBP calls, such as fetching "available" properties, can
1907 * claim physical memory. So, along with initializing the valid
1908 * address bitmap, what we do here is refetch the physical available
1909 * memory list again, and make sure it provides at least as much
1910 * memory as 'pavail' does.
1911 */
d8ed1d43 1912static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1da177e4 1913{
1da177e4
LT		 1914 int i;
1915
13edad7a 1916 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1917
13edad7a 1918 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1919 unsigned long old_start, old_end;
1920
13edad7a 1921 old_start = pavail[i].phys_addr;
919ee677 1922 old_end = old_start + pavail[i].reg_size;
1da177e4
LT		 1923 while (old_start < old_end) {
1924 int n;
1925
c2a5a46b 1926 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1927 unsigned long new_start, new_end;
1928
13edad7a
DM		 1929 new_start = pavail_rescan[n].phys_addr;
1930 new_end = new_start +
1931 pavail_rescan[n].reg_size;
1da177e4
LT		 1932
1933 if (new_start <= old_start &&
1934 new_end >= (old_start + PAGE_SIZE)) {
d8ed1d43 1935 set_bit(old_start >> 22, bitmap);
1da177e4
LT		 1936 goto do_next_page;
1937 }
1938 }
919ee677
DM		 1939
1940 prom_printf("mem_init: Lost memory in pavail\n");
1941 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1942 pavail[i].phys_addr,
1943 pavail[i].reg_size);
1944 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1945 pavail_rescan[i].phys_addr,
1946 pavail_rescan[i].reg_size);
1947 prom_printf("mem_init: Cannot continue, aborting.\n");
1948 prom_halt();
1da177e4
LT		 1949
1950 do_next_page:
1951 old_start += PAGE_SIZE;
1952 }
1953 }
1954}
1955
d8ed1d43
DM		 1956static void __init patch_tlb_miss_handler_bitmap(void)
1957{
1958 extern unsigned int valid_addr_bitmap_insn[];
1959 extern unsigned int valid_addr_bitmap_patch[];
1960
1961 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
1962 mb();
1963 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
1964 flushi(&valid_addr_bitmap_insn[0]);
1965}
1966
1da177e4
LT		 1967void __init mem_init(void)
1968{
1969 unsigned long codepages, datapages, initpages;
1970 unsigned long addr, last;
1da177e4
LT		 1971
1972 addr = PAGE_OFFSET + kern_base;
1973 last = PAGE_ALIGN(kern_size) + addr;
1974 while (addr < last) {
1975 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1976 addr += PAGE_SIZE;
1977 }
1978
d8ed1d43
DM		 1979 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
1980 patch_tlb_miss_handler_bitmap();
1da177e4 1981
1da177e4
LT		 1982 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1983
919ee677 1984#ifdef CONFIG_NEED_MULTIPLE_NODES
d8ed1d43
DM		 1985 {
1986 int i;
1987 for_each_online_node(i) {
1988 if (NODE_DATA(i)->node_spanned_pages != 0) {
1989 totalram_pages +=
1990 free_all_bootmem_node(NODE_DATA(i));
1991 }
919ee677
DM		 1992 }
1993 }
1994#else
1995 totalram_pages = free_all_bootmem();
1996#endif
1997
f1cfdb55
DM		 1998 /* We subtract one to account for the mem_map_zero page
1999 * allocated below.
2000 */
919ee677
DM		 2001 totalram_pages -= 1;
2002 num_physpages = totalram_pages;
1da177e4
LT		 2003
2004 /*
2005 * Set up the zero page, mark it reserved, so that page count
2006 * is not manipulated when freeing the page from user ptes.
2007 */
2008 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2009 if (mem_map_zero == NULL) {
2010 prom_printf("paging_init: Cannot alloc zero page.\n");
2011 prom_halt();
2012 }
2013 SetPageReserved(mem_map_zero);
2014
2015 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2016 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2017 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2018 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2019 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2020 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2021
96177299 2022 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 2023 nr_free_pages() << (PAGE_SHIFT-10),
2024 codepages << (PAGE_SHIFT-10),
2025 datapages << (PAGE_SHIFT-10),
2026 initpages << (PAGE_SHIFT-10),
2027 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2028
2029 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2030 cheetah_ecache_flush_init();
2031}
2032
898cf0ec 2033void free_initmem(void)
1da177e4
LT		 2034{
2035 unsigned long addr, initend;
f2b60794
DM		 2036 int do_free = 1;
2037
2038 /* If the physical memory maps were trimmed by kernel command
2039 * line options, don't even try freeing this initmem stuff up.
2040 * The kernel image could have been in the trimmed out region
2041 * and if so the freeing below will free invalid page structs.
2042 */
2043 if (cmdline_memory_size)
2044 do_free = 0;
1da177e4
LT		 2045
2046 /*
2047 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2048 */
2049 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2050 initend = (unsigned long)(__init_end) & PAGE_MASK;
2051 for (; addr < initend; addr += PAGE_SIZE) {
2052 unsigned long page;
2053 struct page *p;
2054
2055 page = (addr +
2056 ((unsigned long) __va(kern_base)) -
2057 ((unsigned long) KERNBASE));
c9cf5528 2058 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4 2059
f2b60794
DM		 2060 if (do_free) {
2061 p = virt_to_page(page);
2062
2063 ClearPageReserved(p);
2064 init_page_count(p);
2065 __free_page(p);
2066 num_physpages++;
2067 totalram_pages++;
2068 }
1da177e4
LT		 2069 }
2070}
2071
2072#ifdef CONFIG_BLK_DEV_INITRD
2073void free_initrd_mem(unsigned long start, unsigned long end)
2074{
2075 if (start < end)
2076 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2077 for (; start < end; start += PAGE_SIZE) {
2078 struct page *p = virt_to_page(start);
2079
2080 ClearPageReserved(p);
7835e98b 2081 init_page_count(p);
1da177e4
LT		 2082 __free_page(p);
2083 num_physpages++;
2084 totalram_pages++;
2085 }
2086}
2087#endif
c4bce90e 2088
c4bce90e
DM		 2089#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2090#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2091#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2092#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2093#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2094#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2095
2096pgprot_t PAGE_KERNEL __read_mostly;
2097EXPORT_SYMBOL(PAGE_KERNEL);
2098
2099pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2100pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 2101
2102pgprot_t PAGE_SHARED __read_mostly;
2103EXPORT_SYMBOL(PAGE_SHARED);
2104
c4bce90e
DM		 2105unsigned long pg_iobits __read_mostly;
2106
2107unsigned long _PAGE_IE __read_mostly;
987c74fc 2108EXPORT_SYMBOL(_PAGE_IE);
b2bef442 2109
c4bce90e 2110unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 2111EXPORT_SYMBOL(_PAGE_E);
2112
c4bce90e 2113unsigned long _PAGE_CACHE __read_mostly;
b2bef442 2114EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 2115
46644c24 2116#ifdef CONFIG_SPARSEMEM_VMEMMAP
46644c24
DM		 2117unsigned long vmemmap_table[VMEMMAP_SIZE];
2118
2119int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2120{
2121 unsigned long vstart = (unsigned long) start;
2122 unsigned long vend = (unsigned long) (start + nr);
2123 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2124 unsigned long phys_end = (vend - VMEMMAP_BASE);
2125 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2126 unsigned long end = VMEMMAP_ALIGN(phys_end);
2127 unsigned long pte_base;
2128
2129 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2130 _PAGE_CP_4U | _PAGE_CV_4U |
2131 _PAGE_P_4U | _PAGE_W_4U);
2132 if (tlb_type == hypervisor)
2133 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2134 _PAGE_CP_4V | _PAGE_CV_4V |
2135 _PAGE_P_4V | _PAGE_W_4V);
2136
2137 for (; addr < end; addr += VMEMMAP_CHUNK) {
2138 unsigned long *vmem_pp =
2139 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2140 void *block;
2141
2142 if (!(*vmem_pp & _PAGE_VALID)) {
2143 block = vmemmap_alloc_block(1UL << 22, node);
2144 if (!block)
2145 return -ENOMEM;
2146
2147 *vmem_pp = pte_base | __pa(block);
2148
2149 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2150 "node=%d entry=%lu/%lu\n", start, block, nr,
2151 node,
2152 addr >> VMEMMAP_CHUNK_SHIFT,
33cd9dfa 2153 VMEMMAP_SIZE);
46644c24
DM		 2154 }
2155 }
2156 return 0;
2157}
2158#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2159
c4bce90e
DM		 2160static void prot_init_common(unsigned long page_none,
2161 unsigned long page_shared,
2162 unsigned long page_copy,
2163 unsigned long page_readonly,
2164 unsigned long page_exec_bit)
2165{
2166 PAGE_COPY = __pgprot(page_copy);
0f15952a 2167 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 2168
2169 protection_map[0x0] = __pgprot(page_none);
2170 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2171 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2172 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2173 protection_map[0x4] = __pgprot(page_readonly);
2174 protection_map[0x5] = __pgprot(page_readonly);
2175 protection_map[0x6] = __pgprot(page_copy);
2176 protection_map[0x7] = __pgprot(page_copy);
2177 protection_map[0x8] = __pgprot(page_none);
2178 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2179 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2180 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2181 protection_map[0xc] = __pgprot(page_readonly);
2182 protection_map[0xd] = __pgprot(page_readonly);
2183 protection_map[0xe] = __pgprot(page_shared);
2184 protection_map[0xf] = __pgprot(page_shared);
2185}
2186
2187static void __init sun4u_pgprot_init(void)
2188{
2189 unsigned long page_none, page_shared, page_copy, page_readonly;
2190 unsigned long page_exec_bit;
2191
2192 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2193 _PAGE_CACHE_4U | _PAGE_P_4U |
2194 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2195 _PAGE_EXEC_4U);
2196 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2197 _PAGE_CACHE_4U | _PAGE_P_4U |
2198 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2199 _PAGE_EXEC_4U | _PAGE_L_4U);
c4bce90e
DM		 2200
2201 _PAGE_IE = _PAGE_IE_4U;
2202 _PAGE_E = _PAGE_E_4U;
2203 _PAGE_CACHE = _PAGE_CACHE_4U;
2204
2205 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2206 __ACCESS_BITS_4U | _PAGE_E_4U);
2207
d1acb421
DM		 2208#ifdef CONFIG_DEBUG_PAGEALLOC
2209 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
af1ee569 2210 0xfffff80000000000UL;
d1acb421 2211#else
9cc3a1ac 2212 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
af1ee569 2213 0xfffff80000000000UL;
d1acb421 2214#endif
9cc3a1ac
DM		 2215 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2216 _PAGE_P_4U | _PAGE_W_4U);
2217
2218 /* XXX Should use 256MB on Panther. XXX */
2219 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 2220
2221 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2222 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2223 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2224 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2225
2226
2227 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2228 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2229 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2230 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2231 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2232 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2233 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2234
2235 page_exec_bit = _PAGE_EXEC_4U;
2236
2237 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2238 page_exec_bit);
2239}
2240
2241static void __init sun4v_pgprot_init(void)
2242{
2243 unsigned long page_none, page_shared, page_copy, page_readonly;
2244 unsigned long page_exec_bit;
2245
2246 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2247 _PAGE_CACHE_4V | _PAGE_P_4V |
2248 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2249 _PAGE_EXEC_4V);
2250 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
c4bce90e
DM		 2251
2252 _PAGE_IE = _PAGE_IE_4V;
2253 _PAGE_E = _PAGE_E_4V;
2254 _PAGE_CACHE = _PAGE_CACHE_4V;
2255
d1acb421
DM		 2256#ifdef CONFIG_DEBUG_PAGEALLOC
2257 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
af1ee569 2258 0xfffff80000000000UL;
d1acb421 2259#else
9cc3a1ac 2260 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
af1ee569 2261 0xfffff80000000000UL;
d1acb421 2262#endif
9cc3a1ac
DM		 2263 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2264 _PAGE_P_4V | _PAGE_W_4V);
2265
d1acb421
DM		 2266#ifdef CONFIG_DEBUG_PAGEALLOC
2267 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
af1ee569 2268 0xfffff80000000000UL;
d1acb421 2269#else
9cc3a1ac 2270 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
af1ee569 2271 0xfffff80000000000UL;
d1acb421 2272#endif
9cc3a1ac
DM		 2273 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2274 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 2275
2276 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2277 __ACCESS_BITS_4V | _PAGE_E_4V);
2278
2279 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2280 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2281 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2282 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2283 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2284
2285 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2286 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2287 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2288 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2289 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2290 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2291 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2292
2293 page_exec_bit = _PAGE_EXEC_4V;
2294
2295 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2296 page_exec_bit);
2297}
2298
2299unsigned long pte_sz_bits(unsigned long sz)
2300{
2301 if (tlb_type == hypervisor) {
2302 switch (sz) {
2303 case 8 * 1024:
2304 default:
2305 return _PAGE_SZ8K_4V;
2306 case 64 * 1024:
2307 return _PAGE_SZ64K_4V;
2308 case 512 * 1024:
2309 return _PAGE_SZ512K_4V;
2310 case 4 * 1024 * 1024:
2311 return _PAGE_SZ4MB_4V;
6cb79b3f 2312 }
c4bce90e
DM		 2313 } else {
2314 switch (sz) {
2315 case 8 * 1024:
2316 default:
2317 return _PAGE_SZ8K_4U;
2318 case 64 * 1024:
2319 return _PAGE_SZ64K_4U;
2320 case 512 * 1024:
2321 return _PAGE_SZ512K_4U;
2322 case 4 * 1024 * 1024:
2323 return _PAGE_SZ4MB_4U;
6cb79b3f 2324 }
c4bce90e
DM		 2325 }
2326}
2327
2328pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2329{
2330 pte_t pte;
cf627156
DM		 2331
2332 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 2333 pte_val(pte) |= (((unsigned long)space) << 32);
2334 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 2335
cf627156 2336 return pte;
c4bce90e
DM		 2337}
2338
2339static unsigned long kern_large_tte(unsigned long paddr)
2340{
2341 unsigned long val;
2342
2343 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2344 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2345 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2346 if (tlb_type == hypervisor)
2347 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2348 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2349 _PAGE_EXEC_4V | _PAGE_W_4V);
2350
2351 return val | paddr;
2352}
2353
c4bce90e
DM		 2354/* If not locked, zap it. */
2355void __flush_tlb_all(void)
2356{
2357 unsigned long pstate;
2358 int i;
2359
2360 __asm__ __volatile__("flushw\n\t"
2361 "rdpr %%pstate, %0\n\t"
2362 "wrpr %0, %1, %%pstate"
2363 : "=r" (pstate)
2364 : "i" (PSTATE_IE));
8f361453
DM		 2365 if (tlb_type == hypervisor) {
2366 sun4v_mmu_demap_all();
2367 } else if (tlb_type == spitfire) {
c4bce90e
DM		 2368 for (i = 0; i < 64; i++) {
2369 /* Spitfire Errata #32 workaround */
2370 /* NOTE: Always runs on spitfire, so no
2371 * cheetah+ page size encodings.
2372 */
2373 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2374 "flush %%g6"
2375 : /* No outputs */
2376 : "r" (0),
2377 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2378
2379 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2380 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2381 "membar #Sync"
2382 : /* no outputs */
2383 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2384 spitfire_put_dtlb_data(i, 0x0UL);
2385 }
2386
2387 /* Spitfire Errata #32 workaround */
2388 /* NOTE: Always runs on spitfire, so no
2389 * cheetah+ page size encodings.
2390 */
2391 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2392 "flush %%g6"
2393 : /* No outputs */
2394 : "r" (0),
2395 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2396
2397 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2398 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2399 "membar #Sync"
2400 : /* no outputs */
2401 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2402 spitfire_put_itlb_data(i, 0x0UL);
2403 }
2404 }
2405 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2406 cheetah_flush_dtlb_all();
2407 cheetah_flush_itlb_all();
2408 }
2409 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2410 : : "r" (pstate));
2411}
kernel source for telekom puls (alcatel/mediatek)