[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / arch / sparc / kernel / smp.c

/* smp.c: Sparc SMP support.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
 */

#include <asm/head.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/cache.h>
#include <linux/delay.h>

#include <asm/ptrace.h>
#include <asm/atomic.h>

#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/cpudata.h>

int smp_num_cpus = 1;
volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
unsigned char boot_cpu_id = 0;
unsigned char boot_cpu_id4 = 0; /* boot_cpu_id << 2 */
int smp_activated = 0;
volatile int __cpu_number_map[NR_CPUS];
volatile int __cpu_logical_map[NR_CPUS];

cpumask_t cpu_online_map = CPU_MASK_NONE;
cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
cpumask_t smp_commenced_mask = CPU_MASK_NONE;

/* The only guaranteed locking primitive available on all Sparc
 * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
 * places the current byte at the effective address into dest_reg and
 * places 0xff there afterwards.  Pretty lame locking primitive
 * compared to the Alpha and the Intel no?  Most Sparcs have 'swap'
 * instruction which is much better...
 */

/* Used to make bitops atomic */
unsigned char bitops_spinlock = 0;

void __cpuinit smp_store_cpu_info(int id)
{
	int cpu_node;

	cpu_data(id).udelay_val = loops_per_jiffy;

	cpu_find_by_mid(id, &cpu_node);
	cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
						     "clock-frequency", 0);
	cpu_data(id).prom_node = cpu_node;
	cpu_data(id).mid = cpu_get_hwmid(cpu_node);

	/* this is required to tune the scheduler correctly */
	/* is it possible to have CPUs with different cache sizes? */
	if (id == boot_cpu_id) {
		int cache_line,cache_nlines;
		cache_line = 0x20;
		cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line);
		cache_nlines = 0x8000;
		cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
		max_cache_size = cache_line * cache_nlines;
	}
	if (cpu_data(id).mid < 0)
		panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	extern void smp4m_smp_done(void);
	extern void smp4d_smp_done(void);
	unsigned long bogosum = 0;
	int cpu, num;

	for (cpu = 0, num = 0; cpu < NR_CPUS; cpu++)
		if (cpu_online(cpu)) {
			num++;
			bogosum += cpu_data(cpu).udelay_val;
		}

	printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
		num, bogosum/(500000/HZ),
		(bogosum/(5000/HZ))%100);

	switch(sparc_cpu_model) {
	case sun4:
		printk("SUN4\n");
		BUG();
		break;
	case sun4c:
		printk("SUN4C\n");
		BUG();
		break;
	case sun4m:
		smp4m_smp_done();
		break;
	case sun4d:
		smp4d_smp_done();
		break;
	case sun4e:
		printk("SUN4E\n");
		BUG();
		break;
	case sun4u:
		printk("SUN4U\n");
		BUG();
		break;
	default:
		printk("UNKNOWN!\n");
		BUG();
		break;
	};
}

void cpu_panic(void)
{
	printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
	panic("SMP bolixed\n");
}

struct linux_prom_registers smp_penguin_ctable __initdata = { 0 };

void smp_send_reschedule(int cpu)
{
	/* See sparc64 */
}

void smp_send_stop(void)
{
}

void smp_flush_cache_all(void)
{
	xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all));
	local_flush_cache_all();
}

void smp_flush_tlb_all(void)
{
	xc0((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_all));
	local_flush_tlb_all();
}

void smp_flush_cache_mm(struct mm_struct *mm)
{
	if(mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask))
			xc1((smpfunc_t) BTFIXUP_CALL(local_flush_cache_mm), (unsigned long) mm);
		local_flush_cache_mm(mm);
	}
}

void smp_flush_tlb_mm(struct mm_struct *mm)
{
	if(mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask)) {
			xc1((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_mm), (unsigned long) mm);
			if(atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
				mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
		}
		local_flush_tlb_mm(mm);
	}
}

void smp_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
			   unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;

	if (mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask))
			xc3((smpfunc_t) BTFIXUP_CALL(local_flush_cache_range), (unsigned long) vma, start, end);
		local_flush_cache_range(vma, start, end);
	}
}

void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
			 unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;

	if (mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask))
			xc3((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_range), (unsigned long) vma, start, end);
		local_flush_tlb_range(vma, start, end);
	}
}

void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
{
	struct mm_struct *mm = vma->vm_mm;

	if(mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask))
			xc2((smpfunc_t) BTFIXUP_CALL(local_flush_cache_page), (unsigned long) vma, page);
		local_flush_cache_page(vma, page);
	}
}

void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	struct mm_struct *mm = vma->vm_mm;

	if(mm->context != NO_CONTEXT) {
		cpumask_t cpu_mask = mm->cpu_vm_mask;
		cpu_clear(smp_processor_id(), cpu_mask);
		if (!cpus_empty(cpu_mask))
			xc2((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_page), (unsigned long) vma, page);
		local_flush_tlb_page(vma, page);
	}
}

void smp_reschedule_irq(void)
{
	set_need_resched();
}

void smp_flush_page_to_ram(unsigned long page)
{
	/* Current theory is that those who call this are the one's
	 * who have just dirtied their cache with the pages contents
	 * in kernel space, therefore we only run this on local cpu.
	 *
	 * XXX This experiment failed, research further... -DaveM
	 */
#if 1
	xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_to_ram), page);
#endif
	local_flush_page_to_ram(page);
}

void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
{
	cpumask_t cpu_mask = mm->cpu_vm_mask;
	cpu_clear(smp_processor_id(), cpu_mask);
	if (!cpus_empty(cpu_mask))
		xc2((smpfunc_t) BTFIXUP_CALL(local_flush_sig_insns), (unsigned long) mm, insn_addr);
	local_flush_sig_insns(mm, insn_addr);
}

extern unsigned int lvl14_resolution;

/* /proc/profile writes can call this, don't __init it please. */
static DEFINE_SPINLOCK(prof_setup_lock);

int setup_profiling_timer(unsigned int multiplier)
{
	int i;
	unsigned long flags;

	/* Prevent level14 ticker IRQ flooding. */
	if((!multiplier) || (lvl14_resolution / multiplier) < 500)
		return -EINVAL;

	spin_lock_irqsave(&prof_setup_lock, flags);
	for_each_possible_cpu(i) {
		load_profile_irq(i, lvl14_resolution / multiplier);
		prof_multiplier(i) = multiplier;
	}
	spin_unlock_irqrestore(&prof_setup_lock, flags);

	return 0;
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	extern void __init smp4m_boot_cpus(void);
	extern void __init smp4d_boot_cpus(void);
	int i, cpuid, extra;

	printk("Entering SMP Mode...\n");

	extra = 0;
	for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
		if (cpuid >= NR_CPUS)
			extra++;
	}
	/* i = number of cpus */
	if (extra && max_cpus > i - extra)
		printk("Warning: NR_CPUS is too low to start all cpus\n");

	smp_store_cpu_info(boot_cpu_id);

	switch(sparc_cpu_model) {
	case sun4:
		printk("SUN4\n");
		BUG();
		break;
	case sun4c:
		printk("SUN4C\n");
		BUG();
		break;
	case sun4m:
		smp4m_boot_cpus();
		break;
	case sun4d:
		smp4d_boot_cpus();
		break;
	case sun4e:
		printk("SUN4E\n");
		BUG();
		break;
	case sun4u:
		printk("SUN4U\n");
		BUG();
		break;
	default:
		printk("UNKNOWN!\n");
		BUG();
		break;
	};
}

/* Set this up early so that things like the scheduler can init
 * properly.  We use the same cpu mask for both the present and
 * possible cpu map.
 */
void __init smp_setup_cpu_possible_map(void)
{
	int instance, mid;

	instance = 0;
	while (!cpu_find_by_instance(instance, NULL, &mid)) {
		if (mid < NR_CPUS) {
			cpu_set(mid, phys_cpu_present_map);
			cpu_set(mid, cpu_present_map);
		}
		instance++;
	}
}

void __init smp_prepare_boot_cpu(void)
{
	int cpuid = hard_smp_processor_id();

	if (cpuid >= NR_CPUS) {
		prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
		prom_halt();
	}
	if (cpuid != 0)
		printk("boot cpu id != 0, this could work but is untested\n");

	current_thread_info()->cpu = cpuid;
	cpu_set(cpuid, cpu_online_map);
	cpu_set(cpuid, phys_cpu_present_map);
}

int __cpuinit __cpu_up(unsigned int cpu)
{
	extern int __cpuinit smp4m_boot_one_cpu(int);
	extern int __cpuinit smp4d_boot_one_cpu(int);
	int ret=0;

	switch(sparc_cpu_model) {
	case sun4:
		printk("SUN4\n");
		BUG();
		break;
	case sun4c:
		printk("SUN4C\n");
		BUG();
		break;
	case sun4m:
		ret = smp4m_boot_one_cpu(cpu);
		break;
	case sun4d:
		ret = smp4d_boot_one_cpu(cpu);
		break;
	case sun4e:
		printk("SUN4E\n");
		BUG();
		break;
	case sun4u:
		printk("SUN4U\n");
		BUG();
		break;
	default:
		printk("UNKNOWN!\n");
		BUG();
		break;
	};

	if (!ret) {
		cpu_set(cpu, smp_commenced_mask);
		while (!cpu_online(cpu))
			mb();
	}
	return ret;
}

void smp_bogo(struct seq_file *m)
{
	int i;
	
	for_each_online_cpu(i) {
		seq_printf(m,
			   "Cpu%dBogo\t: %lu.%02lu\n",
			   i,
			   cpu_data(i).udelay_val/(500000/HZ),
			   (cpu_data(i).udelay_val/(5000/HZ))%100);
	}
}

void smp_info(struct seq_file *m)
{
	int i;

	seq_printf(m, "State:\n");
	for_each_online_cpu(i)
		seq_printf(m, "CPU%d\t\t: online\n", i);
}
Commit	Line	Data
1da177e4 LT	1	/* smp.c: Sparc SMP support.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	4	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
	6	*/
	7
	8	#include <asm/head.h>
	9
	10	#include <linux/kernel.h>
	11	#include <linux/sched.h>
	12	#include <linux/threads.h>
	13	#include <linux/smp.h>
1da177e4 LT	14	#include <linux/interrupt.h>
	15	#include <linux/kernel_stat.h>
	16	#include <linux/init.h>
	17	#include <linux/spinlock.h>
	18	#include <linux/mm.h>
	19	#include <linux/fs.h>
	20	#include <linux/seq_file.h>
	21	#include <linux/cache.h>
	22	#include <linux/delay.h>
	23
	24	#include <asm/ptrace.h>
	25	#include <asm/atomic.h>
	26
	27	#include <asm/irq.h>
	28	#include <asm/page.h>
	29	#include <asm/pgalloc.h>
	30	#include <asm/pgtable.h>
	31	#include <asm/oplib.h>
	32	#include <asm/cacheflush.h>
	33	#include <asm/tlbflush.h>
	34	#include <asm/cpudata.h>
	35
1da177e4 LT	36	int smp_num_cpus = 1;
	37	volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
	38	unsigned char boot_cpu_id = 0;
	39	unsigned char boot_cpu_id4 = 0; /* boot_cpu_id << 2 */
	40	int smp_activated = 0;
	41	volatile int __cpu_number_map[NR_CPUS];
	42	volatile int __cpu_logical_map[NR_CPUS];
	43
	44	cpumask_t cpu_online_map = CPU_MASK_NONE;
	45	cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
a54123e2	46	cpumask_t smp_commenced_mask = CPU_MASK_NONE;
1da177e4 LT	47
	48	/* The only guaranteed locking primitive available on all Sparc
	49	* processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
	50	* places the current byte at the effective address into dest_reg and
	51	* places 0xff there afterwards. Pretty lame locking primitive
	52	* compared to the Alpha and the Intel no? Most Sparcs have 'swap'
	53	* instruction which is much better...
	54	*/
	55
	56	/* Used to make bitops atomic */
	57	unsigned char bitops_spinlock = 0;
	58
92d452f0	59	void __cpuinit smp_store_cpu_info(int id)
1da177e4 LT	60	{
	61	int cpu_node;
	62
	63	cpu_data(id).udelay_val = loops_per_jiffy;
	64
	65	cpu_find_by_mid(id, &cpu_node);
	66	cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
	67	"clock-frequency", 0);
	68	cpu_data(id).prom_node = cpu_node;
	69	cpu_data(id).mid = cpu_get_hwmid(cpu_node);
650fb838 KH	70
	71	/* this is required to tune the scheduler correctly */
	72	/* is it possible to have CPUs with different cache sizes? */
	73	if (id == boot_cpu_id) {
	74	int cache_line,cache_nlines;
	75	cache_line = 0x20;
	76	cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line);
	77	cache_nlines = 0x8000;
	78	cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
	79	max_cache_size = cache_line * cache_nlines;
	80	}
1da177e4 LT	81	if (cpu_data(id).mid < 0)
	82	panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
	83	}
	84
	85	void __init smp_cpus_done(unsigned int max_cpus)
	86	{
a54123e2	87	extern void smp4m_smp_done(void);
8b3c848c	88	extern void smp4d_smp_done(void);
a54123e2 BB	89	unsigned long bogosum = 0;
	90	int cpu, num;
	91
	92	for (cpu = 0, num = 0; cpu < NR_CPUS; cpu++)
	93	if (cpu_online(cpu)) {
	94	num++;
	95	bogosum += cpu_data(cpu).udelay_val;
	96	}
	97
	98	printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
	99	num, bogosum/(500000/HZ),
	100	(bogosum/(5000/HZ))%100);
	101
8b3c848c RB	102	switch(sparc_cpu_model) {
	103	case sun4:
	104	printk("SUN4\n");
	105	BUG();
	106	break;
	107	case sun4c:
	108	printk("SUN4C\n");
	109	BUG();
	110	break;
	111	case sun4m:
	112	smp4m_smp_done();
	113	break;
	114	case sun4d:
	115	smp4d_smp_done();
	116	break;
	117	case sun4e:
	118	printk("SUN4E\n");
	119	BUG();
	120	break;
	121	case sun4u:
	122	printk("SUN4U\n");
	123	BUG();
	124	break;
	125	default:
	126	printk("UNKNOWN!\n");
	127	BUG();
	128	break;
	129	};
1da177e4 LT	130	}
	131
	132	void cpu_panic(void)
	133	{
	134	printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
	135	panic("SMP bolixed\n");
	136	}
	137
	138	struct linux_prom_registers smp_penguin_ctable __initdata = { 0 };
	139
1da177e4 LT	140	void smp_send_reschedule(int cpu)
	141	{
	142	/* See sparc64 */
	143	}
	144
	145	void smp_send_stop(void)
	146	{
	147	}
	148
	149	void smp_flush_cache_all(void)
	150	{
	151	xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all));
	152	local_flush_cache_all();
	153	}
	154
	155	void smp_flush_tlb_all(void)
	156	{
	157	xc0((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_all));
	158	local_flush_tlb_all();
	159	}
	160
	161	void smp_flush_cache_mm(struct mm_struct *mm)
	162	{
	163	if(mm->context != NO_CONTEXT) {
	164	cpumask_t cpu_mask = mm->cpu_vm_mask;
	165	cpu_clear(smp_processor_id(), cpu_mask);
	166	if (!cpus_empty(cpu_mask))
	167	xc1((smpfunc_t) BTFIXUP_CALL(local_flush_cache_mm), (unsigned long) mm);
	168	local_flush_cache_mm(mm);
	169	}
	170	}
	171
	172	void smp_flush_tlb_mm(struct mm_struct *mm)
	173	{
	174	if(mm->context != NO_CONTEXT) {
	175	cpumask_t cpu_mask = mm->cpu_vm_mask;
	176	cpu_clear(smp_processor_id(), cpu_mask);
	177	if (!cpus_empty(cpu_mask)) {
	178	xc1((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_mm), (unsigned long) mm);
	179	if(atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
	180	mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
	181	}
	182	local_flush_tlb_mm(mm);
	183	}
	184	}
	185
	186	void smp_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
	187	unsigned long end)
	188	{
	189	struct mm_struct *mm = vma->vm_mm;
	190
	191	if (mm->context != NO_CONTEXT) {
	192	cpumask_t cpu_mask = mm->cpu_vm_mask;
	193	cpu_clear(smp_processor_id(), cpu_mask);
	194	if (!cpus_empty(cpu_mask))
	195	xc3((smpfunc_t) BTFIXUP_CALL(local_flush_cache_range), (unsigned long) vma, start, end);
	196	local_flush_cache_range(vma, start, end);
	197	}
	198	}
	199
	200	void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	201	unsigned long end)
	202	{
	203	struct mm_struct *mm = vma->vm_mm;
204
205	if (mm->context != NO_CONTEXT) {
206	cpumask_t cpu_mask = mm->cpu_vm_mask;
207	cpu_clear(smp_processor_id(), cpu_mask);
208	if (!cpus_empty(cpu_mask))
209	xc3((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_range), (unsigned long) vma, start, end);
210	local_flush_tlb_range(vma, start, end);
211	}
212	}
213
214	void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
215	{
216	struct mm_struct *mm = vma->vm_mm;
217
218	if(mm->context != NO_CONTEXT) {
219	cpumask_t cpu_mask = mm->cpu_vm_mask;
220	cpu_clear(smp_processor_id(), cpu_mask);
221	if (!cpus_empty(cpu_mask))
222	xc2((smpfunc_t) BTFIXUP_CALL(local_flush_cache_page), (unsigned long) vma, page);
223	local_flush_cache_page(vma, page);
224	}
225	}
226
227	void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
228	{
229	struct mm_struct *mm = vma->vm_mm;
230
231	if(mm->context != NO_CONTEXT) {
232	cpumask_t cpu_mask = mm->cpu_vm_mask;
233	cpu_clear(smp_processor_id(), cpu_mask);
234	if (!cpus_empty(cpu_mask))
235	xc2((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_page), (unsigned long) vma, page);
236	local_flush_tlb_page(vma, page);
237	}
238	}
239
240	void smp_reschedule_irq(void)
241	{
242	set_need_resched();
243	}
244
245	void smp_flush_page_to_ram(unsigned long page)
246	{
247	/* Current theory is that those who call this are the one's
248	* who have just dirtied their cache with the pages contents
249	* in kernel space, therefore we only run this on local cpu.
250	*
251	* XXX This experiment failed, research further... -DaveM
252	*/
253	#if 1
254	xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_to_ram), page);
255	#endif
256	local_flush_page_to_ram(page);
257	}
258
259	void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
260	{
261	cpumask_t cpu_mask = mm->cpu_vm_mask;
262	cpu_clear(smp_processor_id(), cpu_mask);
263	if (!cpus_empty(cpu_mask))
264	xc2((smpfunc_t) BTFIXUP_CALL(local_flush_sig_insns), (unsigned long) mm, insn_addr);
265	local_flush_sig_insns(mm, insn_addr);
266	}
267
268	extern unsigned int lvl14_resolution;
269
270	/* /proc/profile writes can call this, don't __init it please. */
271	static DEFINE_SPINLOCK(prof_setup_lock);
272
273	int setup_profiling_timer(unsigned int multiplier)
274	{
275	int i;
276	unsigned long flags;
277
278	/* Prevent level14 ticker IRQ flooding. */
279	if((!multiplier) \|\| (lvl14_resolution / multiplier) < 500)
280	return -EINVAL;
281
282	spin_lock_irqsave(&prof_setup_lock, flags);
fff8efe7	283	for_each_possible_cpu(i) {
394e3902	284	load_profile_irq(i, lvl14_resolution / multiplier);
1da177e4 LT	285	prof_multiplier(i) = multiplier;
	286	}
	287	spin_unlock_irqrestore(&prof_setup_lock, flags);
	288
	289	return 0;
	290	}
	291
a54123e2	292	void __init smp_prepare_cpus(unsigned int max_cpus)
1da177e4	293	{
b4cff846 AV	294	extern void __init smp4m_boot_cpus(void);
b4cff846 AV	295	extern void __init smp4d_boot_cpus(void);
7202fb49	296	int i, cpuid, extra;
a54123e2	297
a54123e2 BB	298	printk("Entering SMP Mode...\n");
a54123e2 BB	299
a54123e2 BB	300	extra = 0;
a54123e2 BB	301	for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
7202fb49	302	if (cpuid >= NR_CPUS)
a54123e2 BB	303	extra++;
a54123e2 BB	304	}
7202fb49 BB	305	/* i = number of cpus */
7202fb49 BB	306	if (extra && max_cpus > i - extra)
a54123e2 BB	307	printk("Warning: NR_CPUS is too low to start all cpus\n");
	308
	309	smp_store_cpu_info(boot_cpu_id);
	310
8b3c848c RB	311	switch(sparc_cpu_model) {
	312	case sun4:
	313	printk("SUN4\n");
	314	BUG();
	315	break;
	316	case sun4c:
	317	printk("SUN4C\n");
	318	BUG();
	319	break;
	320	case sun4m:
	321	smp4m_boot_cpus();
	322	break;
	323	case sun4d:
	324	smp4d_boot_cpus();
	325	break;
	326	case sun4e:
	327	printk("SUN4E\n");
	328	BUG();
	329	break;
	330	case sun4u:
	331	printk("SUN4U\n");
	332	BUG();
	333	break;
	334	default:
	335	printk("UNKNOWN!\n");
	336	BUG();
	337	break;
	338	};
1da177e4 LT	339	}
1da177e4 LT	340
7202fb49 BB	341	/* Set this up early so that things like the scheduler can init
	342	* properly. We use the same cpu mask for both the present and
	343	* possible cpu map.
	344	*/
	345	void __init smp_setup_cpu_possible_map(void)
	346	{
	347	int instance, mid;
	348
	349	instance = 0;
	350	while (!cpu_find_by_instance(instance, NULL, &mid)) {
	351	if (mid < NR_CPUS) {
	352	cpu_set(mid, phys_cpu_present_map);
	353	cpu_set(mid, cpu_present_map);
	354	}
	355	instance++;
	356	}
	357	}
	358
92d452f0	359	void __init smp_prepare_boot_cpu(void)
1da177e4	360	{
a54123e2 BB	361	int cpuid = hard_smp_processor_id();
	362
	363	if (cpuid >= NR_CPUS) {
	364	prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
	365	prom_halt();
	366	}
	367	if (cpuid != 0)
	368	printk("boot cpu id != 0, this could work but is untested\n");
	369
	370	current_thread_info()->cpu = cpuid;
	371	cpu_set(cpuid, cpu_online_map);
	372	cpu_set(cpuid, phys_cpu_present_map);
1da177e4 LT	373	}
1da177e4 LT	374
92d452f0	375	int __cpuinit __cpu_up(unsigned int cpu)
1da177e4	376	{
b4cff846 AV	377	extern int __cpuinit smp4m_boot_one_cpu(int);
b4cff846 AV	378	extern int __cpuinit smp4d_boot_one_cpu(int);
8b3c848c RB	379	int ret=0;
	380
	381	switch(sparc_cpu_model) {
	382	case sun4:
	383	printk("SUN4\n");
	384	BUG();
	385	break;
	386	case sun4c:
	387	printk("SUN4C\n");
	388	BUG();
	389	break;
	390	case sun4m:
	391	ret = smp4m_boot_one_cpu(cpu);
	392	break;
	393	case sun4d:
	394	ret = smp4d_boot_one_cpu(cpu);
	395	break;
	396	case sun4e:
	397	printk("SUN4E\n");
	398	BUG();
	399	break;
	400	case sun4u:
	401	printk("SUN4U\n");
	402	BUG();
	403	break;
	404	default:
	405	printk("UNKNOWN!\n");
	406	BUG();
	407	break;
	408	};
a54123e2 BB	409
	410	if (!ret) {
	411	cpu_set(cpu, smp_commenced_mask);
	412	while (!cpu_online(cpu))
	413	mb();
	414	}
	415	return ret;
1da177e4 LT	416	}
	417
	418	void smp_bogo(struct seq_file *m)
	419	{
	420	int i;
	421
394e3902 AM	422	for_each_online_cpu(i) {
	423	seq_printf(m,
	424	"Cpu%dBogo\t: %lu.%02lu\n",
	425	i,
	426	cpu_data(i).udelay_val/(500000/HZ),
	427	(cpu_data(i).udelay_val/(5000/HZ))%100);
1da177e4 LT	428	}
	429	}
	430
	431	void smp_info(struct seq_file *m)
	432	{
	433	int i;
	434
	435	seq_printf(m, "State:\n");
394e3902 AM	436	for_each_online_cpu(i)
394e3902 AM	437	seq_printf(m, "CPU%d\t\t: online\n", i);
1da177e4	438	}