Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/sh/kernel/smp.c | |
3 | * | |
4 | * SMP support for the SuperH processors. | |
5 | * | |
3366e358 | 6 | * Copyright (C) 2002 - 2010 Paul Mundt |
aba1030a | 7 | * Copyright (C) 2006 - 2007 Akio Idehara |
1da177e4 | 8 | * |
aba1030a PM |
9 | * This file is subject to the terms and conditions of the GNU General Public |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
1da177e4 | 12 | */ |
66c5227e | 13 | #include <linux/err.h> |
1da177e4 LT |
14 | #include <linux/cache.h> |
15 | #include <linux/cpumask.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
1da177e4 | 18 | #include <linux/spinlock.h> |
aba1030a | 19 | #include <linux/mm.h> |
1da177e4 | 20 | #include <linux/module.h> |
b56050ae | 21 | #include <linux/cpu.h> |
aba1030a | 22 | #include <linux/interrupt.h> |
184748cc | 23 | #include <linux/sched.h> |
60063497 | 24 | #include <linux/atomic.h> |
1da177e4 | 25 | #include <asm/processor.h> |
1da177e4 LT |
26 | #include <asm/mmu_context.h> |
27 | #include <asm/smp.h> | |
aba1030a PM |
28 | #include <asm/cacheflush.h> |
29 | #include <asm/sections.h> | |
f03c4866 | 30 | #include <asm/setup.h> |
1da177e4 | 31 | |
aba1030a PM |
32 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
33 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | |
1da177e4 | 34 | |
3366e358 PM |
35 | struct plat_smp_ops *mp_ops = NULL; |
36 | ||
9715b8c7 PM |
37 | /* State of each CPU */ |
38 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
39 | ||
3366e358 PM |
40 | void __cpuinit register_smp_ops(struct plat_smp_ops *ops) |
41 | { | |
42 | if (mp_ops) | |
43 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
44 | ||
45 | mp_ops = ops; | |
46 | } | |
47 | ||
1cfa1e8f | 48 | static inline void __cpuinit smp_store_cpu_info(unsigned int cpu) |
1da177e4 | 49 | { |
aba1030a PM |
50 | struct sh_cpuinfo *c = cpu_data + cpu; |
51 | ||
a66c2ede PM |
52 | memcpy(c, &boot_cpu_data, sizeof(struct sh_cpuinfo)); |
53 | ||
aba1030a | 54 | c->loops_per_jiffy = loops_per_jiffy; |
1da177e4 LT |
55 | } |
56 | ||
57 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
58 | { | |
59 | unsigned int cpu = smp_processor_id(); | |
1da177e4 | 60 | |
aba1030a PM |
61 | init_new_context(current, &init_mm); |
62 | current_thread_info()->cpu = cpu; | |
3366e358 | 63 | mp_ops->prepare_cpus(max_cpus); |
aba1030a PM |
64 | |
65 | #ifndef CONFIG_HOTPLUG_CPU | |
004f4ce9 | 66 | init_cpu_present(cpu_possible_mask); |
aba1030a | 67 | #endif |
1da177e4 LT |
68 | } |
69 | ||
1cfa1e8f | 70 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
71 | { |
72 | unsigned int cpu = smp_processor_id(); | |
73 | ||
aba1030a PM |
74 | __cpu_number_map[0] = cpu; |
75 | __cpu_logical_map[0] = cpu; | |
76 | ||
e09377ba RR |
77 | set_cpu_online(cpu, true); |
78 | set_cpu_possible(cpu, true); | |
9715b8c7 PM |
79 | |
80 | per_cpu(cpu_state, cpu) = CPU_ONLINE; | |
1da177e4 LT |
81 | } |
82 | ||
763142d1 PM |
83 | #ifdef CONFIG_HOTPLUG_CPU |
84 | void native_cpu_die(unsigned int cpu) | |
85 | { | |
86 | unsigned int i; | |
87 | ||
88 | for (i = 0; i < 10; i++) { | |
89 | smp_rmb(); | |
90 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
91 | if (system_state == SYSTEM_RUNNING) | |
92 | pr_info("CPU %u is now offline\n", cpu); | |
93 | ||
94 | return; | |
95 | } | |
96 | ||
97 | msleep(100); | |
98 | } | |
99 | ||
100 | pr_err("CPU %u didn't die...\n", cpu); | |
101 | } | |
102 | ||
103 | int native_cpu_disable(unsigned int cpu) | |
104 | { | |
105 | return cpu == 0 ? -EPERM : 0; | |
106 | } | |
107 | ||
108 | void play_dead_common(void) | |
109 | { | |
110 | idle_task_exit(); | |
111 | irq_ctx_exit(raw_smp_processor_id()); | |
112 | mb(); | |
113 | ||
114 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
115 | local_irq_disable(); | |
116 | } | |
117 | ||
118 | void native_play_dead(void) | |
119 | { | |
120 | play_dead_common(); | |
121 | } | |
122 | ||
123 | int __cpu_disable(void) | |
124 | { | |
125 | unsigned int cpu = smp_processor_id(); | |
763142d1 PM |
126 | int ret; |
127 | ||
128 | ret = mp_ops->cpu_disable(cpu); | |
129 | if (ret) | |
130 | return ret; | |
131 | ||
132 | /* | |
133 | * Take this CPU offline. Once we clear this, we can't return, | |
134 | * and we must not schedule until we're ready to give up the cpu. | |
135 | */ | |
136 | set_cpu_online(cpu, false); | |
137 | ||
138 | /* | |
139 | * OK - migrate IRQs away from this CPU | |
140 | */ | |
141 | migrate_irqs(); | |
142 | ||
143 | /* | |
144 | * Stop the local timer for this CPU. | |
145 | */ | |
146 | local_timer_stop(cpu); | |
147 | ||
148 | /* | |
149 | * Flush user cache and TLB mappings, and then remove this CPU | |
150 | * from the vm mask set of all processes. | |
151 | */ | |
152 | flush_cache_all(); | |
153 | local_flush_tlb_all(); | |
154 | ||
1198c8b9 | 155 | clear_tasks_mm_cpumask(cpu); |
763142d1 PM |
156 | |
157 | return 0; | |
158 | } | |
159 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1483feac | 160 | int native_cpu_disable(unsigned int cpu) |
763142d1 PM |
161 | { |
162 | return -ENOSYS; | |
163 | } | |
164 | ||
165 | void native_cpu_die(unsigned int cpu) | |
166 | { | |
167 | /* We said "no" in __cpu_disable */ | |
168 | BUG(); | |
169 | } | |
170 | ||
171 | void native_play_dead(void) | |
172 | { | |
173 | BUG(); | |
174 | } | |
175 | #endif | |
176 | ||
aba1030a | 177 | asmlinkage void __cpuinit start_secondary(void) |
1da177e4 | 178 | { |
9715b8c7 | 179 | unsigned int cpu = smp_processor_id(); |
aba1030a | 180 | struct mm_struct *mm = &init_mm; |
1da177e4 | 181 | |
4bea3418 | 182 | enable_mmu(); |
aba1030a PM |
183 | atomic_inc(&mm->mm_count); |
184 | atomic_inc(&mm->mm_users); | |
185 | current->active_mm = mm; | |
aba1030a | 186 | enter_lazy_tlb(mm, current); |
763142d1 | 187 | local_flush_tlb_all(); |
aba1030a PM |
188 | |
189 | per_cpu_trap_init(); | |
190 | ||
191 | preempt_disable(); | |
192 | ||
9715b8c7 | 193 | notify_cpu_starting(cpu); |
e545a614 | 194 | |
aba1030a | 195 | local_irq_enable(); |
1da177e4 | 196 | |
8c24594d PM |
197 | /* Enable local timers */ |
198 | local_timer_setup(cpu); | |
aba1030a PM |
199 | calibrate_delay(); |
200 | ||
aba1030a | 201 | smp_store_cpu_info(cpu); |
1da177e4 | 202 | |
f0ccf277 | 203 | set_cpu_online(cpu, true); |
9715b8c7 | 204 | per_cpu(cpu_state, cpu) = CPU_ONLINE; |
1da177e4 | 205 | |
dc775dd8 | 206 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
207 | } |
208 | ||
aba1030a PM |
209 | extern struct { |
210 | unsigned long sp; | |
211 | unsigned long bss_start; | |
212 | unsigned long bss_end; | |
213 | void *start_kernel_fn; | |
214 | void *cpu_init_fn; | |
215 | void *thread_info; | |
216 | } stack_start; | |
217 | ||
ea0588cb | 218 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tsk) |
1da177e4 | 219 | { |
aba1030a | 220 | unsigned long timeout; |
5bfb5d69 | 221 | |
9715b8c7 PM |
222 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
223 | ||
aba1030a PM |
224 | /* Fill in data in head.S for secondary cpus */ |
225 | stack_start.sp = tsk->thread.sp; | |
226 | stack_start.thread_info = tsk->stack; | |
227 | stack_start.bss_start = 0; /* don't clear bss for secondary cpus */ | |
228 | stack_start.start_kernel_fn = start_secondary; | |
1da177e4 | 229 | |
d780613a PM |
230 | flush_icache_range((unsigned long)&stack_start, |
231 | (unsigned long)&stack_start + sizeof(stack_start)); | |
232 | wmb(); | |
1da177e4 | 233 | |
3366e358 | 234 | mp_ops->start_cpu(cpu, (unsigned long)_stext); |
1da177e4 | 235 | |
aba1030a PM |
236 | timeout = jiffies + HZ; |
237 | while (time_before(jiffies, timeout)) { | |
238 | if (cpu_online(cpu)) | |
239 | break; | |
240 | ||
241 | udelay(10); | |
763142d1 | 242 | barrier(); |
aba1030a PM |
243 | } |
244 | ||
245 | if (cpu_online(cpu)) | |
246 | return 0; | |
247 | ||
248 | return -ENOENT; | |
1da177e4 LT |
249 | } |
250 | ||
251 | void __init smp_cpus_done(unsigned int max_cpus) | |
252 | { | |
aba1030a PM |
253 | unsigned long bogosum = 0; |
254 | int cpu; | |
255 | ||
256 | for_each_online_cpu(cpu) | |
257 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
258 | ||
259 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
260 | "(%lu.%02lu BogoMIPS).\n", num_online_cpus(), | |
261 | bogosum / (500000/HZ), | |
262 | (bogosum / (5000/HZ)) % 100); | |
1da177e4 LT |
263 | } |
264 | ||
265 | void smp_send_reschedule(int cpu) | |
266 | { | |
3366e358 | 267 | mp_ops->send_ipi(cpu, SMP_MSG_RESCHEDULE); |
1da177e4 LT |
268 | } |
269 | ||
1da177e4 LT |
270 | void smp_send_stop(void) |
271 | { | |
8691e5a8 | 272 | smp_call_function(stop_this_cpu, 0, 0); |
1da177e4 LT |
273 | } |
274 | ||
819807df | 275 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 276 | { |
490f5de5 | 277 | int cpu; |
1da177e4 | 278 | |
819807df | 279 | for_each_cpu(cpu, mask) |
3366e358 | 280 | mp_ops->send_ipi(cpu, SMP_MSG_FUNCTION); |
490f5de5 | 281 | } |
1da177e4 | 282 | |
490f5de5 JA |
283 | void arch_send_call_function_single_ipi(int cpu) |
284 | { | |
3366e358 | 285 | mp_ops->send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE); |
1da177e4 LT |
286 | } |
287 | ||
320ab2b0 | 288 | void smp_timer_broadcast(const struct cpumask *mask) |
6f52707e PM |
289 | { |
290 | int cpu; | |
291 | ||
320ab2b0 | 292 | for_each_cpu(cpu, mask) |
3366e358 | 293 | mp_ops->send_ipi(cpu, SMP_MSG_TIMER); |
6f52707e PM |
294 | } |
295 | ||
296 | static void ipi_timer(void) | |
297 | { | |
298 | irq_enter(); | |
8c24594d | 299 | local_timer_interrupt(); |
6f52707e PM |
300 | irq_exit(); |
301 | } | |
302 | ||
173a44dd PM |
303 | void smp_message_recv(unsigned int msg) |
304 | { | |
305 | switch (msg) { | |
306 | case SMP_MSG_FUNCTION: | |
307 | generic_smp_call_function_interrupt(); | |
308 | break; | |
309 | case SMP_MSG_RESCHEDULE: | |
184748cc | 310 | scheduler_ipi(); |
173a44dd PM |
311 | break; |
312 | case SMP_MSG_FUNCTION_SINGLE: | |
313 | generic_smp_call_function_single_interrupt(); | |
314 | break; | |
6f52707e PM |
315 | case SMP_MSG_TIMER: |
316 | ipi_timer(); | |
317 | break; | |
173a44dd PM |
318 | default: |
319 | printk(KERN_WARNING "SMP %d: %s(): unknown IPI %d\n", | |
320 | smp_processor_id(), __func__, msg); | |
321 | break; | |
322 | } | |
323 | } | |
324 | ||
1da177e4 LT |
325 | /* Not really SMP stuff ... */ |
326 | int setup_profiling_timer(unsigned int multiplier) | |
327 | { | |
328 | return 0; | |
329 | } | |
330 | ||
9964fa8b PM |
331 | static void flush_tlb_all_ipi(void *info) |
332 | { | |
333 | local_flush_tlb_all(); | |
334 | } | |
335 | ||
336 | void flush_tlb_all(void) | |
337 | { | |
15c8b6c1 | 338 | on_each_cpu(flush_tlb_all_ipi, 0, 1); |
9964fa8b PM |
339 | } |
340 | ||
341 | static void flush_tlb_mm_ipi(void *mm) | |
342 | { | |
343 | local_flush_tlb_mm((struct mm_struct *)mm); | |
344 | } | |
345 | ||
346 | /* | |
347 | * The following tlb flush calls are invoked when old translations are | |
348 | * being torn down, or pte attributes are changing. For single threaded | |
349 | * address spaces, a new context is obtained on the current cpu, and tlb | |
350 | * context on other cpus are invalidated to force a new context allocation | |
351 | * at switch_mm time, should the mm ever be used on other cpus. For | |
352 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
353 | * Another case where intercpu interrupts are required is when the target | |
354 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
355 | * behalf of debugees, kswapd stealing pages from another process etc). | |
356 | * Kanoj 07/00. | |
357 | */ | |
9964fa8b PM |
358 | void flush_tlb_mm(struct mm_struct *mm) |
359 | { | |
360 | preempt_disable(); | |
361 | ||
362 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
8691e5a8 | 363 | smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1); |
9964fa8b PM |
364 | } else { |
365 | int i; | |
366 | for (i = 0; i < num_online_cpus(); i++) | |
367 | if (smp_processor_id() != i) | |
368 | cpu_context(i, mm) = 0; | |
369 | } | |
370 | local_flush_tlb_mm(mm); | |
371 | ||
372 | preempt_enable(); | |
373 | } | |
374 | ||
375 | struct flush_tlb_data { | |
376 | struct vm_area_struct *vma; | |
377 | unsigned long addr1; | |
378 | unsigned long addr2; | |
379 | }; | |
380 | ||
381 | static void flush_tlb_range_ipi(void *info) | |
382 | { | |
383 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
384 | ||
385 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
386 | } | |
387 | ||
388 | void flush_tlb_range(struct vm_area_struct *vma, | |
389 | unsigned long start, unsigned long end) | |
390 | { | |
391 | struct mm_struct *mm = vma->vm_mm; | |
392 | ||
393 | preempt_disable(); | |
394 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
395 | struct flush_tlb_data fd; | |
396 | ||
397 | fd.vma = vma; | |
398 | fd.addr1 = start; | |
399 | fd.addr2 = end; | |
8691e5a8 | 400 | smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1); |
9964fa8b PM |
401 | } else { |
402 | int i; | |
403 | for (i = 0; i < num_online_cpus(); i++) | |
404 | if (smp_processor_id() != i) | |
405 | cpu_context(i, mm) = 0; | |
406 | } | |
407 | local_flush_tlb_range(vma, start, end); | |
408 | preempt_enable(); | |
409 | } | |
410 | ||
411 | static void flush_tlb_kernel_range_ipi(void *info) | |
412 | { | |
413 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
414 | ||
415 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
416 | } | |
417 | ||
418 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
419 | { | |
420 | struct flush_tlb_data fd; | |
421 | ||
422 | fd.addr1 = start; | |
423 | fd.addr2 = end; | |
15c8b6c1 | 424 | on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1); |
9964fa8b PM |
425 | } |
426 | ||
427 | static void flush_tlb_page_ipi(void *info) | |
428 | { | |
429 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
430 | ||
431 | local_flush_tlb_page(fd->vma, fd->addr1); | |
432 | } | |
433 | ||
434 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
435 | { | |
436 | preempt_disable(); | |
437 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || | |
438 | (current->mm != vma->vm_mm)) { | |
439 | struct flush_tlb_data fd; | |
440 | ||
441 | fd.vma = vma; | |
442 | fd.addr1 = page; | |
8691e5a8 | 443 | smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1); |
9964fa8b PM |
444 | } else { |
445 | int i; | |
446 | for (i = 0; i < num_online_cpus(); i++) | |
447 | if (smp_processor_id() != i) | |
448 | cpu_context(i, vma->vm_mm) = 0; | |
449 | } | |
450 | local_flush_tlb_page(vma, page); | |
451 | preempt_enable(); | |
452 | } | |
453 | ||
454 | static void flush_tlb_one_ipi(void *info) | |
455 | { | |
456 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
457 | local_flush_tlb_one(fd->addr1, fd->addr2); | |
458 | } | |
459 | ||
460 | void flush_tlb_one(unsigned long asid, unsigned long vaddr) | |
461 | { | |
462 | struct flush_tlb_data fd; | |
463 | ||
464 | fd.addr1 = asid; | |
465 | fd.addr2 = vaddr; | |
466 | ||
8691e5a8 | 467 | smp_call_function(flush_tlb_one_ipi, (void *)&fd, 1); |
9964fa8b PM |
468 | local_flush_tlb_one(asid, vaddr); |
469 | } |