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ac44e669 PM |
1 | /* |
2 | * Performance event support framework for SuperH hardware counters. | |
3 | * | |
4 | * Copyright (C) 2009 Paul Mundt | |
5 | * | |
6 | * Heavily based on the x86 and PowerPC implementations. | |
7 | * | |
8 | * x86: | |
9 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
10 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
11 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
12 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
13 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
14 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
15 | * | |
16 | * ppc: | |
17 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
18 | * | |
19 | * This file is subject to the terms and conditions of the GNU General Public | |
20 | * License. See the file "COPYING" in the main directory of this archive | |
21 | * for more details. | |
22 | */ | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/perf_event.h> | |
28 | #include <asm/processor.h> | |
29 | ||
30 | struct cpu_hw_events { | |
31 | struct perf_event *events[MAX_HWEVENTS]; | |
32 | unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; | |
33 | unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; | |
34 | }; | |
35 | ||
36 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | |
37 | ||
38 | static struct sh_pmu *sh_pmu __read_mostly; | |
39 | ||
40 | /* Number of perf_events counting hardware events */ | |
41 | static atomic_t num_events; | |
42 | /* Used to avoid races in calling reserve/release_pmc_hardware */ | |
43 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
44 | ||
45 | /* | |
46 | * Stub these out for now, do something more profound later. | |
47 | */ | |
48 | int reserve_pmc_hardware(void) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | void release_pmc_hardware(void) | |
54 | { | |
55 | } | |
56 | ||
57 | static inline int sh_pmu_initialized(void) | |
58 | { | |
59 | return !!sh_pmu; | |
60 | } | |
61 | ||
3bf101ba MF |
62 | int perf_num_counters(void) |
63 | { | |
64 | if (!sh_pmu) | |
65 | return 0; | |
66 | ||
67 | return sh_pmu->num_events; | |
68 | } | |
69 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
70 | ||
ac44e669 PM |
71 | /* |
72 | * Release the PMU if this is the last perf_event. | |
73 | */ | |
74 | static void hw_perf_event_destroy(struct perf_event *event) | |
75 | { | |
76 | if (!atomic_add_unless(&num_events, -1, 1)) { | |
77 | mutex_lock(&pmc_reserve_mutex); | |
78 | if (atomic_dec_return(&num_events) == 0) | |
79 | release_pmc_hardware(); | |
80 | mutex_unlock(&pmc_reserve_mutex); | |
81 | } | |
82 | } | |
83 | ||
84 | static int hw_perf_cache_event(int config, int *evp) | |
85 | { | |
86 | unsigned long type, op, result; | |
87 | int ev; | |
88 | ||
89 | if (!sh_pmu->cache_events) | |
90 | return -EINVAL; | |
91 | ||
92 | /* unpack config */ | |
93 | type = config & 0xff; | |
94 | op = (config >> 8) & 0xff; | |
95 | result = (config >> 16) & 0xff; | |
96 | ||
97 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
98 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
99 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
100 | return -EINVAL; | |
101 | ||
102 | ev = (*sh_pmu->cache_events)[type][op][result]; | |
103 | if (ev == 0) | |
104 | return -EOPNOTSUPP; | |
105 | if (ev == -1) | |
106 | return -EINVAL; | |
107 | *evp = ev; | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int __hw_perf_event_init(struct perf_event *event) | |
112 | { | |
113 | struct perf_event_attr *attr = &event->attr; | |
114 | struct hw_perf_event *hwc = &event->hw; | |
8820002c | 115 | int config = -1; |
ac44e669 PM |
116 | int err; |
117 | ||
118 | if (!sh_pmu_initialized()) | |
119 | return -ENODEV; | |
120 | ||
121 | /* | |
122 | * All of the on-chip counters are "limited", in that they have | |
123 | * no interrupts, and are therefore unable to do sampling without | |
124 | * further work and timer assistance. | |
125 | */ | |
126 | if (hwc->sample_period) | |
127 | return -EINVAL; | |
128 | ||
129 | /* | |
130 | * See if we need to reserve the counter. | |
131 | * | |
132 | * If no events are currently in use, then we have to take a | |
133 | * mutex to ensure that we don't race with another task doing | |
134 | * reserve_pmc_hardware or release_pmc_hardware. | |
135 | */ | |
136 | err = 0; | |
137 | if (!atomic_inc_not_zero(&num_events)) { | |
138 | mutex_lock(&pmc_reserve_mutex); | |
139 | if (atomic_read(&num_events) == 0 && | |
140 | reserve_pmc_hardware()) | |
141 | err = -EBUSY; | |
142 | else | |
143 | atomic_inc(&num_events); | |
144 | mutex_unlock(&pmc_reserve_mutex); | |
145 | } | |
146 | ||
147 | if (err) | |
148 | return err; | |
149 | ||
150 | event->destroy = hw_perf_event_destroy; | |
151 | ||
152 | switch (attr->type) { | |
153 | case PERF_TYPE_RAW: | |
154 | config = attr->config & sh_pmu->raw_event_mask; | |
155 | break; | |
156 | case PERF_TYPE_HW_CACHE: | |
157 | err = hw_perf_cache_event(attr->config, &config); | |
158 | if (err) | |
159 | return err; | |
160 | break; | |
161 | case PERF_TYPE_HARDWARE: | |
162 | if (attr->config >= sh_pmu->max_events) | |
163 | return -EINVAL; | |
164 | ||
165 | config = sh_pmu->event_map(attr->config); | |
166 | break; | |
ac44e669 PM |
167 | } |
168 | ||
169 | if (config == -1) | |
170 | return -EINVAL; | |
171 | ||
172 | hwc->config |= config; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static void sh_perf_event_update(struct perf_event *event, | |
178 | struct hw_perf_event *hwc, int idx) | |
179 | { | |
180 | u64 prev_raw_count, new_raw_count; | |
181 | s64 delta; | |
182 | int shift = 0; | |
183 | ||
184 | /* | |
185 | * Depending on the counter configuration, they may or may not | |
186 | * be chained, in which case the previous counter value can be | |
187 | * updated underneath us if the lower-half overflows. | |
188 | * | |
189 | * Our tactic to handle this is to first atomically read and | |
190 | * exchange a new raw count - then add that new-prev delta | |
191 | * count to the generic counter atomically. | |
192 | * | |
193 | * As there is no interrupt associated with the overflow events, | |
194 | * this is the simplest approach for maintaining consistency. | |
195 | */ | |
196 | again: | |
e7850595 | 197 | prev_raw_count = local64_read(&hwc->prev_count); |
ac44e669 PM |
198 | new_raw_count = sh_pmu->read(idx); |
199 | ||
e7850595 | 200 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ac44e669 PM |
201 | new_raw_count) != prev_raw_count) |
202 | goto again; | |
203 | ||
204 | /* | |
205 | * Now we have the new raw value and have updated the prev | |
206 | * timestamp already. We can now calculate the elapsed delta | |
207 | * (counter-)time and add that to the generic counter. | |
208 | * | |
209 | * Careful, not all hw sign-extends above the physical width | |
210 | * of the count. | |
211 | */ | |
212 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
213 | delta >>= shift; | |
214 | ||
e7850595 | 215 | local64_add(delta, &event->count); |
ac44e669 PM |
216 | } |
217 | ||
218 | static void sh_pmu_disable(struct perf_event *event) | |
219 | { | |
220 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
221 | struct hw_perf_event *hwc = &event->hw; | |
222 | int idx = hwc->idx; | |
223 | ||
224 | clear_bit(idx, cpuc->active_mask); | |
225 | sh_pmu->disable(hwc, idx); | |
226 | ||
227 | barrier(); | |
228 | ||
229 | sh_perf_event_update(event, &event->hw, idx); | |
230 | ||
231 | cpuc->events[idx] = NULL; | |
232 | clear_bit(idx, cpuc->used_mask); | |
233 | ||
234 | perf_event_update_userpage(event); | |
235 | } | |
236 | ||
237 | static int sh_pmu_enable(struct perf_event *event) | |
238 | { | |
239 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
240 | struct hw_perf_event *hwc = &event->hw; | |
241 | int idx = hwc->idx; | |
242 | ||
243 | if (test_and_set_bit(idx, cpuc->used_mask)) { | |
244 | idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); | |
245 | if (idx == sh_pmu->num_events) | |
246 | return -EAGAIN; | |
247 | ||
248 | set_bit(idx, cpuc->used_mask); | |
249 | hwc->idx = idx; | |
250 | } | |
251 | ||
252 | sh_pmu->disable(hwc, idx); | |
253 | ||
254 | cpuc->events[idx] = event; | |
255 | set_bit(idx, cpuc->active_mask); | |
256 | ||
257 | sh_pmu->enable(hwc, idx); | |
258 | ||
259 | perf_event_update_userpage(event); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static void sh_pmu_read(struct perf_event *event) | |
265 | { | |
266 | sh_perf_event_update(event, &event->hw, event->hw.idx); | |
267 | } | |
268 | ||
269 | static const struct pmu pmu = { | |
270 | .enable = sh_pmu_enable, | |
271 | .disable = sh_pmu_disable, | |
272 | .read = sh_pmu_read, | |
273 | }; | |
274 | ||
275 | const struct pmu *hw_perf_event_init(struct perf_event *event) | |
276 | { | |
277 | int err = __hw_perf_event_init(event); | |
278 | if (unlikely(err)) { | |
279 | if (event->destroy) | |
280 | event->destroy(event); | |
281 | return ERR_PTR(err); | |
282 | } | |
283 | ||
284 | return &pmu; | |
285 | } | |
286 | ||
3f6da390 | 287 | static void sh_pmu_setup(int cpu) |
ac44e669 PM |
288 | { |
289 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); | |
290 | ||
291 | memset(cpuhw, 0, sizeof(struct cpu_hw_events)); | |
292 | } | |
293 | ||
3f6da390 PZ |
294 | static int __cpuinit |
295 | sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
296 | { | |
297 | unsigned int cpu = (long)hcpu; | |
298 | ||
299 | switch (action & ~CPU_TASKS_FROZEN) { | |
300 | case CPU_UP_PREPARE: | |
301 | sh_pmu_setup(cpu); | |
302 | break; | |
303 | ||
304 | default: | |
305 | break; | |
306 | } | |
307 | ||
308 | return NOTIFY_OK; | |
309 | } | |
310 | ||
ac44e669 PM |
311 | void hw_perf_enable(void) |
312 | { | |
313 | if (!sh_pmu_initialized()) | |
314 | return; | |
315 | ||
316 | sh_pmu->enable_all(); | |
317 | } | |
318 | ||
319 | void hw_perf_disable(void) | |
320 | { | |
321 | if (!sh_pmu_initialized()) | |
322 | return; | |
323 | ||
324 | sh_pmu->disable_all(); | |
325 | } | |
326 | ||
90851c40 | 327 | int __cpuinit register_sh_pmu(struct sh_pmu *pmu) |
ac44e669 PM |
328 | { |
329 | if (sh_pmu) | |
330 | return -EBUSY; | |
331 | sh_pmu = pmu; | |
332 | ||
333 | pr_info("Performance Events: %s support registered\n", pmu->name); | |
334 | ||
1d317f90 | 335 | WARN_ON(pmu->num_events > MAX_HWEVENTS); |
ac44e669 | 336 | |
3f6da390 | 337 | perf_cpu_notifier(sh_pmu_notifier); |
ac44e669 PM |
338 | return 0; |
339 | } |