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1 | /* |
2 | * SuperH KGDB support | |
3 | * | |
4 | * Copyright (C) 2008 Paul Mundt | |
5 | * | |
6 | * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel. | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/kgdb.h> | |
13 | #include <linux/kdebug.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
16 | #include <asm/cacheflush.h> | |
17 | ||
18 | char in_nmi = 0; /* Set during NMI to prevent re-entry */ | |
19 | ||
20 | /* Macros for single step instruction identification */ | |
21 | #define OPCODE_BT(op) (((op) & 0xff00) == 0x8900) | |
22 | #define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00) | |
23 | #define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \ | |
24 | (((op) & 0x7f ) << 1)) | |
25 | #define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00) | |
26 | #define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00) | |
27 | #define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000) | |
28 | #define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ | |
29 | (((op) & 0x7ff) << 1)) | |
30 | #define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023) | |
31 | #define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8) | |
32 | #define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000) | |
33 | #define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ | |
34 | (((op) & 0x7ff) << 1)) | |
35 | #define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003) | |
36 | #define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf) | |
37 | #define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b) | |
38 | #define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf) | |
39 | #define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b) | |
40 | #define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf) | |
41 | #define OPCODE_RTS(op) ((op) == 0xb) | |
42 | #define OPCODE_RTE(op) ((op) == 0x2b) | |
43 | ||
44 | #define SR_T_BIT_MASK 0x1 | |
45 | #define STEP_OPCODE 0xc33d | |
46 | ||
47 | /* Calculate the new address for after a step */ | |
48 | static short *get_step_address(struct pt_regs *linux_regs) | |
49 | { | |
50 | opcode_t op = __raw_readw(linux_regs->pc); | |
51 | long addr; | |
52 | ||
53 | /* BT */ | |
54 | if (OPCODE_BT(op)) { | |
55 | if (linux_regs->sr & SR_T_BIT_MASK) | |
56 | addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); | |
57 | else | |
58 | addr = linux_regs->pc + 2; | |
59 | } | |
60 | ||
61 | /* BTS */ | |
62 | else if (OPCODE_BTS(op)) { | |
63 | if (linux_regs->sr & SR_T_BIT_MASK) | |
64 | addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); | |
65 | else | |
66 | addr = linux_regs->pc + 4; /* Not in delay slot */ | |
67 | } | |
68 | ||
69 | /* BF */ | |
70 | else if (OPCODE_BF(op)) { | |
71 | if (!(linux_regs->sr & SR_T_BIT_MASK)) | |
72 | addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); | |
73 | else | |
74 | addr = linux_regs->pc + 2; | |
75 | } | |
76 | ||
77 | /* BFS */ | |
78 | else if (OPCODE_BFS(op)) { | |
79 | if (!(linux_regs->sr & SR_T_BIT_MASK)) | |
80 | addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); | |
81 | else | |
82 | addr = linux_regs->pc + 4; /* Not in delay slot */ | |
83 | } | |
84 | ||
85 | /* BRA */ | |
86 | else if (OPCODE_BRA(op)) | |
87 | addr = linux_regs->pc + 4 + OPCODE_BRA_DISP(op); | |
88 | ||
89 | /* BRAF */ | |
90 | else if (OPCODE_BRAF(op)) | |
91 | addr = linux_regs->pc + 4 | |
92 | + linux_regs->regs[OPCODE_BRAF_REG(op)]; | |
93 | ||
94 | /* BSR */ | |
95 | else if (OPCODE_BSR(op)) | |
96 | addr = linux_regs->pc + 4 + OPCODE_BSR_DISP(op); | |
97 | ||
98 | /* BSRF */ | |
99 | else if (OPCODE_BSRF(op)) | |
100 | addr = linux_regs->pc + 4 | |
101 | + linux_regs->regs[OPCODE_BSRF_REG(op)]; | |
102 | ||
103 | /* JMP */ | |
104 | else if (OPCODE_JMP(op)) | |
105 | addr = linux_regs->regs[OPCODE_JMP_REG(op)]; | |
106 | ||
107 | /* JSR */ | |
108 | else if (OPCODE_JSR(op)) | |
109 | addr = linux_regs->regs[OPCODE_JSR_REG(op)]; | |
110 | ||
111 | /* RTS */ | |
112 | else if (OPCODE_RTS(op)) | |
113 | addr = linux_regs->pr; | |
114 | ||
115 | /* RTE */ | |
116 | else if (OPCODE_RTE(op)) | |
117 | addr = linux_regs->regs[15]; | |
118 | ||
119 | /* Other */ | |
120 | else | |
121 | addr = linux_regs->pc + instruction_size(op); | |
122 | ||
123 | flush_icache_range(addr, addr + instruction_size(op)); | |
124 | return (short *)addr; | |
125 | } | |
126 | ||
127 | /* | |
128 | * Replace the instruction immediately after the current instruction | |
129 | * (i.e. next in the expected flow of control) with a trap instruction, | |
130 | * so that returning will cause only a single instruction to be executed. | |
131 | * Note that this model is slightly broken for instructions with delay | |
132 | * slots (e.g. B[TF]S, BSR, BRA etc), where both the branch and the | |
133 | * instruction in the delay slot will be executed. | |
134 | */ | |
135 | ||
136 | static unsigned long stepped_address; | |
137 | static opcode_t stepped_opcode; | |
138 | ||
139 | static void do_single_step(struct pt_regs *linux_regs) | |
140 | { | |
141 | /* Determine where the target instruction will send us to */ | |
142 | unsigned short *addr = get_step_address(linux_regs); | |
143 | ||
144 | stepped_address = (int)addr; | |
145 | ||
146 | /* Replace it */ | |
147 | stepped_opcode = __raw_readw((long)addr); | |
148 | *addr = STEP_OPCODE; | |
149 | ||
150 | /* Flush and return */ | |
151 | flush_icache_range((long)addr, (long)addr + | |
152 | instruction_size(stepped_opcode)); | |
153 | } | |
154 | ||
155 | /* Undo a single step */ | |
156 | static void undo_single_step(struct pt_regs *linux_regs) | |
157 | { | |
158 | /* If we have stepped, put back the old instruction */ | |
159 | /* Use stepped_address in case we stopped elsewhere */ | |
160 | if (stepped_opcode != 0) { | |
161 | __raw_writew(stepped_opcode, stepped_address); | |
162 | flush_icache_range(stepped_address, stepped_address + 2); | |
163 | } | |
164 | ||
165 | stepped_opcode = 0; | |
166 | } | |
167 | ||
168 | void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) | |
169 | { | |
170 | int i; | |
171 | ||
172 | for (i = 0; i < 16; i++) | |
173 | gdb_regs[GDB_R0 + i] = regs->regs[i]; | |
174 | ||
175 | gdb_regs[GDB_PC] = regs->pc; | |
176 | gdb_regs[GDB_PR] = regs->pr; | |
177 | gdb_regs[GDB_SR] = regs->sr; | |
178 | gdb_regs[GDB_GBR] = regs->gbr; | |
179 | gdb_regs[GDB_MACH] = regs->mach; | |
180 | gdb_regs[GDB_MACL] = regs->macl; | |
181 | ||
182 | __asm__ __volatile__ ("stc vbr, %0" : "=r" (gdb_regs[GDB_VBR])); | |
183 | } | |
184 | ||
185 | void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) | |
186 | { | |
187 | int i; | |
188 | ||
189 | for (i = 0; i < 16; i++) | |
190 | regs->regs[GDB_R0 + i] = gdb_regs[GDB_R0 + i]; | |
191 | ||
192 | regs->pc = gdb_regs[GDB_PC]; | |
193 | regs->pr = gdb_regs[GDB_PR]; | |
194 | regs->sr = gdb_regs[GDB_SR]; | |
195 | regs->gbr = gdb_regs[GDB_GBR]; | |
196 | regs->mach = gdb_regs[GDB_MACH]; | |
197 | regs->macl = gdb_regs[GDB_MACL]; | |
198 | ||
199 | __asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR])); | |
200 | } | |
201 | ||
202 | void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) | |
203 | { | |
204 | gdb_regs[GDB_R15] = p->thread.sp; | |
205 | gdb_regs[GDB_PC] = p->thread.pc; | |
206 | } | |
207 | ||
208 | int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, | |
209 | char *remcomInBuffer, char *remcomOutBuffer, | |
210 | struct pt_regs *linux_regs) | |
211 | { | |
212 | unsigned long addr; | |
213 | char *ptr; | |
214 | ||
215 | /* Undo any stepping we may have done */ | |
216 | undo_single_step(linux_regs); | |
217 | ||
218 | switch (remcomInBuffer[0]) { | |
219 | case 'c': | |
220 | case 's': | |
221 | /* try to read optional parameter, pc unchanged if no parm */ | |
222 | ptr = &remcomInBuffer[1]; | |
223 | if (kgdb_hex2long(&ptr, &addr)) | |
224 | linux_regs->pc = addr; | |
225 | case 'D': | |
226 | case 'k': | |
227 | atomic_set(&kgdb_cpu_doing_single_step, -1); | |
228 | ||
229 | if (remcomInBuffer[0] == 's') { | |
230 | do_single_step(linux_regs); | |
231 | kgdb_single_step = 1; | |
232 | ||
233 | atomic_set(&kgdb_cpu_doing_single_step, | |
234 | raw_smp_processor_id()); | |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | /* this means that we do not want to exit from the handler: */ | |
241 | return -1; | |
242 | } | |
243 | ||
244 | /* | |
245 | * The primary entry points for the kgdb debug trap table entries. | |
246 | */ | |
247 | BUILD_TRAP_HANDLER(singlestep) | |
248 | { | |
249 | unsigned long flags; | |
250 | TRAP_HANDLER_DECL; | |
251 | ||
252 | local_irq_save(flags); | |
253 | regs->pc -= instruction_size(__raw_readw(regs->pc - 4)); | |
254 | kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs); | |
255 | local_irq_restore(flags); | |
256 | } | |
257 | ||
258 | ||
259 | BUILD_TRAP_HANDLER(breakpoint) | |
260 | { | |
261 | unsigned long flags; | |
262 | TRAP_HANDLER_DECL; | |
263 | ||
264 | local_irq_save(flags); | |
265 | kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs); | |
266 | local_irq_restore(flags); | |
267 | } | |
268 | ||
269 | int kgdb_arch_init(void) | |
270 | { | |
271 | return 0; | |
272 | } | |
273 | ||
274 | void kgdb_arch_exit(void) | |
275 | { | |
276 | } | |
277 | ||
278 | struct kgdb_arch arch_kgdb_ops = { | |
279 | /* Breakpoint instruction: trapa #0x3c */ | |
280 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
281 | .gdb_bpt_instr = { 0x3c, 0xc3 }, | |
282 | #else | |
283 | .gdb_bpt_instr = { 0xc3, 0x3c }, | |
284 | #endif | |
285 | }; |