[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sh / kernel / cpu / sh2a / setup-sh7203.c

/*
 * SH7203 and SH7263 Setup
 *
 *  Copyright (C) 2007 - 2009  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <linux/io.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
	USB, LCDC, CMT0, CMT1, BSC, WDT,

	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
	MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,

	ADC_ADI,

	IIC30, IIC31, IIC32, IIC33,
	SCIF0, SCIF1, SCIF2, SCIF3,

	SSU0, SSU1,

	SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,

	/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
	ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
	SRC, IEBI,

	/* interrupt groups */
	PINT,
};

static struct intc_vect vectors[] __initdata = {
	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
	INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
	INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
	INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
	INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
	INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
	INTC_IRQ(MTU0_VEF, 150),
	INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
	INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
	INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
	INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
	INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
	INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
	INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
	INTC_IRQ(MTU2_TCI3V, 165),
	INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
	INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
	INTC_IRQ(MTU2_TCI4V, 170),
	INTC_IRQ(ADC_ADI, 171),
	INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
	INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
	INTC_IRQ(IIC30, 176),
	INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
	INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
	INTC_IRQ(IIC31, 181),
	INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
	INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
	INTC_IRQ(IIC32, 186),
	INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
	INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
	INTC_IRQ(IIC33, 191),
	INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
	INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
	INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
	INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
	INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
	INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
	INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
	INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
	INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
	INTC_IRQ(SSU0, 210),
	INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
	INTC_IRQ(SSU1, 213),
	INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
	INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
	INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
	INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
	INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
	INTC_IRQ(RTC, 233),
	INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
	INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
	INTC_IRQ(RCAN0, 238),
	INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
	INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
	INTC_IRQ(RCAN1, 243),

	/* SH7263-specific trash */
#ifdef CONFIG_CPU_SUBTYPE_SH7263
	INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
	INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
	INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),

	INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
	INTC_IRQ(SDHI, 230),

	INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
	INTC_IRQ(SRC, 246),

	INTC_IRQ(IEBI, 247),
#endif
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
		   PINT4, PINT5, PINT6, PINT7),
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
					      MTU2_VU } },
	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
					      MTU2_TCI4V } },
	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
#ifdef CONFIG_CPU_SUBTYPE_SH7203
	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
					      SSI3_SSII, 0 } },
	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
#else
	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
					      SSI3_SSII, ROMDEC } },
	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
#endif
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfffe0808, 0, 16, /* PINTER */
	  { 0, 0, 0, 0, 0, 0, 0, 0,
	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
			 mask_registers, prio_registers, NULL);

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xfffe8000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		=  { 192, 192, 192, 192 },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xfffe8800,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		=  { 196, 196, 196, 196 },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xfffe9000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		=  { 200, 200, 200, 200 },
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xfffe9800,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		=  { 204, 204, 204, 204 },
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct sh_timer_config cmt0_platform_data = {
	.channel_offset = 0x02,
	.timer_bit = 0,
	.clockevent_rating = 125,
	.clocksource_rating = 0, /* disabled due to code generation issues */
};

static struct resource cmt0_resources[] = {
	[0] = {
		.start	= 0xfffec002,
		.end	= 0xfffec007,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 142,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt0_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt0_platform_data,
	},
	.resource	= cmt0_resources,
	.num_resources	= ARRAY_SIZE(cmt0_resources),
};

static struct sh_timer_config cmt1_platform_data = {
	.channel_offset = 0x08,
	.timer_bit = 1,
	.clockevent_rating = 125,
	.clocksource_rating = 0, /* disabled due to code generation issues */
};

static struct resource cmt1_resources[] = {
	[0] = {
		.start	= 0xfffec008,
		.end	= 0xfffec00d,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 143,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt1_device = {
	.name		= "sh_cmt",
	.id		= 1,
	.dev = {
		.platform_data	= &cmt1_platform_data,
	},
	.resource	= cmt1_resources,
	.num_resources	= ARRAY_SIZE(cmt1_resources),
};

static struct sh_timer_config mtu2_0_platform_data = {
	.channel_offset = -0x80,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource mtu2_0_resources[] = {
	[0] = {
		.start	= 0xfffe4300,
		.end	= 0xfffe4326,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 146,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_0_device = {
	.name		= "sh_mtu2",
	.id		= 0,
	.dev = {
		.platform_data	= &mtu2_0_platform_data,
	},
	.resource	= mtu2_0_resources,
	.num_resources	= ARRAY_SIZE(mtu2_0_resources),
};

static struct sh_timer_config mtu2_1_platform_data = {
	.channel_offset = -0x100,
	.timer_bit = 1,
	.clockevent_rating = 200,
};

static struct resource mtu2_1_resources[] = {
	[0] = {
		.start	= 0xfffe4380,
		.end	= 0xfffe4390,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 153,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_1_device = {
	.name		= "sh_mtu2",
	.id		= 1,
	.dev = {
		.platform_data	= &mtu2_1_platform_data,
	},
	.resource	= mtu2_1_resources,
	.num_resources	= ARRAY_SIZE(mtu2_1_resources),
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xffff2000,
		.end	= 0xffff2000 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Shared Period/Carry/Alarm IRQ */
		.start	= 231,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct platform_device *sh7203_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt0_device,
	&cmt1_device,
	&mtu2_0_device,
	&mtu2_1_device,
	&rtc_device,
};

static int __init sh7203_devices_setup(void)
{
	return platform_add_devices(sh7203_devices,
				    ARRAY_SIZE(sh7203_devices));
}
arch_initcall(sh7203_devices_setup);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

static struct platform_device *sh7203_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt0_device,
	&cmt1_device,
	&mtu2_0_device,
	&mtu2_1_device,
};

#define STBCR3 0xfffe0408
#define STBCR4 0xfffe040c

void __init plat_early_device_setup(void)
{
	/* enable CMT clock */
	__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);

	/* enable MTU2 clock */
	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

	early_platform_add_devices(sh7203_early_devices,
				   ARRAY_SIZE(sh7203_early_devices));
}
Commit	Line	Data
6d01f510	1	/*
a8f67f4b	2	* SH7203 and SH7263 Setup
6d01f510	3	*
bb943a28	4	* Copyright (C) 2007 - 2009 Paul Mundt
6d01f510 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
46a12f74	14	#include <linux/sh_timer.h>
698aa99d	15	#include <linux/io.h>
6d01f510 PM	16
	17	enum {
	18	UNUSED = 0,
	19
	20	/* interrupt sources */
	21	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	22	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
bb943a28	23	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
6d01f510	24	USB, LCDC, CMT0, CMT1, BSC, WDT,
bb943a28 PM	25
	26	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
	27	MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
	28
6d01f510	29	ADC_ADI,
bb943a28 PM	30
	31	IIC30, IIC31, IIC32, IIC33,
	32	SCIF0, SCIF1, SCIF2, SCIF3,
	33
	34	SSU0, SSU1,
	35
6d01f510	36	SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
a8f67f4b PM	37
a8f67f4b PM	38	/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
e45efe68 PM	39	ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
e45efe68 PM	40	SRC, IEBI,
a8f67f4b	41
6d01f510	42	/* interrupt groups */
e45efe68	43	PINT,
6d01f510 PM	44	};
	45
	46	static struct intc_vect vectors[] __initdata = {
	47	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	48	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	49	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	50	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
	51	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	52	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	53	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	54	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
bb943a28 PM	55	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
	56	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
	57	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
	58	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
	59	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
	60	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
	61	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
	62	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
6d01f510 PM	63	INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
	64	INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
	65	INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
bb943a28 PM	66	INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
	67	INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
	68	INTC_IRQ(MTU0_VEF, 150),
	69	INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
	70	INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
	71	INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
	72	INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
	73	INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
	74	INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
	75	INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
6d01f510	76	INTC_IRQ(MTU2_TCI3V, 165),
bb943a28 PM	77	INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
bb943a28 PM	78	INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
6d01f510 PM	79	INTC_IRQ(MTU2_TCI4V, 170),
6d01f510 PM	80	INTC_IRQ(ADC_ADI, 171),
bb943a28 PM	81	INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
	82	INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
	83	INTC_IRQ(IIC30, 176),
	84	INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
	85	INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
	86	INTC_IRQ(IIC31, 181),
	87	INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
	88	INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
	89	INTC_IRQ(IIC32, 186),
	90	INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
	91	INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
	92	INTC_IRQ(IIC33, 191),
	93	INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
	94	INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
	95	INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
	96	INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
	97	INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
	98	INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
	99	INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
	100	INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
	101	INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
	102	INTC_IRQ(SSU0, 210),
	103	INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
	104	INTC_IRQ(SSU1, 213),
6d01f510 PM	105	INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
6d01f510 PM	106	INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
bb943a28 PM	107	INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
	108	INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
	109	INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
	110	INTC_IRQ(RTC, 233),
	111	INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
	112	INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
	113	INTC_IRQ(RCAN0, 238),
	114	INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
	115	INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
	116	INTC_IRQ(RCAN1, 243),
a8f67f4b PM	117
	118	/* SH7263-specific trash */
	119	#ifdef CONFIG_CPU_SUBTYPE_SH7263
e45efe68 PM	120	INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
	121	INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
	122	INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
a8f67f4b	123
e45efe68 PM	124	INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
e45efe68 PM	125	INTC_IRQ(SDHI, 230),
a8f67f4b	126
e45efe68 PM	127	INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
e45efe68 PM	128	INTC_IRQ(SRC, 246),
a8f67f4b PM	129
	130	INTC_IRQ(IEBI, 247),
	131	#endif
6d01f510 PM	132	};
	133
	134	static struct intc_group groups[] __initdata = {
	135	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
	136	PINT4, PINT5, PINT6, PINT7),
6d01f510 PM	137	};
	138
	139	static struct intc_prio_reg prio_registers[] __initdata = {
	140	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	141	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	142	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
	143	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
	144	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
	145	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
	146	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
	147	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
	148	MTU2_VU } },
	149	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
	150	MTU2_TCI4V } },
	151	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
	152	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
	153	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
a8f67f4b	154	#ifdef CONFIG_CPU_SUBTYPE_SH7203
6d01f510 PM	155	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
	156	SSI3_SSII, 0 } },
	157	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
	158	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
a8f67f4b PM	159	#else
	160	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
	161	SSI3_SSII, ROMDEC } },
	162	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
	163	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
	164	#endif
6d01f510 PM	165	};
	166
	167	static struct intc_mask_reg mask_registers[] __initdata = {
	168	{ 0xfffe0808, 0, 16, /* PINTER */
	169	{ 0, 0, 0, 0, 0, 0, 0, 0,
	170	PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
	171	};
	172
	173	static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
7f3edee8	174	mask_registers, prio_registers, NULL);
6d01f510	175
be091d20 MD	176	static struct plat_sci_port scif0_platform_data = {
	177	.mapbase = 0xfffe8000,
	178	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	179	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_REIE,
f43dc23d PM	180	.scbrr_algo_id = SCBRR_ALGO_2,
be091d20 MD	181	.type = PORT_SCIF,
be091d20 MD	182	.irqs = { 192, 192, 192, 192 },
6d01f510 PM	183	};
6d01f510 PM	184
be091d20	185	static struct platform_device scif0_device = {
6d01f510	186	.name = "sh-sci",
be091d20 MD	187	.id = 0,
	188	.dev = {
	189	.platform_data = &scif0_platform_data,
	190	},
	191	};
	192
	193	static struct plat_sci_port scif1_platform_data = {
	194	.mapbase = 0xfffe8800,
	195	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	196	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_REIE,
f43dc23d PM	197	.scbrr_algo_id = SCBRR_ALGO_2,
be091d20 MD	198	.type = PORT_SCIF,
	199	.irqs = { 196, 196, 196, 196 },
	200	};
	201
	202	static struct platform_device scif1_device = {
	203	.name = "sh-sci",
	204	.id = 1,
	205	.dev = {
	206	.platform_data = &scif1_platform_data,
	207	},
	208	};
	209
	210	static struct plat_sci_port scif2_platform_data = {
	211	.mapbase = 0xfffe9000,
	212	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	213	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_REIE,
f43dc23d PM	214	.scbrr_algo_id = SCBRR_ALGO_2,
be091d20 MD	215	.type = PORT_SCIF,
	216	.irqs = { 200, 200, 200, 200 },
	217	};
	218
	219	static struct platform_device scif2_device = {
	220	.name = "sh-sci",
	221	.id = 2,
	222	.dev = {
	223	.platform_data = &scif2_platform_data,
	224	},
	225	};
	226
	227	static struct plat_sci_port scif3_platform_data = {
	228	.mapbase = 0xfffe9800,
	229	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	230	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_REIE,
f43dc23d PM	231	.scbrr_algo_id = SCBRR_ALGO_2,
be091d20 MD	232	.type = PORT_SCIF,
	233	.irqs = { 204, 204, 204, 204 },
	234	};
	235
	236	static struct platform_device scif3_device = {
	237	.name = "sh-sci",
	238	.id = 3,
6d01f510	239	.dev = {
be091d20	240	.platform_data = &scif3_platform_data,
6d01f510 PM	241	},
	242	};
	243
46a12f74	244	static struct sh_timer_config cmt0_platform_data = {
698aa99d MD	245	.channel_offset = 0x02,
698aa99d MD	246	.timer_bit = 0,
698aa99d MD	247	.clockevent_rating = 125,
	248	.clocksource_rating = 0, /* disabled due to code generation issues */
	249	};
	250
	251	static struct resource cmt0_resources[] = {
	252	[0] = {
698aa99d MD	253	.start = 0xfffec002,
	254	.end = 0xfffec007,
	255	.flags = IORESOURCE_MEM,
	256	},
	257	[1] = {
	258	.start = 142,
	259	.flags = IORESOURCE_IRQ,
	260	},
	261	};
	262
	263	static struct platform_device cmt0_device = {
	264	.name = "sh_cmt",
	265	.id = 0,
	266	.dev = {
	267	.platform_data = &cmt0_platform_data,
	268	},
	269	.resource = cmt0_resources,
	270	.num_resources = ARRAY_SIZE(cmt0_resources),
	271	};
	272
46a12f74	273	static struct sh_timer_config cmt1_platform_data = {
698aa99d MD	274	.channel_offset = 0x08,
698aa99d MD	275	.timer_bit = 1,
698aa99d MD	276	.clockevent_rating = 125,
	277	.clocksource_rating = 0, /* disabled due to code generation issues */
	278	};
	279
	280	static struct resource cmt1_resources[] = {
	281	[0] = {
698aa99d MD	282	.start = 0xfffec008,
	283	.end = 0xfffec00d,
	284	.flags = IORESOURCE_MEM,
	285	},
	286	[1] = {
	287	.start = 143,
	288	.flags = IORESOURCE_IRQ,
	289	},
	290	};
	291
	292	static struct platform_device cmt1_device = {
	293	.name = "sh_cmt",
	294	.id = 1,
	295	.dev = {
	296	.platform_data = &cmt1_platform_data,
	297	},
	298	.resource = cmt1_resources,
	299	.num_resources = ARRAY_SIZE(cmt1_resources),
	300	};
	301
46a12f74	302	static struct sh_timer_config mtu2_0_platform_data = {
da107c6e MD	303	.channel_offset = -0x80,
da107c6e MD	304	.timer_bit = 0,
da107c6e MD	305	.clockevent_rating = 200,
	306	};
	307
	308	static struct resource mtu2_0_resources[] = {
	309	[0] = {
da107c6e MD	310	.start = 0xfffe4300,
	311	.end = 0xfffe4326,
	312	.flags = IORESOURCE_MEM,
	313	},
	314	[1] = {
	315	.start = 146,
	316	.flags = IORESOURCE_IRQ,
	317	},
	318	};
	319
	320	static struct platform_device mtu2_0_device = {
	321	.name = "sh_mtu2",
	322	.id = 0,
	323	.dev = {
	324	.platform_data = &mtu2_0_platform_data,
	325	},
	326	.resource = mtu2_0_resources,
	327	.num_resources = ARRAY_SIZE(mtu2_0_resources),
	328	};
	329
46a12f74	330	static struct sh_timer_config mtu2_1_platform_data = {
da107c6e MD	331	.channel_offset = -0x100,
da107c6e MD	332	.timer_bit = 1,
da107c6e MD	333	.clockevent_rating = 200,
	334	};
	335
	336	static struct resource mtu2_1_resources[] = {
	337	[0] = {
da107c6e MD	338	.start = 0xfffe4380,
	339	.end = 0xfffe4390,
	340	.flags = IORESOURCE_MEM,
	341	},
	342	[1] = {
	343	.start = 153,
	344	.flags = IORESOURCE_IRQ,
	345	},
	346	};
	347
	348	static struct platform_device mtu2_1_device = {
	349	.name = "sh_mtu2",
	350	.id = 1,
	351	.dev = {
	352	.platform_data = &mtu2_1_platform_data,
	353	},
	354	.resource = mtu2_1_resources,
	355	.num_resources = ARRAY_SIZE(mtu2_1_resources),
	356	};
	357
6d01f510 PM	358	static struct resource rtc_resources[] = {
	359	[0] = {
	360	.start = 0xffff2000,
	361	.end = 0xffff2000 + 0x58 - 1,
	362	.flags = IORESOURCE_IO,
	363	},
	364	[1] = {
bb943a28	365	/* Shared Period/Carry/Alarm IRQ */
6d01f510 PM	366	.start = 231,
	367	.flags = IORESOURCE_IRQ,
	368	},
	369	};
	370
	371	static struct platform_device rtc_device = {
	372	.name = "sh-rtc",
	373	.id = -1,
	374	.num_resources = ARRAY_SIZE(rtc_resources),
	375	.resource = rtc_resources,
	376	};
	377
	378	static struct platform_device *sh7203_devices[] __initdata = {
be091d20 MD	379	&scif0_device,
	380	&scif1_device,
	381	&scif2_device,
	382	&scif3_device,
698aa99d MD	383	&cmt0_device,
698aa99d MD	384	&cmt1_device,
da107c6e MD	385	&mtu2_0_device,
da107c6e MD	386	&mtu2_1_device,
6d01f510 PM	387	&rtc_device,
	388	};
	389
	390	static int __init sh7203_devices_setup(void)
	391	{
	392	return platform_add_devices(sh7203_devices,
	393	ARRAY_SIZE(sh7203_devices));
	394	}
ba9a6337	395	arch_initcall(sh7203_devices_setup);
6d01f510 PM	396
	397	void __init plat_irq_setup(void)
	398	{
	399	register_intc_controller(&intc_desc);
	400	}
698aa99d MD	401
698aa99d MD	402	static struct platform_device *sh7203_early_devices[] __initdata = {
be091d20 MD	403	&scif0_device,
	404	&scif1_device,
	405	&scif2_device,
	406	&scif3_device,
698aa99d MD	407	&cmt0_device,
698aa99d MD	408	&cmt1_device,
da107c6e MD	409	&mtu2_0_device,
da107c6e MD	410	&mtu2_1_device,
698aa99d MD	411	};
698aa99d MD	412
da107c6e	413	#define STBCR3 0xfffe0408
698aa99d MD	414	#define STBCR4 0xfffe040c
	415
	416	void __init plat_early_device_setup(void)
	417	{
	418	/* enable CMT clock */
	419	__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
	420
da107c6e MD	421	/* enable MTU2 clock */
	422	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
	423
698aa99d MD	424	early_platform_add_devices(sh7203_early_devices,
	425	ARRAY_SIZE(sh7203_early_devices));
	426	}