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5283ecb5 PM |
1 | /* |
2 | * Low-Level PCI Support for the SH7780 | |
3 | * | |
4 | * Dustin McIntire (dustin@sensoria.com) | |
5 | * Derived from arch/i386/kernel/pci-*.c which bore the message: | |
6 | * (c) 1999--2000 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * Ported to the new API by Paul Mundt <lethal@linux-sh.org> | |
9 | * With cleanup by Paul van Gool <pvangool@mimotech.com> | |
10 | * | |
11 | * May be copied or modified under the terms of the GNU General Public | |
12 | * License. See linux/COPYING for more information. | |
13 | * | |
14 | */ | |
5283ecb5 PM |
15 | #undef DEBUG |
16 | ||
5283ecb5 PM |
17 | #include <linux/types.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/pci.h> | |
5283ecb5 | 21 | #include <linux/errno.h> |
5283ecb5 | 22 | #include <linux/delay.h> |
959f85f8 | 23 | #include "pci-sh4.h" |
5283ecb5 PM |
24 | |
25 | /* | |
959f85f8 PM |
26 | * Initialization. Try all known PCI access methods. Note that we support |
27 | * using both PCI BIOS and direct access: in such cases, we use I/O ports | |
28 | * to access config space. | |
29 | * | |
30 | * Note that the platform specific initialization (BSC registers, and memory | |
31 | * space mapping) will be called via the platform defined function | |
32 | * pcibios_init_platform(). | |
5283ecb5 | 33 | */ |
959f85f8 | 34 | static int __init sh7780_pci_init(void) |
5283ecb5 | 35 | { |
959f85f8 PM |
36 | unsigned int id; |
37 | int ret; | |
5283ecb5 | 38 | |
959f85f8 | 39 | pr_debug("PCI: Starting intialization.\n"); |
5283ecb5 PM |
40 | |
41 | outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ | |
42 | ||
43 | /* check for SH7780/SH7780R hardware */ | |
959f85f8 | 44 | id = pci_read_reg(SH7780_PCIVID); |
5283ecb5 PM |
45 | if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) && |
46 | (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) { | |
47 | printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); | |
48 | return -ENODEV; | |
49 | } | |
50 | ||
5283ecb5 PM |
51 | /* Setup the INTC */ |
52 | ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */ | |
53 | ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */ | |
54 | ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */ | |
55 | ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */ | |
56 | ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */ | |
57 | ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */ | |
58 | ||
959f85f8 | 59 | if ((ret = sh4_pci_check_direct()) != 0) |
5283ecb5 PM |
60 | return ret; |
61 | ||
62 | return pcibios_init_platform(); | |
63 | } | |
5283ecb5 PM |
64 | core_initcall(sh7780_pci_init); |
65 | ||
959f85f8 | 66 | int __init sh7780_pcic_init(struct sh4_pci_address_map *map) |
5283ecb5 PM |
67 | { |
68 | u32 word; | |
69 | ||
70 | /* | |
71 | * This code is unused for some boards as it is done in the | |
72 | * bootloader and doing it here means the MAC addresses loaded | |
73 | * by the bootloader get lost. | |
74 | */ | |
959f85f8 | 75 | if (!(map->flags & SH4_PCIC_NO_RESET)) { |
5283ecb5 | 76 | /* toggle PCI reset pin */ |
959f85f8 PM |
77 | word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; |
78 | pci_write_reg(word, SH4_PCICR); | |
5283ecb5 PM |
79 | /* Wait for a long time... not 1 sec. but long enough */ |
80 | mdelay(100); | |
959f85f8 PM |
81 | word = SH4_PCICR_PREFIX; |
82 | pci_write_reg(word, SH4_PCICR); | |
5283ecb5 PM |
83 | } |
84 | ||
85 | /* set the command/status bits to: | |
86 | * Wait Cycle Control + Parity Enable + Bus Master + | |
87 | * Mem space enable | |
88 | */ | |
959f85f8 | 89 | pci_write_reg(0x00000046, SH7780_PCICMD); |
5283ecb5 PM |
90 | |
91 | /* define this host as the host bridge */ | |
959f85f8 PM |
92 | word = PCI_BASE_CLASS_BRIDGE << 24; |
93 | pci_write_reg(word, SH7780_PCIRID); | |
5283ecb5 PM |
94 | |
95 | /* Set IO and Mem windows to local address | |
96 | * Make PCI and local address the same for easy 1 to 1 mapping | |
97 | * Window0 = map->window0.size @ non-cached area base = SDRAM | |
98 | * Window1 = map->window1.size @ cached area base = SDRAM | |
99 | */ | |
100 | word = ((map->window0.size - 1) & 0x1ff00001) | 0x01; | |
959f85f8 | 101 | pci_write_reg(0x07f00001, SH4_PCILSR0); |
5283ecb5 | 102 | word = ((map->window1.size - 1) & 0x1ff00001) | 0x01; |
959f85f8 | 103 | pci_write_reg(0x00000001, SH4_PCILSR1); |
5283ecb5 PM |
104 | /* Set the values on window 0 PCI config registers */ |
105 | word = P2SEGADDR(map->window0.base); | |
959f85f8 PM |
106 | pci_write_reg(0xa8000000, SH4_PCILAR0); |
107 | pci_write_reg(0x08000000, SH7780_PCIMBAR0); | |
5283ecb5 PM |
108 | /* Set the values on window 1 PCI config registers */ |
109 | word = P2SEGADDR(map->window1.base); | |
959f85f8 PM |
110 | pci_write_reg(0x00000000, SH4_PCILAR1); |
111 | pci_write_reg(0x00000000, SH7780_PCIMBAR1); | |
5283ecb5 PM |
112 | |
113 | /* Map IO space into PCI IO window | |
114 | * The IO window is 64K-PCIBIOS_MIN_IO in size | |
115 | * IO addresses will be translated to the | |
116 | * PCI IO window base address | |
117 | */ | |
959f85f8 PM |
118 | pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", |
119 | PCIBIOS_MIN_IO, (64 << 10), | |
120 | SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO); | |
5283ecb5 PM |
121 | |
122 | /* NOTE: I'm ignoring the PCI error IRQs for now.. | |
123 | * TODO: add support for the internal error interrupts and | |
124 | * DMA interrupts... | |
125 | */ | |
126 | ||
127 | #ifdef CONFIG_SH_R7780RP | |
128 | pci_fixup_pcic(); | |
129 | #endif | |
130 | ||
131 | /* SH7780 init done, set central function init complete */ | |
132 | /* use round robin mode to stop a device starving/overruning */ | |
959f85f8 PM |
133 | word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; |
134 | pci_write_reg(word, SH4_PCICR); | |
5283ecb5 PM |
135 | |
136 | return 1; | |
137 | } |