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fbdev: sh_mobile_lcdc: Rename (lcd|num)_cfg (lcd|num)_modes
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / sh / boards / mach-se / 7724 / setup.c
CommitLineData
287c1297
KM		 1/*
2 * linux/arch/sh/boards/se/7724/setup.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
a68a0784 17#include <linux/mmc/host.h>
960b9e7e 18#include <linux/mmc/sh_mobile_sdhi.h>
287c1297
KM		 19#include <linux/mtd/physmap.h>
20#include <linux/delay.h>
21#include <linux/smc91x.h>
22#include <linux/gpio.h>
23#include <linux/input.h>
fc1d003d 24#include <linux/input/sh_keysc.h>
9731f4a2 25#include <linux/usb/r8a66597.h>
cf8e56bf 26#include <linux/sh_eth.h>
a1ad8033 27#include <linux/videodev2.h>
287c1297
KM		 28#include <video/sh_mobile_lcdc.h>
29#include <media/sh_mobile_ceu.h>
3e9ad52b 30#include <sound/sh_fsi.h>
287c1297
KM		 31#include <asm/io.h>
32#include <asm/heartbeat.h>
a80cad95 33#include <asm/clock.h>
3b9f2952 34#include <asm/suspend.h>
287c1297
KM		 35#include <cpu/sh7724.h>
36#include <mach-se/mach/se7724.h>
37
38/*
39 * SWx 1234 5678
40 * ------------------------------------
41 * SW31 : 1001 1100 : default
42 * SW32 : 0111 1111 : use on board flash
43 *
44 * SW41 : abxx xxxx -> a = 0 : Analog monitor
45 * 1 : Digital monitor
46 * b = 0 : VGA
4f324311
KM		 47 * 1 : 720p
48 */
49
50/*
51 * about 720p
52 *
53 * When you use 1280 x 720 lcdc output,
54 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
55 * and change SW41 to use 720p
287c1297
KM		 56 */
57
bec9fb07
KM		 58/*
59 * about sound
60 *
61 * This setup.c supports FSI slave mode.
62 * Please change J20, J21, J22 pin to 1-2 connection.
63 */
64
287c1297 65/* Heartbeat */
a09d2831
PM		 66static struct resource heartbeat_resource = {
67 .start = PA_LED,
68 .end = PA_LED,
69 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
287c1297
KM		 70};
71
72static struct platform_device heartbeat_device = {
73 .name = "heartbeat",
74 .id = -1,
a09d2831
PM		 75 .num_resources = 1,
76 .resource = &heartbeat_resource,
287c1297
KM		 77};
78
79/* LAN91C111 */
80static struct smc91x_platdata smc91x_info = {
81 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
82};
83
84static struct resource smc91x_eth_resources[] = {
85 [0] = {
86 .name = "SMC91C111" ,
87 .start = 0x1a300300,
88 .end = 0x1a30030f,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = IRQ0_SMC,
93 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
94 },
95};
96
97static struct platform_device smc91x_eth_device = {
98 .name = "smc91x",
99 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
100 .resource = smc91x_eth_resources,
101 .dev = {
102 .platform_data = &smc91x_info,
103 },
104};
105
106/* MTD */
107static struct mtd_partition nor_flash_partitions[] = {
108 {
109 .name = "uboot",
110 .offset = 0,
111 .size = (1 * 1024 * 1024),
112 .mask_flags = MTD_WRITEABLE, /* Read-only */
113 }, {
114 .name = "kernel",
115 .offset = MTDPART_OFS_APPEND,
116 .size = (2 * 1024 * 1024),
117 }, {
118 .name = "free-area",
119 .offset = MTDPART_OFS_APPEND,
120 .size = MTDPART_SIZ_FULL,
121 },
122};
123
124static struct physmap_flash_data nor_flash_data = {
125 .width = 2,
126 .parts = nor_flash_partitions,
127 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
128};
129
130static struct resource nor_flash_resources[] = {
131 [0] = {
132 .name = "NOR Flash",
133 .start = 0x00000000,
134 .end = 0x01ffffff,
135 .flags = IORESOURCE_MEM,
136 }
137};
138
139static struct platform_device nor_flash_device = {
140 .name = "physmap-flash",
141 .resource = nor_flash_resources,
142 .num_resources = ARRAY_SIZE(nor_flash_resources),
143 .dev = {
144 .platform_data = &nor_flash_data,
145 },
146};
147
148/* LCDC */
e04008eb 149static const struct fb_videomode lcdc_720p_modes[] = {
44432407
GL		 150 {
151 .name = "LB070WV1",
152 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 153 .xres = 1280,
154 .yres = 720,
155 .left_margin = 220,
156 .right_margin = 110,
157 .hsync_len = 40,
158 .upper_margin = 20,
159 .lower_margin = 5,
160 .vsync_len = 5,
44432407
GL		 161 },
162};
163
e04008eb 164static const struct fb_videomode lcdc_vga_modes[] = {
44432407
GL		 165 {
166 .name = "LB070WV1",
167 .sync = 0, /* hsync and vsync are active low */
46f12936
GL		 168 .xres = 640,
169 .yres = 480,
170 .left_margin = 105,
171 .right_margin = 50,
172 .hsync_len = 96,
173 .upper_margin = 33,
174 .lower_margin = 10,
175 .vsync_len = 2,
44432407
GL		 176 },
177};
178
287c1297
KM		 179static struct sh_mobile_lcdc_info lcdc_info = {
180 .clock_source = LCDC_CLK_EXTERNAL,
181 .ch[0] = {
182 .chan = LCDC_CHAN_MAINLCD,
edd153a3 183 .fourcc = V4L2_PIX_FMT_RGB565,
287c1297 184 .clock_divider = 1,
afaad83b 185 .panel_cfg = { /* 7.0 inch */
287c1297
KM		 186 .width = 152,
187 .height = 91,
188 },
287c1297
KM		 189 }
190};
191
192static struct resource lcdc_resources[] = {
193 [0] = {
194 .name = "LCDC",
195 .start = 0xfe940000,
a6f15ade 196 .end = 0xfe942fff,
287c1297
KM		 197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = 106,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204
205static struct platform_device lcdc_device = {
206 .name = "sh_mobile_lcdc_fb",
207 .num_resources = ARRAY_SIZE(lcdc_resources),
208 .resource = lcdc_resources,
209 .dev = {
210 .platform_data = &lcdc_info,
211 },
212};
213
214/* CEU0 */
215static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
216 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
217};
218
219static struct resource ceu0_resources[] = {
220 [0] = {
221 .name = "CEU0",
222 .start = 0xfe910000,
223 .end = 0xfe91009f,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = 52,
228 .flags = IORESOURCE_IRQ,
229 },
230 [2] = {
231 /* place holder for contiguous memory */
232 },
233};
234
235static struct platform_device ceu0_device = {
236 .name = "sh_mobile_ceu",
237 .id = 0, /* "ceu0" clock */
238 .num_resources = ARRAY_SIZE(ceu0_resources),
239 .resource = ceu0_resources,
240 .dev = {
241 .platform_data = &sh_mobile_ceu0_info,
242 },
243};
244
245/* CEU1 */
246static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
247 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
248};
249
250static struct resource ceu1_resources[] = {
251 [0] = {
252 .name = "CEU1",
253 .start = 0xfe914000,
254 .end = 0xfe91409f,
255 .flags = IORESOURCE_MEM,
256 },
257 [1] = {
258 .start = 63,
259 .flags = IORESOURCE_IRQ,
260 },
261 [2] = {
262 /* place holder for contiguous memory */
263 },
264};
265
266static struct platform_device ceu1_device = {
267 .name = "sh_mobile_ceu",
268 .id = 1, /* "ceu1" clock */
269 .num_resources = ARRAY_SIZE(ceu1_resources),
270 .resource = ceu1_resources,
271 .dev = {
272 .platform_data = &sh_mobile_ceu1_info,
273 },
274};
275
3e9ad52b 276/* FSI */
bec9fb07 277/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
560526f1 278static struct sh_fsi_platform_info fsi_info = {
f17c13ca 279 .porta_flags = SH_FSI_BRS_INV,
3e9ad52b
KM		 280};
281
282static struct resource fsi_resources[] = {
283 [0] = {
284 .name = "FSI",
285 .start = 0xFE3C0000,
286 .end = 0xFE3C021d,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = 108,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device fsi_device = {
296 .name = "sh_fsi",
297 .id = 0,
298 .num_resources = ARRAY_SIZE(fsi_resources),
299 .resource = fsi_resources,
300 .dev = {
301 .platform_data = &fsi_info,
302 },
303};
304
45f31216
KM		 305static struct fsi_ak4642_info fsi_ak4642_info = {
306 .name = "AK4642",
307 .card = "FSIA-AK4642",
308 .cpu_dai = "fsia-dai",
309 .codec = "ak4642-codec.0-0012",
310 .platform = "sh_fsi.0",
311 .id = FSI_PORT_A,
312};
313
c8d6bf9a 314static struct platform_device fsi_ak4642_device = {
45f31216
KM		 315 .name = "fsi-ak4642-audio",
316 .dev = {
317 .platform_data = &fsi_ak4642_info,
318 },
c8d6bf9a
KM		 319};
320
9747e78b 321/* KEYSC in SoC (Needs SW33-2 set to ON) */
287c1297
KM		 322static struct sh_keysc_info keysc_info = {
323 .mode = SH_KEYSC_MODE_1,
29463c28 324 .scan_timing = 3,
287c1297
KM		 325 .delay = 50,
326 .keycodes = {
327 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
328 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
329 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
330 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
331 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
332 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
333 },
334};
335
336static struct resource keysc_resources[] = {
337 [0] = {
9747e78b
MD		 338 .name = "KEYSC",
339 .start = 0x044b0000,
340 .end = 0x044b000f,
287c1297
KM		 341 .flags = IORESOURCE_MEM,
342 },
343 [1] = {
9747e78b 344 .start = 79,
287c1297
KM		 345 .flags = IORESOURCE_IRQ,
346 },
347};
348
349static struct platform_device keysc_device = {
350 .name = "sh_keysc",
351 .id = 0, /* "keysc0" clock */
352 .num_resources = ARRAY_SIZE(keysc_resources),
353 .resource = keysc_resources,
354 .dev = {
355 .platform_data = &keysc_info,
356 },
357};
358
a80cad95
KM		 359/* SH Eth */
360static struct resource sh_eth_resources[] = {
361 [0] = {
362 .start = SH_ETH_ADDR,
363 .end = SH_ETH_ADDR + 0x1FC,
364 .flags = IORESOURCE_MEM,
365 },
366 [1] = {
367 .start = 91,
368 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
369 },
370};
371
560526f1 372static struct sh_eth_plat_data sh_eth_plat = {
a80cad95
KM		 373 .phy = 0x1f, /* SMSC LAN8187 */
374 .edmac_endian = EDMAC_LITTLE_ENDIAN,
375};
376
377static struct platform_device sh_eth_device = {
378 .name = "sh-eth",
379 .id = 0,
380 .dev = {
381 .platform_data = &sh_eth_plat,
382 },
383 .num_resources = ARRAY_SIZE(sh_eth_resources),
384 .resource = sh_eth_resources,
385};
386
9731f4a2 387static struct r8a66597_platdata sh7724_usb0_host_data = {
719a72b7 388 .on_chip = 1,
9731f4a2
MD		 389};
390
391static struct resource sh7724_usb0_host_resources[] = {
392 [0] = {
393 .start = 0xa4d80000,
1bc265d0 394 .end = 0xa4d80124 - 1,
9731f4a2
MD		 395 .flags = IORESOURCE_MEM,
396 },
397 [1] = {
398 .start = 65,
399 .end = 65,
400 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
401 },
402};
403
404static struct platform_device sh7724_usb0_host_device = {
405 .name = "r8a66597_hcd",
406 .id = 0,
407 .dev = {
408 .dma_mask = NULL, /* not use dma */
409 .coherent_dma_mask = 0xffffffff,
410 .platform_data = &sh7724_usb0_host_data,
411 },
412 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
413 .resource = sh7724_usb0_host_resources,
414};
415
f8f8c079
MD		 416static struct r8a66597_platdata sh7724_usb1_gadget_data = {
417 .on_chip = 1,
418};
419
420static struct resource sh7724_usb1_gadget_resources[] = {
421 [0] = {
422 .start = 0xa4d90000,
423 .end = 0xa4d90123,
424 .flags = IORESOURCE_MEM,
425 },
426 [1] = {
427 .start = 66,
428 .end = 66,
429 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
430 },
431};
432
433static struct platform_device sh7724_usb1_gadget_device = {
434 .name = "r8a66597_udc",
435 .id = 1, /* USB1 */
436 .dev = {
437 .dma_mask = NULL, /* not use dma */
438 .coherent_dma_mask = 0xffffffff,
439 .platform_data = &sh7724_usb1_gadget_data,
440 },
441 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
442 .resource = sh7724_usb1_gadget_resources,
443};
444
0f79af60
MD		 445static struct resource sdhi0_cn7_resources[] = {
446 [0] = {
447 .name = "SDHI0",
448 .start = 0x04ce0000,
d80e9221 449 .end = 0x04ce00ff,
0f79af60
MD		 450 .flags = IORESOURCE_MEM,
451 },
452 [1] = {
3844eadc 453 .start = 100,
0f79af60
MD		 454 .flags = IORESOURCE_IRQ,
455 },
456};
457
470ef1a7
GL		 458static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
459 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
460 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
a68a0784 461 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 462};
463
0f79af60
MD		 464static struct platform_device sdhi0_cn7_device = {
465 .name = "sh_mobile_sdhi",
5b380ec1 466 .id = 0,
0f79af60
MD		 467 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
468 .resource = sdhi0_cn7_resources,
470ef1a7
GL		 469 .dev = {
470 .platform_data = &sh7724_sdhi0_data,
471 },
0f79af60
MD		 472};
473
5b380ec1
MD		 474static struct resource sdhi1_cn8_resources[] = {
475 [0] = {
476 .name = "SDHI1",
477 .start = 0x04cf0000,
d80e9221 478 .end = 0x04cf00ff,
5b380ec1
MD		 479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
3844eadc 482 .start = 23,
5b380ec1
MD		 483 .flags = IORESOURCE_IRQ,
484 },
485};
486
470ef1a7
GL		 487static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
488 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
489 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
a68a0784 490 .tmio_caps = MMC_CAP_SDIO_IRQ,
470ef1a7
GL		 491};
492
5b380ec1
MD		 493static struct platform_device sdhi1_cn8_device = {
494 .name = "sh_mobile_sdhi",
495 .id = 1,
496 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
497 .resource = sdhi1_cn8_resources,
470ef1a7
GL		 498 .dev = {
499 .platform_data = &sh7724_sdhi1_data,
500 },
5b380ec1
MD		 501};
502
bbb892aa
KM		 503/* IrDA */
504static struct resource irda_resources[] = {
505 [0] = {
506 .name = "IrDA",
507 .start = 0xA45D0000,
508 .end = 0xA45D0049,
509 .flags = IORESOURCE_MEM,
510 },
511 [1] = {
512 .start = 20,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device irda_device = {
518 .name = "sh_sir",
519 .num_resources = ARRAY_SIZE(irda_resources),
520 .resource = irda_resources,
521};
522
2d151248
GL		 523#include <media/ak881x.h>
524#include <media/sh_vou.h>
525
560526f1 526static struct ak881x_pdata ak881x_pdata = {
2d151248
GL		 527 .flags = AK881X_IF_MODE_SLAVE,
528};
529
530static struct i2c_board_info ak8813 = {
531 /* With open J18 jumper address is 0x21 */
532 I2C_BOARD_INFO("ak8813", 0x20),
533 .platform_data = &ak881x_pdata,
534};
535
560526f1 536static struct sh_vou_pdata sh_vou_pdata = {
2d151248
GL		 537 .bus_fmt = SH_VOU_BUS_8BIT,
538 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
539 .board_info = &ak8813,
540 .i2c_adap = 0,
2d151248
GL		 541};
542
543static struct resource sh_vou_resources[] = {
544 [0] = {
545 .start = 0xfe960000,
546 .end = 0xfe962043,
547 .flags = IORESOURCE_MEM,
548 },
549 [1] = {
550 .start = 55,
551 .flags = IORESOURCE_IRQ,
552 },
553};
554
555static struct platform_device vou_device = {
556 .name = "sh-vou",
557 .id = -1,
558 .num_resources = ARRAY_SIZE(sh_vou_resources),
559 .resource = sh_vou_resources,
560 .dev = {
561 .platform_data = &sh_vou_pdata,
562 },
2d151248
GL		 563};
564
287c1297
KM		 565static struct platform_device *ms7724se_devices[] __initdata = {
566 &heartbeat_device,
567 &smc91x_eth_device,
568 &lcdc_device,
569 &nor_flash_device,
570 &ceu0_device,
571 &ceu1_device,
572 &keysc_device,
a80cad95 573 &sh_eth_device,
9731f4a2 574 &sh7724_usb0_host_device,
f8f8c079 575 &sh7724_usb1_gadget_device,
3e9ad52b 576 &fsi_device,
c8d6bf9a 577 &fsi_ak4642_device,
0f79af60 578 &sdhi0_cn7_device,
5b380ec1 579 &sdhi1_cn8_device,
bbb892aa 580 &irda_device,
2d151248 581 &vou_device,
287c1297
KM		 582};
583
9f815a17
KM		 584/* I2C device */
585static struct i2c_board_info i2c0_devices[] = {
586 {
587 I2C_BOARD_INFO("ak4642", 0x12),
588 },
589};
590
a80cad95
KM		 591#define EEPROM_OP 0xBA206000
592#define EEPROM_ADR 0xBA206004
593#define EEPROM_DATA 0xBA20600C
594#define EEPROM_STAT 0xBA206010
595#define EEPROM_STRT 0xBA206014
596static int __init sh_eth_is_eeprom_ready(void)
597{
598 int t = 10000;
599
600 while (t--) {
9d56dd3b 601 if (!__raw_readw(EEPROM_STAT))
a80cad95 602 return 1;
c718aff2 603 udelay(1);
a80cad95
KM		 604 }
605
606 printk(KERN_ERR "ms7724se can not access to eeprom\n");
607 return 0;
608}
609
610static void __init sh_eth_init(void)
611{
612 int i;
8013cc9a 613 u16 mac;
a80cad95
KM		 614
615 /* check EEPROM status */
616 if (!sh_eth_is_eeprom_ready())
617 return;
618
619 /* read MAC addr from EEPROM */
620 for (i = 0 ; i < 3 ; i++) {
9d56dd3b
PM		 621 __raw_writew(0x0, EEPROM_OP); /* read */
622 __raw_writew(i*2, EEPROM_ADR);
623 __raw_writew(0x1, EEPROM_STRT);
a80cad95
KM		 624 if (!sh_eth_is_eeprom_ready())
625 return;
626
9d56dd3b 627 mac = __raw_readw(EEPROM_DATA);
8013cc9a
MD		 628 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
629 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
a80cad95 630 }
a80cad95
KM		 631}
632
287c1297
KM		 633#define SW4140 0xBA201000
634#define FPGA_OUT 0xBA200400
635#define PORT_HIZA 0xA4050158
9731f4a2 636#define PORT_MSELCRB 0xA4050182
287c1297
KM		 637
638#define SW41_A 0x0100
639#define SW41_B 0x0200
640#define SW41_C 0x0400
641#define SW41_D 0x0800
642#define SW41_E 0x1000
643#define SW41_F 0x2000
644#define SW41_G 0x4000
645#define SW41_H 0x8000
9731f4a2 646
3b9f2952
MD		 647extern char ms7724se_sdram_enter_start;
648extern char ms7724se_sdram_enter_end;
649extern char ms7724se_sdram_leave_start;
650extern char ms7724se_sdram_leave_end;
651
9f815a17
KM		 652
653static int __init arch_setup(void)
654{
655 /* enable I2C device */
656 i2c_register_board_info(0, i2c0_devices,
657 ARRAY_SIZE(i2c0_devices));
658 return 0;
659}
660arch_initcall(arch_setup);
661
287c1297
KM		 662static int __init devices_setup(void)
663{
9d56dd3b 664 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
16afc9fb 665 struct clk *clk;
2d151248 666 u16 fpga_out;
287c1297 667
3b9f2952 668 /* register board specific self-refresh code */
b67cf284
MD		 669 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
670 SUSP_SH_RSTANDBY,
3b9f2952
MD		 671 &ms7724se_sdram_enter_start,
672 &ms7724se_sdram_enter_end,
673 &ms7724se_sdram_leave_start,
674 &ms7724se_sdram_leave_end);
287c1297 675 /* Reset Release */
2d151248
GL		 676 fpga_out = __raw_readw(FPGA_OUT);
677 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
678 fpga_out &= ~((1 << 1) | /* LAN */
679 (1 << 4) | /* AK8813 PDN */
680 (1 << 5) | /* AK8813 RESET */
681 (1 << 6) | /* VIDEO DAC */
682 (1 << 7) | /* AK4643 */
683 (1 << 8) | /* IrDA */
684 (1 << 12) | /* USB0 */
685 (1 << 14)); /* RMII */
686 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
687
688 udelay(10);
689
690 /* AK8813 RESET */
691 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
692
693 udelay(10);
694
695 __raw_writew(fpga_out, FPGA_OUT);
287c1297 696
9731f4a2 697 /* turn on USB clocks, use external clock */
9d56dd3b 698 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
9731f4a2 699
7766e16b
MD		 700 /* Let LED9 show STATUS2 */
701 gpio_request(GPIO_FN_STATUS2, NULL);
702
703 /* Lit LED10 show STATUS0 */
704 gpio_request(GPIO_FN_STATUS0, NULL);
705
706 /* Lit LED11 show PDSTATUS */
707 gpio_request(GPIO_FN_PDSTATUS, NULL);
7766e16b 708
9731f4a2 709 /* enable USB0 port */
9d56dd3b 710 __raw_writew(0x0600, 0xa40501d4);
9731f4a2 711
f8f8c079 712 /* enable USB1 port */
9d56dd3b 713 __raw_writew(0x0600, 0xa4050192);
f8f8c079 714
287c1297
KM		 715 /* enable IRQ 0,1,2 */
716 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
717 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
718 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
719
720 /* enable SCIFA3 */
721 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
722 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
723 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
724 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
725 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
726
727 /* enable LCDC */
728 gpio_request(GPIO_FN_LCDD23, NULL);
729 gpio_request(GPIO_FN_LCDD22, NULL);
730 gpio_request(GPIO_FN_LCDD21, NULL);
731 gpio_request(GPIO_FN_LCDD20, NULL);
732 gpio_request(GPIO_FN_LCDD19, NULL);
733 gpio_request(GPIO_FN_LCDD18, NULL);
734 gpio_request(GPIO_FN_LCDD17, NULL);
735 gpio_request(GPIO_FN_LCDD16, NULL);
736 gpio_request(GPIO_FN_LCDD15, NULL);
737 gpio_request(GPIO_FN_LCDD14, NULL);
738 gpio_request(GPIO_FN_LCDD13, NULL);
739 gpio_request(GPIO_FN_LCDD12, NULL);
740 gpio_request(GPIO_FN_LCDD11, NULL);
741 gpio_request(GPIO_FN_LCDD10, NULL);
742 gpio_request(GPIO_FN_LCDD9, NULL);
743 gpio_request(GPIO_FN_LCDD8, NULL);
744 gpio_request(GPIO_FN_LCDD7, NULL);
745 gpio_request(GPIO_FN_LCDD6, NULL);
746 gpio_request(GPIO_FN_LCDD5, NULL);
747 gpio_request(GPIO_FN_LCDD4, NULL);
748 gpio_request(GPIO_FN_LCDD3, NULL);
749 gpio_request(GPIO_FN_LCDD2, NULL);
750 gpio_request(GPIO_FN_LCDD1, NULL);
751 gpio_request(GPIO_FN_LCDD0, NULL);
752 gpio_request(GPIO_FN_LCDDISP, NULL);
753 gpio_request(GPIO_FN_LCDHSYN, NULL);
754 gpio_request(GPIO_FN_LCDDCK, NULL);
755 gpio_request(GPIO_FN_LCDVSYN, NULL);
756 gpio_request(GPIO_FN_LCDDON, NULL);
757 gpio_request(GPIO_FN_LCDVEPWC, NULL);
758 gpio_request(GPIO_FN_LCDVCPWC, NULL);
759 gpio_request(GPIO_FN_LCDRD, NULL);
760 gpio_request(GPIO_FN_LCDLCLK, NULL);
9d56dd3b 761 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
287c1297
KM		 762
763 /* enable CEU0 */
764 gpio_request(GPIO_FN_VIO0_D15, NULL);
765 gpio_request(GPIO_FN_VIO0_D14, NULL);
766 gpio_request(GPIO_FN_VIO0_D13, NULL);
767 gpio_request(GPIO_FN_VIO0_D12, NULL);
768 gpio_request(GPIO_FN_VIO0_D11, NULL);
769 gpio_request(GPIO_FN_VIO0_D10, NULL);
770 gpio_request(GPIO_FN_VIO0_D9, NULL);
771 gpio_request(GPIO_FN_VIO0_D8, NULL);
772 gpio_request(GPIO_FN_VIO0_D7, NULL);
773 gpio_request(GPIO_FN_VIO0_D6, NULL);
774 gpio_request(GPIO_FN_VIO0_D5, NULL);
775 gpio_request(GPIO_FN_VIO0_D4, NULL);
776 gpio_request(GPIO_FN_VIO0_D3, NULL);
777 gpio_request(GPIO_FN_VIO0_D2, NULL);
778 gpio_request(GPIO_FN_VIO0_D1, NULL);
779 gpio_request(GPIO_FN_VIO0_D0, NULL);
780 gpio_request(GPIO_FN_VIO0_VD, NULL);
781 gpio_request(GPIO_FN_VIO0_CLK, NULL);
782 gpio_request(GPIO_FN_VIO0_FLD, NULL);
783 gpio_request(GPIO_FN_VIO0_HD, NULL);
84f7597c 784 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
287c1297
KM		 785
786 /* enable CEU1 */
787 gpio_request(GPIO_FN_VIO1_D7, NULL);
788 gpio_request(GPIO_FN_VIO1_D6, NULL);
789 gpio_request(GPIO_FN_VIO1_D5, NULL);
790 gpio_request(GPIO_FN_VIO1_D4, NULL);
791 gpio_request(GPIO_FN_VIO1_D3, NULL);
792 gpio_request(GPIO_FN_VIO1_D2, NULL);
793 gpio_request(GPIO_FN_VIO1_D1, NULL);
794 gpio_request(GPIO_FN_VIO1_D0, NULL);
795 gpio_request(GPIO_FN_VIO1_FLD, NULL);
796 gpio_request(GPIO_FN_VIO1_HD, NULL);
797 gpio_request(GPIO_FN_VIO1_VD, NULL);
798 gpio_request(GPIO_FN_VIO1_CLK, NULL);
84f7597c 799 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
287c1297
KM		 800
801 /* KEYSC */
802 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
803 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
804 gpio_request(GPIO_FN_KEYIN4, NULL);
805 gpio_request(GPIO_FN_KEYIN3, NULL);
806 gpio_request(GPIO_FN_KEYIN2, NULL);
807 gpio_request(GPIO_FN_KEYIN1, NULL);
808 gpio_request(GPIO_FN_KEYIN0, NULL);
809 gpio_request(GPIO_FN_KEYOUT3, NULL);
810 gpio_request(GPIO_FN_KEYOUT2, NULL);
811 gpio_request(GPIO_FN_KEYOUT1, NULL);
812 gpio_request(GPIO_FN_KEYOUT0, NULL);
813
3e9ad52b 814 /* enable FSI */
3e9ad52b 815 gpio_request(GPIO_FN_FSIMCKA, NULL);
c44352c5 816 gpio_request(GPIO_FN_FSIIASD, NULL);
3e9ad52b
KM		 817 gpio_request(GPIO_FN_FSIOASD, NULL);
818 gpio_request(GPIO_FN_FSIIABCK, NULL);
819 gpio_request(GPIO_FN_FSIIALRCK, NULL);
820 gpio_request(GPIO_FN_FSIOABCK, NULL);
821 gpio_request(GPIO_FN_FSIOALRCK, NULL);
822 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
3e9ad52b 823
16afc9fb
KM		 824 /* set SPU2 clock to 83.4 MHz */
825 clk = clk_get(NULL, "spu_clk");
193006f7 826 if (!IS_ERR(clk)) {
03c5ecd1
KM		 827 clk_set_rate(clk, clk_round_rate(clk, 83333333));
828 clk_put(clk);
829 }
16afc9fb 830
3e9ad52b 831 /* change parent of FSI A */
16afc9fb 832 clk = clk_get(NULL, "fsia_clk");
193006f7 833 if (!IS_ERR(clk)) {
e17ca5cf
NI		 834 /* 48kHz dummy clock was used to make sure 1/1 divide */
835 clk_set_rate(&sh7724_fsimcka_clk, 48000);
836 clk_set_parent(clk, &sh7724_fsimcka_clk);
837 clk_set_rate(clk, 48000);
03c5ecd1
KM		 838 clk_put(clk);
839 }
3e9ad52b 840
0f79af60
MD		 841 /* SDHI0 connected to cn7 */
842 gpio_request(GPIO_FN_SDHI0CD, NULL);
843 gpio_request(GPIO_FN_SDHI0WP, NULL);
844 gpio_request(GPIO_FN_SDHI0D3, NULL);
845 gpio_request(GPIO_FN_SDHI0D2, NULL);
846 gpio_request(GPIO_FN_SDHI0D1, NULL);
847 gpio_request(GPIO_FN_SDHI0D0, NULL);
848 gpio_request(GPIO_FN_SDHI0CMD, NULL);
849 gpio_request(GPIO_FN_SDHI0CLK, NULL);
850
5b380ec1
MD		 851 /* SDHI1 connected to cn8 */
852 gpio_request(GPIO_FN_SDHI1CD, NULL);
853 gpio_request(GPIO_FN_SDHI1WP, NULL);
854 gpio_request(GPIO_FN_SDHI1D3, NULL);
855 gpio_request(GPIO_FN_SDHI1D2, NULL);
856 gpio_request(GPIO_FN_SDHI1D1, NULL);
857 gpio_request(GPIO_FN_SDHI1D0, NULL);
858 gpio_request(GPIO_FN_SDHI1CMD, NULL);
859 gpio_request(GPIO_FN_SDHI1CLK, NULL);
860
bbb892aa
KM		 861 /* enable IrDA */
862 gpio_request(GPIO_FN_IRDA_OUT, NULL);
863 gpio_request(GPIO_FN_IRDA_IN, NULL);
864
a80cad95
KM		 865 /*
866 * enable SH-Eth
867 *
868 * please remove J33 pin from your board !!
869 *
870 * ms7724 board should not use GPIO_FN_LNKSTA pin
871 * So, This time PTX5 is set to input pin
872 */
873 gpio_request(GPIO_FN_RMII_RXD0, NULL);
874 gpio_request(GPIO_FN_RMII_RXD1, NULL);
875 gpio_request(GPIO_FN_RMII_TXD0, NULL);
876 gpio_request(GPIO_FN_RMII_TXD1, NULL);
877 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
878 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
879 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
880 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
881 gpio_request(GPIO_FN_MDIO, NULL);
882 gpio_request(GPIO_FN_MDC, NULL);
883 gpio_request(GPIO_PTX5, NULL);
884 gpio_direction_input(GPIO_PTX5);
885 sh_eth_init();
886
287c1297 887 if (sw & SW41_B) {
4f324311 888 /* 720p */
93ff2598
LP		 889 lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
890 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
287c1297
KM		 891 } else {
892 /* VGA */
93ff2598
LP		 893 lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
894 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
287c1297
KM		 895 }
896
897 if (sw & SW41_A) {
898 /* Digital monitor */
899 lcdc_info.ch[0].interface_type = RGB18;
900 lcdc_info.ch[0].flags = 0;
901 } else {
902 /* Analog monitor */
903 lcdc_info.ch[0].interface_type = RGB24;
904 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
905 }
906
2d151248
GL		 907 /* VOU */
908 gpio_request(GPIO_FN_DV_D15, NULL);
909 gpio_request(GPIO_FN_DV_D14, NULL);
910 gpio_request(GPIO_FN_DV_D13, NULL);
911 gpio_request(GPIO_FN_DV_D12, NULL);
912 gpio_request(GPIO_FN_DV_D11, NULL);
913 gpio_request(GPIO_FN_DV_D10, NULL);
914 gpio_request(GPIO_FN_DV_D9, NULL);
915 gpio_request(GPIO_FN_DV_D8, NULL);
916 gpio_request(GPIO_FN_DV_CLKI, NULL);
917 gpio_request(GPIO_FN_DV_CLK, NULL);
918 gpio_request(GPIO_FN_DV_VSYNC, NULL);
919 gpio_request(GPIO_FN_DV_HSYNC, NULL);
920
287c1297 921 return platform_add_devices(ms7724se_devices,
a80cad95 922 ARRAY_SIZE(ms7724se_devices));
287c1297
KM		 923}
924device_initcall(devices_setup);
925
926static struct sh_machine_vector mv_ms7724se __initmv = {
927 .mv_name = "ms7724se",
928 .mv_init_irq = init_se7724_IRQ,
929 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
930};