[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sh / boards / mach-se / 7206 / irq.c

/*
 * linux/arch/sh/boards/se/7206/irq.c
 *
 * Copyright (C) 2005,2006 Yoshinori Sato
 *
 * Hitachi SolutionEngine Support.
 *
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <mach-se/mach/se7206.h>

#define INTSTS0 0x31800000
#define INTSTS1 0x31800002
#define INTMSK0 0x31800004
#define INTMSK1 0x31800006
#define INTSEL  0x31800008

#define IRQ0_IRQ 64
#define IRQ1_IRQ 65
#define IRQ3_IRQ 67

#define INTC_IPR01 0xfffe0818
#define INTC_ICR1  0xfffe0802

static void disable_se7206_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned short val;
	unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
	unsigned short msk0,msk1;

	/* Set the priority in IPR to 0 */
	val = __raw_readw(INTC_IPR01);
	val &= mask;
	__raw_writew(val, INTC_IPR01);
	/* FPGA mask set */
	msk0 = __raw_readw(INTMSK0);
	msk1 = __raw_readw(INTMSK1);

	switch (irq) {
	case IRQ0_IRQ:
		msk0 |= 0x0010;
		break;
	case IRQ1_IRQ:
		msk0 |= 0x000f;
		break;
	case IRQ3_IRQ:
		msk0 |= 0x0f00;
		msk1 |= 0x00ff;
		break;
	}
	__raw_writew(msk0, INTMSK0);
	__raw_writew(msk1, INTMSK1);
}

static void enable_se7206_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned short val;
	unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
	unsigned short msk0,msk1;

	/* Set priority in IPR back to original value */
	val = __raw_readw(INTC_IPR01);
	val |= value;
	__raw_writew(val, INTC_IPR01);

	/* FPGA mask reset */
	msk0 = __raw_readw(INTMSK0);
	msk1 = __raw_readw(INTMSK1);

	switch (irq) {
	case IRQ0_IRQ:
		msk0 &= ~0x0010;
		break;
	case IRQ1_IRQ:
		msk0 &= ~0x000f;
		break;
	case IRQ3_IRQ:
		msk0 &= ~0x0f00;
		msk1 &= ~0x00ff;
		break;
	}
	__raw_writew(msk0, INTMSK0);
	__raw_writew(msk1, INTMSK1);
}

static void eoi_se7206_irq(struct irq_data *data)
{
	unsigned short sts0,sts1;
	unsigned int irq = data->irq;

	if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
		enable_se7206_irq(data);
	/* FPGA isr clear */
	sts0 = __raw_readw(INTSTS0);
	sts1 = __raw_readw(INTSTS1);

	switch (irq) {
	case IRQ0_IRQ:
		sts0 &= ~0x0010;
		break;
	case IRQ1_IRQ:
		sts0 &= ~0x000f;
		break;
	case IRQ3_IRQ:
		sts0 &= ~0x0f00;
		sts1 &= ~0x00ff;
		break;
	}
	__raw_writew(sts0, INTSTS0);
	__raw_writew(sts1, INTSTS1);
}

static struct irq_chip se7206_irq_chip __read_mostly = {
	.name		= "SE7206-FPGA",
	.irq_mask	= disable_se7206_irq,
	.irq_unmask	= enable_se7206_irq,
	.irq_eoi	= eoi_se7206_irq,
};

static void make_se7206_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
				      handle_level_irq, "level");
	disable_se7206_irq(irq_get_irq_data(irq));
}

/*
 * Initialize IRQ setting
 */
void __init init_se7206_IRQ(void)
{
	make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
	make_se7206_irq(IRQ1_IRQ); /* ATA */
	make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */

	__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */

	/* FPGA System register setup*/
	__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
	__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */

	/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
	__raw_writew(0x0001,INTSEL);
}
Commit	Line	Data
f36af3fd YS	1	/*
	2	* linux/arch/sh/boards/se/7206/irq.c
	3	*
	4	* Copyright (C) 2005,2006 Yoshinori Sato
	5	*
	6	* Hitachi SolutionEngine Support.
	7	*
	8	*/
f36af3fd YS	9	#include <linux/init.h>
f36af3fd YS	10	#include <linux/irq.h>
710ee0cc	11	#include <linux/io.h>
780a1568	12	#include <linux/interrupt.h>
939a24a6	13	#include <mach-se/mach/se7206.h>
f36af3fd YS	14
	15	#define INTSTS0 0x31800000
	16	#define INTSTS1 0x31800002
	17	#define INTMSK0 0x31800004
	18	#define INTMSK1 0x31800006
	19	#define INTSEL 0x31800008
	20
780a1568 YS	21	#define IRQ0_IRQ 64
	22	#define IRQ1_IRQ 65
	23	#define IRQ3_IRQ 67
	24
	25	#define INTC_IPR01 0xfffe0818
	26	#define INTC_ICR1 0xfffe0802
	27
15ff2c67	28	static void disable_se7206_irq(struct irq_data *data)
f36af3fd	29	{
15ff2c67	30	unsigned int irq = data->irq;
f36af3fd YS	31	unsigned short val;
	32	unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
	33	unsigned short msk0,msk1;
	34
	35	/* Set the priority in IPR to 0 */
9d56dd3b	36	val = __raw_readw(INTC_IPR01);
f36af3fd	37	val &= mask;
9d56dd3b	38	__raw_writew(val, INTC_IPR01);
f36af3fd	39	/* FPGA mask set */
9d56dd3b PM	40	msk0 = __raw_readw(INTMSK0);
9d56dd3b PM	41	msk1 = __raw_readw(INTMSK1);
f36af3fd YS	42
	43	switch (irq) {
	44	case IRQ0_IRQ:
	45	msk0 \|= 0x0010;
	46	break;
	47	case IRQ1_IRQ:
	48	msk0 \|= 0x000f;
	49	break;
780a1568	50	case IRQ3_IRQ:
f36af3fd YS	51	msk0 \|= 0x0f00;
	52	msk1 \|= 0x00ff;
	53	break;
	54	}
9d56dd3b PM	55	__raw_writew(msk0, INTMSK0);
9d56dd3b PM	56	__raw_writew(msk1, INTMSK1);
f36af3fd YS	57	}
f36af3fd YS	58
15ff2c67	59	static void enable_se7206_irq(struct irq_data *data)
f36af3fd	60	{
15ff2c67	61	unsigned int irq = data->irq;
f36af3fd YS	62	unsigned short val;
	63	unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
	64	unsigned short msk0,msk1;
	65
	66	/* Set priority in IPR back to original value */
9d56dd3b	67	val = __raw_readw(INTC_IPR01);
f36af3fd	68	val \|= value;
9d56dd3b	69	__raw_writew(val, INTC_IPR01);
f36af3fd YS	70
f36af3fd YS	71	/* FPGA mask reset */
9d56dd3b PM	72	msk0 = __raw_readw(INTMSK0);
9d56dd3b PM	73	msk1 = __raw_readw(INTMSK1);
f36af3fd YS	74
	75	switch (irq) {
	76	case IRQ0_IRQ:
	77	msk0 &= ~0x0010;
	78	break;
	79	case IRQ1_IRQ:
	80	msk0 &= ~0x000f;
	81	break;
780a1568	82	case IRQ3_IRQ:
f36af3fd YS	83	msk0 &= ~0x0f00;
	84	msk1 &= ~0x00ff;
	85	break;
	86	}
9d56dd3b PM	87	__raw_writew(msk0, INTMSK0);
9d56dd3b PM	88	__raw_writew(msk1, INTMSK1);
f36af3fd YS	89	}
f36af3fd YS	90
15ff2c67	91	static void eoi_se7206_irq(struct irq_data *data)
f36af3fd YS	92	{
f36af3fd YS	93	unsigned short sts0,sts1;
15ff2c67	94	unsigned int irq = data->irq;
f36af3fd	95
a821b279	96	if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
15ff2c67	97	enable_se7206_irq(data);
f36af3fd	98	/* FPGA isr clear */
9d56dd3b PM	99	sts0 = __raw_readw(INTSTS0);
9d56dd3b PM	100	sts1 = __raw_readw(INTSTS1);
f36af3fd YS	101
	102	switch (irq) {
	103	case IRQ0_IRQ:
	104	sts0 &= ~0x0010;
	105	break;
	106	case IRQ1_IRQ:
	107	sts0 &= ~0x000f;
	108	break;
780a1568	109	case IRQ3_IRQ:
f36af3fd YS	110	sts0 &= ~0x0f00;
	111	sts1 &= ~0x00ff;
	112	break;
	113	}
9d56dd3b PM	114	__raw_writew(sts0, INTSTS0);
9d56dd3b PM	115	__raw_writew(sts1, INTSTS1);
f36af3fd YS	116	}
f36af3fd YS	117
710ee0cc	118	static struct irq_chip se7206_irq_chip __read_mostly = {
780a1568	119	.name = "SE7206-FPGA",
15ff2c67 PM	120	.irq_mask = disable_se7206_irq,
	121	.irq_unmask = enable_se7206_irq,
	122	.irq_eoi = eoi_se7206_irq,
f36af3fd YS	123	};
	124
	125	static void make_se7206_irq(unsigned int irq)
	126	{
	127	disable_irq_nosync(irq);
fcb8918f	128	irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
710ee0cc	129	handle_level_irq, "level");
15ff2c67	130	disable_se7206_irq(irq_get_irq_data(irq));
f36af3fd YS	131	}
	132
	133	/*
	134	* Initialize IRQ setting
	135	*/
	136	void __init init_se7206_IRQ(void)
	137	{
	138	make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
	139	make_se7206_irq(IRQ1_IRQ); /* ATA */
	140	make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
e96ce8eb	141
27434f0a	142	__raw_writew(__raw_readw(INTC_ICR1) \| 0x000b, INTC_ICR1); /* ICR1 */
f36af3fd YS	143
f36af3fd YS	144	/* FPGA System register setup*/
9d56dd3b PM	145	__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
9d56dd3b PM	146	__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
e96ce8eb	147
f36af3fd	148	/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
9d56dd3b	149	__raw_writew(0x0001,INTSEL);
f36af3fd	150	}