[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / sh / boards / mach-ap325rxa / setup.c

/*
 * Renesas - AP-325RXA
 * (Compatible with Algo System ., LTD. - AP-320A)
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Author : Yusuke Goda <goda.yuske@renesas.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <media/ov772x.h>
#include <media/soc_camera.h>
#include <media/soc_camera_platform.h>
#include <media/sh_mobile_ceu.h>
#include <video/sh_mobile_lcdc.h>
#include <asm/io.h>
#include <asm/clock.h>
#include <asm/suspend.h>
#include <cpu/sh7723.h>

static struct smsc911x_platform_config smsc911x_config = {
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.flags		= SMSC911X_USE_32BIT,
};

static struct resource smsc9118_resources[] = {
	[0] = {
		.start	= 0xb6080000,
		.end	= 0xb60fffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 35,
		.end	= 35,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device smsc9118_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc9118_resources),
	.resource	= smsc9118_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
 * If this area erased, this board can not boot.
 */
static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	}, {
		.name = "kernel",
		.offset = MTDPART_OFS_APPEND,
		.size = (2 * 1024 * 1024),
	}, {
		.name = "free-area0",
		.offset = MTDPART_OFS_APPEND,
		.size = ((7 * 1024 * 1024) + (512 * 1024)),
	}, {
		.name = "CPLD-Data",
		.offset = MTDPART_OFS_APPEND,
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
		.size = (1024 * 128 * 2),
	}, {
		.name = "free-area1",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data ap325rxa_nor_flash_data = {
	.width		= 2,
	.parts		= ap325rxa_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(ap325rxa_nor_flash_partitions),
};

static struct resource ap325rxa_nor_flash_resources[] = {
	[0] = {
		.name	= "NOR Flash",
		.start	= 0x00000000,
		.end	= 0x00ffffff,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device ap325rxa_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= ap325rxa_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(ap325rxa_nor_flash_resources),
	.dev		= {
		.platform_data = &ap325rxa_nor_flash_data,
	},
};

static struct mtd_partition nand_partition_info[] = {
	{
		.name	= "nand_data",
		.offset	= 0,
		.size	= MTDPART_SIZ_FULL,
	},
};

static struct resource nand_flash_resources[] = {
	[0] = {
		.start	= 0xa4530000,
		.end	= 0xa45300ff,
		.flags	= IORESOURCE_MEM,
	}
};

static struct sh_flctl_platform_data nand_flash_data = {
	.parts		= nand_partition_info,
	.nr_parts	= ARRAY_SIZE(nand_partition_info),
	.flcmncr_val	= FCKSEL_E | TYPESEL_SET | NANWF_E,
	.has_hwecc	= 1,
};

static struct platform_device nand_flash_device = {
	.name		= "sh_flctl",
	.resource	= nand_flash_resources,
	.num_resources	= ARRAY_SIZE(nand_flash_resources),
	.dev		= {
		.platform_data = &nand_flash_data,
	},
};

#define FPGA_LCDREG	0xB4100180
#define FPGA_BKLREG	0xB4100212
#define FPGA_LCDREG_VAL	0x0018
#define PORT_MSELCRB	0xA4050182
#define PORT_HIZCRC	0xA405015C
#define PORT_DRVCRA	0xA405018A
#define PORT_DRVCRB	0xA405018C

static int ap320_wvga_set_brightness(int brightness)
{
	if (brightness) {
		gpio_set_value(GPIO_PTS3, 0);
		__raw_writew(0x100, FPGA_BKLREG);
	} else {
		__raw_writew(0, FPGA_BKLREG);
		gpio_set_value(GPIO_PTS3, 1);
	}
	
	return 0;
}

static int ap320_wvga_get_brightness(void)
{
	return gpio_get_value(GPIO_PTS3);
}

static void ap320_wvga_power_on(void)
{
	msleep(100);

	/* ASD AP-320/325 LCD ON */
	__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
}

static void ap320_wvga_power_off(void)
{
	/* ASD AP-320/325 LCD OFF */
	__raw_writew(0, FPGA_LCDREG);
}

static const struct fb_videomode ap325rxa_lcdc_modes[] = {
	{
		.name = "LB070WV1",
		.xres = 800,
		.yres = 480,
		.left_margin = 32,
		.right_margin = 160,
		.hsync_len = 8,
		.upper_margin = 63,
		.lower_margin = 80,
		.vsync_len = 1,
		.sync = 0, /* hsync and vsync are active low */
	},
};

static struct sh_mobile_lcdc_info lcdc_info = {
	.clock_source = LCDC_CLK_EXTERNAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type = RGB18,
		.clock_divider = 1,
		.lcd_modes = ap325rxa_lcdc_modes,
		.num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
		.panel_cfg = {
			.width = 152,	/* 7.0 inch */
			.height = 91,
			.display_on = ap320_wvga_power_on,
			.display_off = ap320_wvga_power_off,
		},
		.bl_info = {
			.name = "sh_mobile_lcdc_bl",
			.max_brightness = 1,
			.set_brightness = ap320_wvga_set_brightness,
			.get_brightness = ap320_wvga_get_brightness,
		},
	}
};

static struct resource lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe942fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(lcdc_resources),
	.resource	= lcdc_resources,
	.dev		= {
		.platform_data	= &lcdc_info,
	},
};

static void camera_power(int val)
{
	gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
	mdelay(10);
}

#ifdef CONFIG_I2C
/* support for the old ncm03j camera */
static unsigned char camera_ncm03j_magic[] =
{
	0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
	0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
	0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
	0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
	0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
	0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
	0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
	0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
	0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
	0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
	0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
	0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
	0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
	0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
	0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
	0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
};

static int camera_probe(void)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	int ret;

	if (!a)
		return -ENODEV;

	camera_power(1);
	msg.addr = 0x6e;
	msg.buf = camera_ncm03j_magic;
	msg.len = 2;
	msg.flags = 0;
	ret = i2c_transfer(a, &msg, 1);
	camera_power(0);

	return ret;
}

static int camera_set_capture(struct soc_camera_platform_info *info,
			      int enable)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	int ret = 0;
	int i;

	camera_power(0);
	if (!enable)
		return 0; /* no disable for now */

	camera_power(1);
	for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
		u_int8_t buf[8];

		msg.addr = 0x6e;
		msg.buf = buf;
		msg.len = 2;
		msg.flags = 0;

		buf[0] = camera_ncm03j_magic[i];
		buf[1] = camera_ncm03j_magic[i + 1];

		ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	}

	return ret;
}

static int ap325rxa_camera_add(struct soc_camera_device *icd);
static void ap325rxa_camera_del(struct soc_camera_device *icd);

static struct soc_camera_platform_info camera_info = {
	.format_name = "UYVY",
	.format_depth = 16,
	.format = {
		.code = V4L2_MBUS_FMT_UYVY8_2X8,
		.colorspace = V4L2_COLORSPACE_SMPTE170M,
		.field = V4L2_FIELD_NONE,
		.width = 640,
		.height = 480,
	},
	.mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
	V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
	V4L2_MBUS_DATA_ACTIVE_HIGH,
	.mbus_type = V4L2_MBUS_PARALLEL,
	.set_capture = camera_set_capture,
};

static struct soc_camera_link camera_link = {
	.bus_id		= 0,
	.add_device	= ap325rxa_camera_add,
	.del_device	= ap325rxa_camera_del,
	.module_name	= "soc_camera_platform",
	.priv		= &camera_info,
};

static struct platform_device *camera_device;

static void ap325rxa_camera_release(struct device *dev)
{
	soc_camera_platform_release(&camera_device);
}

static int ap325rxa_camera_add(struct soc_camera_device *icd)
{
	int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
					  ap325rxa_camera_release, 0);
	if (ret < 0)
		return ret;

	ret = camera_probe();
	if (ret < 0)
		soc_camera_platform_del(icd, camera_device, &camera_link);

	return ret;
}

static void ap325rxa_camera_del(struct soc_camera_device *icd)
{
	soc_camera_platform_del(icd, camera_device, &camera_link);
}
#endif /* CONFIG_I2C */

static int ov7725_power(struct device *dev, int mode)
{
	camera_power(0);
	if (mode)
		camera_power(1);

	return 0;
}

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(ceu_resources),
	.resource	= ceu_resources,
	.dev		= {
		.platform_data	= &sh_mobile_ceu_info,
	},
};

static struct resource sdhi0_cn3_resources[] = {
	[0] = {
		.name	= "SDHI0",
		.start	= 0x04ce0000,
		.end	= 0x04ce00ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 100,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
	.tmio_caps      = MMC_CAP_SDIO_IRQ,
};

static struct platform_device sdhi0_cn3_device = {
	.name		= "sh_mobile_sdhi",
	.id             = 0, /* "sdhi0" clock */
	.num_resources	= ARRAY_SIZE(sdhi0_cn3_resources),
	.resource	= sdhi0_cn3_resources,
	.dev = {
		.platform_data = &sdhi0_cn3_data,
	},
};

static struct resource sdhi1_cn7_resources[] = {
	[0] = {
		.name	= "SDHI1",
		.start	= 0x04cf0000,
		.end	= 0x04cf00ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 23,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
	.tmio_caps      = MMC_CAP_SDIO_IRQ,
};

static struct platform_device sdhi1_cn7_device = {
	.name		= "sh_mobile_sdhi",
	.id             = 1, /* "sdhi1" clock */
	.num_resources	= ARRAY_SIZE(sdhi1_cn7_resources),
	.resource	= sdhi1_cn7_resources,
	.dev = {
		.platform_data = &sdhi1_cn7_data,
	},
};

static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
	{
		I2C_BOARD_INFO("pcf8563", 0x51),
	},
};

static struct i2c_board_info ap325rxa_i2c_camera[] = {
	{
		I2C_BOARD_INFO("ov772x", 0x21),
	},
};

static struct ov772x_camera_info ov7725_info = {
	.flags		= OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
	.edgectrl	= OV772X_AUTO_EDGECTRL(0xf, 0),
};

static struct soc_camera_link ov7725_link = {
	.bus_id		= 0,
	.power		= ov7725_power,
	.board_info	= &ap325rxa_i2c_camera[0],
	.i2c_adapter_id	= 0,
	.priv		= &ov7725_info,
};

static struct platform_device ap325rxa_camera[] = {
	{
		.name	= "soc-camera-pdrv",
		.id	= 0,
		.dev	= {
			.platform_data = &ov7725_link,
		},
	}, {
		.name	= "soc-camera-pdrv",
		.id	= 1,
		.dev	= {
			.platform_data = &camera_link,
		},
	},
};

static struct platform_device *ap325rxa_devices[] __initdata = {
	&smsc9118_device,
	&ap325rxa_nor_flash_device,
	&lcdc_device,
	&ceu_device,
	&nand_flash_device,
	&sdhi0_cn3_device,
	&sdhi1_cn7_device,
	&ap325rxa_camera[0],
	&ap325rxa_camera[1],
};

extern char ap325rxa_sdram_enter_start;
extern char ap325rxa_sdram_enter_end;
extern char ap325rxa_sdram_leave_start;
extern char ap325rxa_sdram_leave_end;

static int __init ap325rxa_devices_setup(void)
{
	/* register board specific self-refresh code */
	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
					&ap325rxa_sdram_enter_start,
					&ap325rxa_sdram_enter_end,
					&ap325rxa_sdram_leave_start,
					&ap325rxa_sdram_leave_end);

	/* LD3 and LD4 LEDs */
	gpio_request(GPIO_PTX5, NULL); /* RUN */
	gpio_direction_output(GPIO_PTX5, 1);
	gpio_export(GPIO_PTX5, 0);

	gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
	gpio_direction_output(GPIO_PTX4, 0);
	gpio_export(GPIO_PTX4, 0);

	/* SW1 input */
	gpio_request(GPIO_PTF7, NULL); /* MODE */
	gpio_direction_input(GPIO_PTF7);
	gpio_export(GPIO_PTF7, 0);

	/* LCDC */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);

	/* LCD backlight */
	gpio_request(GPIO_PTS3, NULL);
	gpio_direction_output(GPIO_PTS3, 1);

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTZ7, NULL);
	gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
	gpio_request(GPIO_PTZ6, NULL);
	gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
	gpio_request(GPIO_PTZ5, NULL);
	gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
	gpio_request(GPIO_PTZ4, NULL);
	gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */

	__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);

	/* FLCTL */
	gpio_request(GPIO_FN_FCE, NULL);
	gpio_request(GPIO_FN_NAF7, NULL);
	gpio_request(GPIO_FN_NAF6, NULL);
	gpio_request(GPIO_FN_NAF5, NULL);
	gpio_request(GPIO_FN_NAF4, NULL);
	gpio_request(GPIO_FN_NAF3, NULL);
	gpio_request(GPIO_FN_NAF2, NULL);
	gpio_request(GPIO_FN_NAF1, NULL);
	gpio_request(GPIO_FN_NAF0, NULL);
	gpio_request(GPIO_FN_FCDE, NULL);
	gpio_request(GPIO_FN_FOE, NULL);
	gpio_request(GPIO_FN_FSC, NULL);
	gpio_request(GPIO_FN_FWE, NULL);
	gpio_request(GPIO_FN_FRB, NULL);

	__raw_writew(0, PORT_HIZCRC);
	__raw_writew(0xFFFF, PORT_DRVCRA);
	__raw_writew(0xFFFF, PORT_DRVCRB);

	platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);

	/* SDHI0 - CN3 - SD CARD */
	gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
	gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);

	/* SDHI1 - CN7 - MICRO SD CARD */
	gpio_request(GPIO_FN_SDHI1CD, NULL);
	gpio_request(GPIO_FN_SDHI1D3, NULL);
	gpio_request(GPIO_FN_SDHI1D2, NULL);
	gpio_request(GPIO_FN_SDHI1D1, NULL);
	gpio_request(GPIO_FN_SDHI1D0, NULL);
	gpio_request(GPIO_FN_SDHI1CMD, NULL);
	gpio_request(GPIO_FN_SDHI1CLK, NULL);

	i2c_register_board_info(0, ap325rxa_i2c_devices,
				ARRAY_SIZE(ap325rxa_i2c_devices));

	return platform_add_devices(ap325rxa_devices,
				ARRAY_SIZE(ap325rxa_devices));
}
arch_initcall(ap325rxa_devices_setup);

/* Return the board specific boot mode pin configuration */
static int ap325rxa_mode_pins(void)
{
	/* MD0=0, MD1=0, MD2=0: Clock Mode 0
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=1: Test Mode Disabled
	 */
	return MODE_PIN5 | MODE_PIN8;
}

static struct sh_machine_vector mv_ap325rxa __initmv = {
	.mv_name = "AP-325RXA",
	.mv_mode_pins = ap325rxa_mode_pins,
};
Commit	Line	Data
04e917b6 YG	1	/*
	2	* Renesas - AP-325RXA
	3	* (Compatible with Algo System ., LTD. - AP-320A)
	4	*
	5	* Copyright (C) 2008 Renesas Solutions Corp.
	6	* Author : Yusuke Goda <goda.yuske@renesas.com>
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/device.h>
4875ea22	15	#include <linux/interrupt.h>
04e917b6	16	#include <linux/platform_device.h>
365e1087	17	#include <linux/mmc/host.h>
960b9e7e	18	#include <linux/mmc/sh_mobile_sdhi.h>
04e917b6	19	#include <linux/mtd/physmap.h>
908978ac	20	#include <linux/mtd/sh_flctl.h>
04e917b6	21	#include <linux/delay.h>
026953db	22	#include <linux/i2c.h>
90b76491	23	#include <linux/smsc911x.h>
16587c45	24	#include <linux/gpio.h>
a1ad8033	25	#include <linux/videodev2.h>
47131258	26	#include <media/ov772x.h>
ba087e6f	27	#include <media/soc_camera.h>
8b2224dc MD	28	#include <media/soc_camera_platform.h>
8b2224dc MD	29	#include <media/sh_mobile_ceu.h>
225c9a8d	30	#include <video/sh_mobile_lcdc.h>
04e917b6	31	#include <asm/io.h>
6968980a	32	#include <asm/clock.h>
86c7d03a	33	#include <asm/suspend.h>
f7275650	34	#include <cpu/sh7723.h>
04e917b6	35
90b76491 SG	36	static struct smsc911x_platform_config smsc911x_config = {
	37	.phy_interface = PHY_INTERFACE_MODE_MII,
	38	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	39	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	40	.flags = SMSC911X_USE_32BIT,
4875ea22 MD	41	};
4875ea22 MD	42
90b76491	43	static struct resource smsc9118_resources[] = {
04e917b6 YG	44	[0] = {
	45	.start = 0xb6080000,
	46	.end = 0xb60fffff,
	47	.flags = IORESOURCE_MEM,
	48	},
	49	[1] = {
	50	.start = 35,
	51	.end = 35,
	52	.flags = IORESOURCE_IRQ,
	53	}
	54	};
	55
90b76491 SG	56	static struct platform_device smsc9118_device = {
90b76491 SG	57	.name = "smsc911x",
04e917b6	58	.id = -1,
90b76491 SG	59	.num_resources = ARRAY_SIZE(smsc9118_resources),
90b76491 SG	60	.resource = smsc9118_resources,
4875ea22	61	.dev = {
90b76491	62	.platform_data = &smsc911x_config,
4875ea22	63	},
04e917b6 YG	64	};
04e917b6 YG	65
aa88f169 NI	66	/*
	67	* AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
	68	* If this area erased, this board can not boot.
	69	*/
04e917b6 YG	70	static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
04e917b6 YG	71	{
aa88f169 NI	72	.name = "uboot",
	73	.offset = 0,
	74	.size = (1 * 1024 * 1024),
	75	.mask_flags = MTD_WRITEABLE, /* Read-only */
	76	}, {
	77	.name = "kernel",
	78	.offset = MTDPART_OFS_APPEND,
	79	.size = (2 * 1024 * 1024),
	80	}, {
	81	.name = "free-area0",
	82	.offset = MTDPART_OFS_APPEND,
	83	.size = ((7 * 1024 * 1024) + (512 * 1024)),
04e917b6	84	}, {
aa88f169 NI	85	.name = "CPLD-Data",
	86	.offset = MTDPART_OFS_APPEND,
	87	.mask_flags = MTD_WRITEABLE, /* Read-only */
	88	.size = (1024 * 128 * 2),
04e917b6	89	}, {
aa88f169 NI	90	.name = "free-area1",
	91	.offset = MTDPART_OFS_APPEND,
	92	.size = MTDPART_SIZ_FULL,
04e917b6 YG	93	},
	94	};
	95
	96	static struct physmap_flash_data ap325rxa_nor_flash_data = {
	97	.width = 2,
	98	.parts = ap325rxa_nor_flash_partitions,
	99	.nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
	100	};
	101
	102	static struct resource ap325rxa_nor_flash_resources[] = {
	103	[0] = {
	104	.name = "NOR Flash",
	105	.start = 0x00000000,
	106	.end = 0x00ffffff,
	107	.flags = IORESOURCE_MEM,
	108	}
	109	};
	110
	111	static struct platform_device ap325rxa_nor_flash_device = {
	112	.name = "physmap-flash",
	113	.resource = ap325rxa_nor_flash_resources,
	114	.num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
	115	.dev = {
	116	.platform_data = &ap325rxa_nor_flash_data,
	117	},
	118	};
	119
908978ac YS	120	static struct mtd_partition nand_partition_info[] = {
	121	{
	122	.name = "nand_data",
	123	.offset = 0,
	124	.size = MTDPART_SIZ_FULL,
	125	},
	126	};
	127
	128	static struct resource nand_flash_resources[] = {
	129	[0] = {
	130	.start = 0xa4530000,
	131	.end = 0xa45300ff,
	132	.flags = IORESOURCE_MEM,
	133	}
	134	};
	135
	136	static struct sh_flctl_platform_data nand_flash_data = {
	137	.parts = nand_partition_info,
	138	.nr_parts = ARRAY_SIZE(nand_partition_info),
	139	.flcmncr_val = FCKSEL_E \| TYPESEL_SET \| NANWF_E,
	140	.has_hwecc = 1,
	141	};
	142
	143	static struct platform_device nand_flash_device = {
	144	.name = "sh_flctl",
	145	.resource = nand_flash_resources,
	146	.num_resources = ARRAY_SIZE(nand_flash_resources),
	147	.dev = {
	148	.platform_data = &nand_flash_data,
	149	},
	150	};
	151
6968980a MD	152	#define FPGA_LCDREG 0xB4100180
	153	#define FPGA_BKLREG 0xB4100212
	154	#define FPGA_LCDREG_VAL 0x0018
8b2224dc	155	#define PORT_MSELCRB 0xA4050182
908978ac YS	156	#define PORT_HIZCRC 0xA405015C
	157	#define PORT_DRVCRA 0xA405018A
	158	#define PORT_DRVCRB 0xA405018C
6968980a	159
018882aa	160	static int ap320_wvga_set_brightness(int brightness)
bacbe55b AC	161	{
	162	if (brightness) {
	163	gpio_set_value(GPIO_PTS3, 0);
	164	__raw_writew(0x100, FPGA_BKLREG);
	165	} else {
	166	__raw_writew(0, FPGA_BKLREG);
	167	gpio_set_value(GPIO_PTS3, 1);
	168	}
	169
	170	return 0;
	171	}
	172
018882aa	173	static int ap320_wvga_get_brightness(void)
bacbe55b AC	174	{
	175	return gpio_get_value(GPIO_PTS3);
	176	}
	177
018882aa	178	static void ap320_wvga_power_on(void)
6968980a MD	179	{
	180	msleep(100);
	181
	182	/* ASD AP-320/325 LCD ON */
9d56dd3b	183	__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
6968980a MD	184	}
6968980a MD	185
018882aa	186	static void ap320_wvga_power_off(void)
93356d07	187	{
93356d07	188	/* ASD AP-320/325 LCD OFF */
9d56dd3b	189	__raw_writew(0, FPGA_LCDREG);
93356d07 MD	190	}
93356d07 MD	191
e04008eb	192	static const struct fb_videomode ap325rxa_lcdc_modes[] = {
44432407 GL	193	{
	194	.name = "LB070WV1",
	195	.xres = 800,
	196	.yres = 480,
	197	.left_margin = 32,
	198	.right_margin = 160,
	199	.hsync_len = 8,
	200	.upper_margin = 63,
	201	.lower_margin = 80,
	202	.vsync_len = 1,
	203	.sync = 0, /* hsync and vsync are active low */
	204	},
	205	};
	206
6968980a MD	207	static struct sh_mobile_lcdc_info lcdc_info = {
	208	.clock_source = LCDC_CLK_EXTERNAL,
	209	.ch[0] = {
	210	.chan = LCDC_CHAN_MAINLCD,
edd153a3	211	.fourcc = V4L2_PIX_FMT_RGB565,
6968980a MD	212	.interface_type = RGB18,
6968980a MD	213	.clock_divider = 1,
93ff2598 LP	214	.lcd_modes = ap325rxa_lcdc_modes,
93ff2598 LP	215	.num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
afaad83b LP	216	.panel_cfg = {
afaad83b LP	217	.width = 152, /* 7.0 inch */
ce9c008c	218	.height = 91,
6968980a	219	.display_on = ap320_wvga_power_on,
93356d07	220	.display_off = ap320_wvga_power_off,
bacbe55b AC	221	},
	222	.bl_info = {
	223	.name = "sh_mobile_lcdc_bl",
	224	.max_brightness = 1,
43059b0f LP	225	.set_brightness = ap320_wvga_set_brightness,
43059b0f LP	226	.get_brightness = ap320_wvga_get_brightness,
6968980a MD	227	},
	228	}
	229	};
	230
	231	static struct resource lcdc_resources[] = {
	232	[0] = {
	233	.name = "LCDC",
	234	.start = 0xfe940000, /* P4-only space */
a6f15ade	235	.end = 0xfe942fff,
6968980a MD	236	.flags = IORESOURCE_MEM,
6968980a MD	237	},
07905554 MD	238	[1] = {
	239	.start = 28,
	240	.flags = IORESOURCE_IRQ,
	241	},
6968980a MD	242	};
	243
	244	static struct platform_device lcdc_device = {
	245	.name = "sh_mobile_lcdc_fb",
	246	.num_resources = ARRAY_SIZE(lcdc_resources),
	247	.resource = lcdc_resources,
	248	.dev = {
	249	.platform_data = &lcdc_info,
	250	},
	251	};
	252
86746284 KM	253	static void camera_power(int val)
	254	{
	255	gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
	256	mdelay(10);
	257	}
	258
e565b518	259	#ifdef CONFIG_I2C
47131258	260	/* support for the old ncm03j camera */
8b2224dc MD	261	static unsigned char camera_ncm03j_magic[] =
	262	{
	263	0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
	264	0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
	265	0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
	266	0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
	267	0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
	268	0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
	269	0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
	270	0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
	271	0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
	272	0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
	273	0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
	274	0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
	275	0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
	276	0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
	277	0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
	278	0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
	279	};
	280
47131258 KM	281	static int camera_probe(void)
	282	{
	283	struct i2c_adapter *a = i2c_get_adapter(0);
	284	struct i2c_msg msg;
	285	int ret;
	286
37869fa2 MD	287	if (!a)
	288	return -ENODEV;
	289
47131258 KM	290	camera_power(1);
	291	msg.addr = 0x6e;
	292	msg.buf = camera_ncm03j_magic;
	293	msg.len = 2;
	294	msg.flags = 0;
	295	ret = i2c_transfer(a, &msg, 1);
	296	camera_power(0);
	297
	298	return ret;
	299	}
	300
8b2224dc MD	301	static int camera_set_capture(struct soc_camera_platform_info *info,
	302	int enable)
	303	{
	304	struct i2c_adapter *a = i2c_get_adapter(0);
	305	struct i2c_msg msg;
	306	int ret = 0;
	307	int i;
	308
86746284	309	camera_power(0);
8b2224dc MD	310	if (!enable)
	311	return 0; /* no disable for now */
	312
86746284	313	camera_power(1);
8b2224dc MD	314	for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
	315	u_int8_t buf[8];
	316
	317	msg.addr = 0x6e;
	318	msg.buf = buf;
	319	msg.len = 2;
	320	msg.flags = 0;
	321
	322	buf[0] = camera_ncm03j_magic[i];
	323	buf[1] = camera_ncm03j_magic[i + 1];
	324
	325	ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	326	}
	327
	328	return ret;
	329	}
	330
7dfff953 GL	331	static int ap325rxa_camera_add(struct soc_camera_device *icd);
7dfff953 GL	332	static void ap325rxa_camera_del(struct soc_camera_device *icd);
c41debaf	333
8b2224dc	334	static struct soc_camera_platform_info camera_info = {
8b2224dc MD	335	.format_name = "UYVY",
	336	.format_depth = 16,
	337	.format = {
ace6e979	338	.code = V4L2_MBUS_FMT_UYVY8_2X8,
8b2224dc	339	.colorspace = V4L2_COLORSPACE_SMPTE170M,
760697be	340	.field = V4L2_FIELD_NONE,
8b2224dc MD	341	.width = 640,
	342	.height = 480,
	343	},
7e5cf0ae GL	344	.mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING \| V4L2_MBUS_MASTER \|
	345	V4L2_MBUS_VSYNC_ACTIVE_HIGH \| V4L2_MBUS_HSYNC_ACTIVE_HIGH \|
	346	V4L2_MBUS_DATA_ACTIVE_HIGH,
	347	.mbus_type = V4L2_MBUS_PARALLEL,
8b2224dc	348	.set_capture = camera_set_capture,
0f448294 GL	349	};
0f448294 GL	350
f4cdd757	351	static struct soc_camera_link camera_link = {
0f448294 GL	352	.bus_id = 0,
	353	.add_device = ap325rxa_camera_add,
	354	.del_device = ap325rxa_camera_del,
	355	.module_name = "soc_camera_platform",
	356	.priv = &camera_info,
8b2224dc MD	357	};
8b2224dc MD	358
a3793a0d GL	359	static struct platform_device *camera_device;
	360
	361	static void ap325rxa_camera_release(struct device *dev)
0bab829d	362	{
a3793a0d	363	soc_camera_platform_release(&camera_device);
0bab829d GL	364	}
0bab829d GL	365
7dfff953	366	static int ap325rxa_camera_add(struct soc_camera_device *icd)
47131258	367	{
7dfff953	368	int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
a3793a0d GL	369	ap325rxa_camera_release, 0);
	370	if (ret < 0)
	371	return ret;
47131258	372
a3793a0d GL	373	ret = camera_probe();
a3793a0d GL	374	if (ret < 0)
7dfff953	375	soc_camera_platform_del(icd, camera_device, &camera_link);
bc1937b4	376
a3793a0d	377	return ret;
47131258	378	}
47131258	379
7dfff953	380	static void ap325rxa_camera_del(struct soc_camera_device *icd)
c41debaf	381	{
7dfff953	382	soc_camera_platform_del(icd, camera_device, &camera_link);
c41debaf	383	}
e565b518	384	#endif /* CONFIG_I2C */
8b2224dc	385
47131258 KM	386	static int ov7725_power(struct device *dev, int mode)
	387	{
	388	camera_power(0);
	389	if (mode)
	390	camera_power(1);
	391
	392	return 0;
	393	}
	394
8b2224dc	395	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
46368fa0	396	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
8b2224dc MD	397	};
	398
	399	static struct resource ceu_resources[] = {
	400	[0] = {
	401	.name = "CEU",
	402	.start = 0xfe910000,
	403	.end = 0xfe91009f,
	404	.flags = IORESOURCE_MEM,
	405	},
	406	[1] = {
	407	.start = 52,
	408	.flags = IORESOURCE_IRQ,
	409	},
	410	[2] = {
	411	/* place holder for contiguous memory */
	412	},
	413	};
	414
	415	static struct platform_device ceu_device = {
	416	.name = "sh_mobile_ceu",
a42b6dd6	417	.id = 0, /* "ceu0" clock */
8b2224dc MD	418	.num_resources = ARRAY_SIZE(ceu_resources),
	419	.resource = ceu_resources,
	420	.dev = {
	421	.platform_data = &sh_mobile_ceu_info,
	422	},
	423	};
	424
17f81473 MD	425	static struct resource sdhi0_cn3_resources[] = {
	426	[0] = {
	427	.name = "SDHI0",
	428	.start = 0x04ce0000,
d80e9221	429	.end = 0x04ce00ff,
17f81473 MD	430	.flags = IORESOURCE_MEM,
	431	},
	432	[1] = {
e3e80046	433	.start = 100,
17f81473 MD	434	.flags = IORESOURCE_IRQ,
17f81473 MD	435	},
fbdd9a70 MD	436	};
fbdd9a70 MD	437
365e1087 AH	438	static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
	439	.tmio_caps = MMC_CAP_SDIO_IRQ,
	440	};
	441
17f81473 MD	442	static struct platform_device sdhi0_cn3_device = {
17f81473 MD	443	.name = "sh_mobile_sdhi",
8b431a7e	444	.id = 0, /* "sdhi0" clock */
17f81473 MD	445	.num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
17f81473 MD	446	.resource = sdhi0_cn3_resources,
365e1087 AH	447	.dev = {
	448	.platform_data = &sdhi0_cn3_data,
	449	},
fbdd9a70 MD	450	};
fbdd9a70 MD	451
8b431a7e MD	452	static struct resource sdhi1_cn7_resources[] = {
	453	[0] = {
	454	.name = "SDHI1",
	455	.start = 0x04cf0000,
d80e9221	456	.end = 0x04cf00ff,
8b431a7e MD	457	.flags = IORESOURCE_MEM,
	458	},
	459	[1] = {
e3e80046	460	.start = 23,
8b431a7e MD	461	.flags = IORESOURCE_IRQ,
	462	},
	463	};
	464
365e1087 AH	465	static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
	466	.tmio_caps = MMC_CAP_SDIO_IRQ,
	467	};
	468
8b431a7e MD	469	static struct platform_device sdhi1_cn7_device = {
	470	.name = "sh_mobile_sdhi",
	471	.id = 1, /* "sdhi1" clock */
	472	.num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
	473	.resource = sdhi1_cn7_resources,
365e1087 AH	474	.dev = {
	475	.platform_data = &sdhi1_cn7_data,
	476	},
8b431a7e MD	477	};
8b431a7e MD	478
026953db	479	static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
a3e02706 NI	480	{
	481	I2C_BOARD_INFO("pcf8563", 0x51),
	482	},
194a1730 GL	483	};
	484
	485	static struct i2c_board_info ap325rxa_i2c_camera[] = {
47131258 KM	486	{
47131258 KM	487	I2C_BOARD_INFO("ov772x", 0x21),
194a1730 GL	488	},
	489	};
	490
	491	static struct ov772x_camera_info ov7725_info = {
284f28ee	492	.flags = OV772X_FLAG_VFLIP \| OV772X_FLAG_HFLIP,
194a1730	493	.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
0f448294 GL	494	};
	495
	496	static struct soc_camera_link ov7725_link = {
	497	.bus_id = 0,
	498	.power = ov7725_power,
	499	.board_info = &ap325rxa_i2c_camera[0],
	500	.i2c_adapter_id = 0,
0f448294	501	.priv = &ov7725_info,
194a1730 GL	502	};
194a1730 GL	503
c41debaf GL	504	static struct platform_device ap325rxa_camera[] = {
	505	{
	506	.name = "soc-camera-pdrv",
	507	.id = 0,
	508	.dev = {
0f448294	509	.platform_data = &ov7725_link,
c41debaf GL	510	},
	511	}, {
	512	.name = "soc-camera-pdrv",
	513	.id = 1,
	514	.dev = {
0f448294	515	.platform_data = &camera_link,
c41debaf	516	},
47131258	517	},
026953db MD	518	};
026953db MD	519
194a1730 GL	520	static struct platform_device *ap325rxa_devices[] __initdata = {
	521	&smsc9118_device,
	522	&ap325rxa_nor_flash_device,
	523	&lcdc_device,
	524	&ceu_device,
	525	&nand_flash_device,
17f81473	526	&sdhi0_cn3_device,
8b431a7e	527	&sdhi1_cn7_device,
c41debaf GL	528	&ap325rxa_camera[0],
c41debaf GL	529	&ap325rxa_camera[1],
194a1730 GL	530	};
194a1730 GL	531
86c7d03a MD	532	extern char ap325rxa_sdram_enter_start;
	533	extern char ap325rxa_sdram_enter_end;
	534	extern char ap325rxa_sdram_leave_start;
	535	extern char ap325rxa_sdram_leave_end;
	536
04e917b6 YG	537	static int __init ap325rxa_devices_setup(void)
04e917b6 YG	538	{
86c7d03a MD	539	/* register board specific self-refresh code */
	540	sh_mobile_register_self_refresh(SUSP_SH_STANDBY \| SUSP_SH_SF,
	541	&ap325rxa_sdram_enter_start,
	542	&ap325rxa_sdram_enter_end,
	543	&ap325rxa_sdram_leave_start,
	544	&ap325rxa_sdram_leave_end);
	545
16587c45 MD	546	/* LD3 and LD4 LEDs */
	547	gpio_request(GPIO_PTX5, NULL); /* RUN */
	548	gpio_direction_output(GPIO_PTX5, 1);
	549	gpio_export(GPIO_PTX5, 0);
	550
	551	gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
	552	gpio_direction_output(GPIO_PTX4, 0);
	553	gpio_export(GPIO_PTX4, 0);
	554
	555	/* SW1 input */
	556	gpio_request(GPIO_PTF7, NULL); /* MODE */
	557	gpio_direction_input(GPIO_PTF7);
	558	gpio_export(GPIO_PTF7, 0);
	559
	560	/* LCDC */
16587c45 MD	561	gpio_request(GPIO_FN_LCDD15, NULL);
	562	gpio_request(GPIO_FN_LCDD14, NULL);
	563	gpio_request(GPIO_FN_LCDD13, NULL);
	564	gpio_request(GPIO_FN_LCDD12, NULL);
	565	gpio_request(GPIO_FN_LCDD11, NULL);
	566	gpio_request(GPIO_FN_LCDD10, NULL);
	567	gpio_request(GPIO_FN_LCDD9, NULL);
	568	gpio_request(GPIO_FN_LCDD8, NULL);
	569	gpio_request(GPIO_FN_LCDD7, NULL);
	570	gpio_request(GPIO_FN_LCDD6, NULL);
	571	gpio_request(GPIO_FN_LCDD5, NULL);
	572	gpio_request(GPIO_FN_LCDD4, NULL);
	573	gpio_request(GPIO_FN_LCDD3, NULL);
	574	gpio_request(GPIO_FN_LCDD2, NULL);
	575	gpio_request(GPIO_FN_LCDD1, NULL);
	576	gpio_request(GPIO_FN_LCDD0, NULL);
	577	gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
	578	gpio_request(GPIO_FN_LCDDCK, NULL);
	579	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	580	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	581	gpio_request(GPIO_FN_LCDVSYN, NULL);
	582	gpio_request(GPIO_FN_LCDHSYN, NULL);
	583	gpio_request(GPIO_FN_LCDDISP, NULL);
	584	gpio_request(GPIO_FN_LCDDON, NULL);
	585
	586	/* LCD backlight */
	587	gpio_request(GPIO_PTS3, NULL);
	588	gpio_direction_output(GPIO_PTS3, 1);
	589
	590	/* CEU */
16587c45 MD	591	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	592	gpio_request(GPIO_FN_VIO_VD2, NULL);
	593	gpio_request(GPIO_FN_VIO_HD2, NULL);
	594	gpio_request(GPIO_FN_VIO_FLD, NULL);
	595	gpio_request(GPIO_FN_VIO_CKO, NULL);
	596	gpio_request(GPIO_FN_VIO_D15, NULL);
	597	gpio_request(GPIO_FN_VIO_D14, NULL);
	598	gpio_request(GPIO_FN_VIO_D13, NULL);
	599	gpio_request(GPIO_FN_VIO_D12, NULL);
	600	gpio_request(GPIO_FN_VIO_D11, NULL);
	601	gpio_request(GPIO_FN_VIO_D10, NULL);
	602	gpio_request(GPIO_FN_VIO_D9, NULL);
	603	gpio_request(GPIO_FN_VIO_D8, NULL);
	604
	605	gpio_request(GPIO_PTZ7, NULL);
	606	gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
	607	gpio_request(GPIO_PTZ6, NULL);
	608	gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
	609	gpio_request(GPIO_PTZ5, NULL);
86746284	610	gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
16587c45 MD	611	gpio_request(GPIO_PTZ4, NULL);
	612	gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
	613
9d56dd3b	614	__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
8b2224dc	615
908978ac	616	/* FLCTL */
dd0e20e5 PM	617	gpio_request(GPIO_FN_FCE, NULL);
	618	gpio_request(GPIO_FN_NAF7, NULL);
	619	gpio_request(GPIO_FN_NAF6, NULL);
	620	gpio_request(GPIO_FN_NAF5, NULL);
	621	gpio_request(GPIO_FN_NAF4, NULL);
	622	gpio_request(GPIO_FN_NAF3, NULL);
	623	gpio_request(GPIO_FN_NAF2, NULL);
	624	gpio_request(GPIO_FN_NAF1, NULL);
	625	gpio_request(GPIO_FN_NAF0, NULL);
	626	gpio_request(GPIO_FN_FCDE, NULL);
	627	gpio_request(GPIO_FN_FOE, NULL);
	628	gpio_request(GPIO_FN_FSC, NULL);
	629	gpio_request(GPIO_FN_FWE, NULL);
	630	gpio_request(GPIO_FN_FRB, NULL);
908978ac	631
9d56dd3b PM	632	__raw_writew(0, PORT_HIZCRC);
	633	__raw_writew(0xFFFF, PORT_DRVCRA);
	634	__raw_writew(0xFFFF, PORT_DRVCRB);
908978ac	635
8b2224dc	636	platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
6968980a	637
8b431a7e	638	/* SDHI0 - CN3 - SD CARD */
17f81473 MD	639	gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
	640	gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
	641	gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
	642	gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
	643	gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
	644	gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
	645	gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
	646	gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
	647
8b431a7e MD	648	/* SDHI1 - CN7 - MICRO SD CARD */
	649	gpio_request(GPIO_FN_SDHI1CD, NULL);
	650	gpio_request(GPIO_FN_SDHI1D3, NULL);
	651	gpio_request(GPIO_FN_SDHI1D2, NULL);
	652	gpio_request(GPIO_FN_SDHI1D1, NULL);
	653	gpio_request(GPIO_FN_SDHI1D0, NULL);
	654	gpio_request(GPIO_FN_SDHI1CMD, NULL);
	655	gpio_request(GPIO_FN_SDHI1CLK, NULL);
	656
026953db MD	657	i2c_register_board_info(0, ap325rxa_i2c_devices,
026953db MD	658	ARRAY_SIZE(ap325rxa_i2c_devices));
908978ac	659
04e917b6 YG	660	return platform_add_devices(ap325rxa_devices,
	661	ARRAY_SIZE(ap325rxa_devices));
	662	}
dbefd606	663	arch_initcall(ap325rxa_devices_setup);
04e917b6	664
c01641b4 MD	665	/* Return the board specific boot mode pin configuration */
	666	static int ap325rxa_mode_pins(void)
	667	{
	668	/* MD0=0, MD1=0, MD2=0: Clock Mode 0
	669	* MD3=0: 16-bit Area0 Bus Width
	670	* MD5=1: Little Endian
	671	* TSTMD=1, MD8=1: Test Mode Disabled
	672	*/
	673	return MODE_PIN5 \| MODE_PIN8;
	674	}
	675
04e917b6 YG	676	static struct sh_machine_vector mv_ap325rxa __initmv = {
04e917b6 YG	677	.mv_name = "AP-325RXA",
c01641b4	678	.mv_mode_pins = ap325rxa_mode_pins,
04e917b6	679	};