Merge branch 'x86/ptrace' into x86/tsc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / s390 / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
1da177e4
LT
15#include <linux/errno.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/mm.h>
22#include <linux/interrupt.h>
23#include <linux/time.h>
3367b994 24#include <linux/sysdev.h>
1da177e4
LT
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/smp.h>
28#include <linux/types.h>
29#include <linux/profile.h>
30#include <linux/timex.h>
31#include <linux/notifier.h>
dc64bef5 32#include <linux/clocksource.h>
5a62b192 33#include <linux/clockchips.h>
d2fec595 34#include <linux/bootmem.h>
1da177e4
LT
35#include <asm/uaccess.h>
36#include <asm/delay.h>
37#include <asm/s390_ext.h>
38#include <asm/div64.h>
39#include <asm/irq.h>
5a489b98 40#include <asm/irq_regs.h>
1da177e4 41#include <asm/timer.h>
d54853ef 42#include <asm/etr.h>
a806170e 43#include <asm/cio.h>
1da177e4
LT
44
45/* change this if you have some constant time drift */
46#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
47#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
48
d54853ef
MS
49/* The value of the TOD clock for 1.1.1970. */
50#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
51
1da177e4
LT
52/*
53 * Create a small time difference between the timer interrupts
54 * on the different cpus to avoid lock contention.
55 */
56#define CPU_DEVIATION (smp_processor_id() << 12)
57
58#define TICK_SIZE tick
59
1da177e4 60static ext_int_info_t ext_int_info_cc;
d54853ef 61static ext_int_info_t ext_int_etr_cc;
8107d829 62static u64 sched_clock_base_cc;
5a62b192
HC
63
64static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 65
1da177e4
LT
66/*
67 * Scheduler clock - returns current time in nanosec units.
68 */
69unsigned long long sched_clock(void)
70{
8107d829 71 return ((get_clock_xt() - sched_clock_base_cc) * 125) >> 9;
1da177e4
LT
72}
73
32f65f27
JG
74/*
75 * Monotonic_clock - returns # of nanoseconds passed since time_init()
76 */
77unsigned long long monotonic_clock(void)
78{
79 return sched_clock();
80}
81EXPORT_SYMBOL(monotonic_clock);
82
1da177e4
LT
83void tod_to_timeval(__u64 todval, struct timespec *xtime)
84{
85 unsigned long long sec;
86
87 sec = todval >> 12;
88 do_div(sec, 1000000);
89 xtime->tv_sec = sec;
90 todval -= (sec * 1000000) << 12;
91 xtime->tv_nsec = ((todval * 1000) >> 12);
92}
93
1da177e4 94#ifdef CONFIG_PROFILING
5a489b98 95#define s390_do_profile() profile_tick(CPU_PROFILING)
1da177e4 96#else
5a489b98 97#define s390_do_profile() do { ; } while(0)
1da177e4
LT
98#endif /* CONFIG_PROFILING */
99
5a62b192 100void clock_comparator_work(void)
1da177e4 101{
5a62b192 102 struct clock_event_device *cd;
1da177e4 103
5a62b192
HC
104 S390_lowcore.clock_comparator = -1ULL;
105 set_clock_comparator(S390_lowcore.clock_comparator);
106 cd = &__get_cpu_var(comparators);
107 cd->event_handler(cd);
5a489b98 108 s390_do_profile();
1da177e4
LT
109}
110
1da177e4 111/*
5a62b192 112 * Fixup the clock comparator.
1da177e4 113 */
5a62b192 114static void fixup_clock_comparator(unsigned long long delta)
1da177e4 115{
5a62b192
HC
116 /* If nobody is waiting there's nothing to fix. */
117 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 118 return;
5a62b192
HC
119 S390_lowcore.clock_comparator += delta;
120 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
121}
122
5a62b192
HC
123static int s390_next_event(unsigned long delta,
124 struct clock_event_device *evt)
1da177e4 125{
5a62b192
HC
126 S390_lowcore.clock_comparator = get_clock() + delta;
127 set_clock_comparator(S390_lowcore.clock_comparator);
128 return 0;
1da177e4
LT
129}
130
5a62b192
HC
131static void s390_set_mode(enum clock_event_mode mode,
132 struct clock_event_device *evt)
1da177e4 133{
d54853ef
MS
134}
135
136/*
137 * Set up lowcore and control register of the current cpu to
138 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
139 */
140void init_cpu_timer(void)
141{
5a62b192
HC
142 struct clock_event_device *cd;
143 int cpu;
144
145 S390_lowcore.clock_comparator = -1ULL;
146 set_clock_comparator(S390_lowcore.clock_comparator);
147
148 cpu = smp_processor_id();
149 cd = &per_cpu(comparators, cpu);
150 cd->name = "comparator";
151 cd->features = CLOCK_EVT_FEAT_ONESHOT;
152 cd->mult = 16777;
153 cd->shift = 12;
154 cd->min_delta_ns = 1;
155 cd->max_delta_ns = LONG_MAX;
156 cd->rating = 400;
157 cd->cpumask = cpumask_of_cpu(cpu);
158 cd->set_next_event = s390_next_event;
159 cd->set_mode = s390_set_mode;
160
161 clockevents_register_device(cd);
d54853ef
MS
162
163 /* Enable clock comparator timer interrupt. */
164 __ctl_set_bit(0,11);
165
d2fec595 166 /* Always allow the timing alert external interrupt. */
d54853ef
MS
167 __ctl_set_bit(0, 4);
168}
169
170static void clock_comparator_interrupt(__u16 code)
171{
d3d238c7
HC
172 if (S390_lowcore.clock_comparator == -1ULL)
173 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
174}
175
d2fec595
MS
176static void etr_timing_alert(struct etr_irq_parm *);
177static void stp_timing_alert(struct stp_irq_parm *);
178
179static void timing_alert_interrupt(__u16 code)
180{
181 if (S390_lowcore.ext_params & 0x00c40000)
182 etr_timing_alert((struct etr_irq_parm *)
183 &S390_lowcore.ext_params);
184 if (S390_lowcore.ext_params & 0x00038000)
185 stp_timing_alert((struct stp_irq_parm *)
186 &S390_lowcore.ext_params);
187}
188
d54853ef 189static void etr_reset(void);
d2fec595 190static void stp_reset(void);
d54853ef
MS
191
192/*
193 * Get the TOD clock running.
194 */
195static u64 __init reset_tod_clock(void)
196{
197 u64 time;
198
199 etr_reset();
d2fec595 200 stp_reset();
d54853ef
MS
201 if (store_clock(&time) == 0)
202 return time;
203 /* TOD clock not running. Set the clock to Unix Epoch. */
204 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
205 panic("TOD clock not operational.");
1da177e4 206
d54853ef 207 return TOD_UNIX_EPOCH;
1da177e4
LT
208}
209
dc64bef5
MS
210static cycle_t read_tod_clock(void)
211{
212 return get_clock();
213}
214
215static struct clocksource clocksource_tod = {
216 .name = "tod",
d2cb0e6e 217 .rating = 400,
dc64bef5
MS
218 .read = read_tod_clock,
219 .mask = -1ULL,
220 .mult = 1000,
221 .shift = 12,
cc02d809 222 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
223};
224
225
1da177e4
LT
226/*
227 * Initialize the TOD clock and the CPU timer of
228 * the boot cpu.
229 */
230void __init time_init(void)
231{
8107d829 232 sched_clock_base_cc = reset_tod_clock();
1da177e4
LT
233
234 /* set xtime */
8107d829 235 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &xtime);
1da177e4
LT
236 set_normalized_timespec(&wall_to_monotonic,
237 -xtime.tv_sec, -xtime.tv_nsec);
238
239 /* request the clock comparator external interrupt */
d54853ef
MS
240 if (register_early_external_interrupt(0x1004,
241 clock_comparator_interrupt,
1da177e4
LT
242 &ext_int_info_cc) != 0)
243 panic("Couldn't request external interrupt 0x1004");
244
dc64bef5
MS
245 if (clocksource_register(&clocksource_tod) != 0)
246 panic("Could not register TOD clock source");
247
d2fec595
MS
248 /* request the timing alert external interrupt */
249 if (register_early_external_interrupt(0x1406,
250 timing_alert_interrupt,
d54853ef
MS
251 &ext_int_etr_cc) != 0)
252 panic("Couldn't request external interrupt 0x1406");
253
254 /* Enable TOD clock interrupts on the boot cpu. */
255 init_cpu_timer();
1da177e4 256
1da177e4
LT
257#ifdef CONFIG_VIRT_TIMER
258 vtime_init();
259#endif
d54853ef
MS
260}
261
d2fec595
MS
262/*
263 * The time is "clock". old is what we think the time is.
264 * Adjust the value by a multiple of jiffies and add the delta to ntp.
265 * "delay" is an approximation how long the synchronization took. If
266 * the time correction is positive, then "delay" is subtracted from
267 * the time difference and only the remaining part is passed to ntp.
268 */
269static unsigned long long adjust_time(unsigned long long old,
270 unsigned long long clock,
271 unsigned long long delay)
272{
273 unsigned long long delta, ticks;
274 struct timex adjust;
275
276 if (clock > old) {
277 /* It is later than we thought. */
278 delta = ticks = clock - old;
279 delta = ticks = (delta < delay) ? 0 : delta - delay;
280 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
281 adjust.offset = ticks * (1000000 / HZ);
282 } else {
283 /* It is earlier than we thought. */
284 delta = ticks = old - clock;
285 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
286 delta = -delta;
287 adjust.offset = -ticks * (1000000 / HZ);
288 }
8107d829 289 sched_clock_base_cc += delta;
d2fec595
MS
290 if (adjust.offset != 0) {
291 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
292 adjust.offset);
293 adjust.modes = ADJ_OFFSET_SINGLESHOT;
294 do_adjtimex(&adjust);
295 }
296 return delta;
297}
298
299static DEFINE_PER_CPU(atomic_t, clock_sync_word);
300static unsigned long clock_sync_flags;
301
302#define CLOCK_SYNC_HAS_ETR 0
303#define CLOCK_SYNC_HAS_STP 1
304#define CLOCK_SYNC_ETR 2
305#define CLOCK_SYNC_STP 3
306
307/*
308 * The synchronous get_clock function. It will write the current clock
309 * value to the clock pointer and return 0 if the clock is in sync with
310 * the external time source. If the clock mode is local it will return
311 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
312 * reference.
313 */
314int get_sync_clock(unsigned long long *clock)
315{
316 atomic_t *sw_ptr;
317 unsigned int sw0, sw1;
318
319 sw_ptr = &get_cpu_var(clock_sync_word);
320 sw0 = atomic_read(sw_ptr);
321 *clock = get_clock();
322 sw1 = atomic_read(sw_ptr);
323 put_cpu_var(clock_sync_sync);
324 if (sw0 == sw1 && (sw0 & 0x80000000U))
325 /* Success: time is in sync. */
326 return 0;
327 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
328 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
329 return -ENOSYS;
330 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
331 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
332 return -EACCES;
333 return -EAGAIN;
334}
335EXPORT_SYMBOL(get_sync_clock);
336
337/*
338 * Make get_sync_clock return -EAGAIN.
339 */
340static void disable_sync_clock(void *dummy)
341{
342 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
343 /*
344 * Clear the in-sync bit 2^31. All get_sync_clock calls will
345 * fail until the sync bit is turned back on. In addition
346 * increase the "sequence" counter to avoid the race of an
347 * etr event and the complete recovery against get_sync_clock.
348 */
349 atomic_clear_mask(0x80000000, sw_ptr);
350 atomic_inc(sw_ptr);
351}
352
353/*
354 * Make get_sync_clock return 0 again.
355 * Needs to be called from a context disabled for preemption.
356 */
357static void enable_sync_clock(void)
358{
359 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
360 atomic_set_mask(0x80000000, sw_ptr);
361}
362
d54853ef
MS
363/*
364 * External Time Reference (ETR) code.
365 */
366static int etr_port0_online;
367static int etr_port1_online;
d2fec595 368static int etr_steai_available;
d54853ef
MS
369
370static int __init early_parse_etr(char *p)
371{
372 if (strncmp(p, "off", 3) == 0)
373 etr_port0_online = etr_port1_online = 0;
374 else if (strncmp(p, "port0", 5) == 0)
375 etr_port0_online = 1;
376 else if (strncmp(p, "port1", 5) == 0)
377 etr_port1_online = 1;
378 else if (strncmp(p, "on", 2) == 0)
379 etr_port0_online = etr_port1_online = 1;
380 return 0;
381}
382early_param("etr", early_parse_etr);
383
384enum etr_event {
385 ETR_EVENT_PORT0_CHANGE,
386 ETR_EVENT_PORT1_CHANGE,
387 ETR_EVENT_PORT_ALERT,
388 ETR_EVENT_SYNC_CHECK,
389 ETR_EVENT_SWITCH_LOCAL,
390 ETR_EVENT_UPDATE,
391};
392
d54853ef
MS
393/*
394 * Valid bit combinations of the eacr register are (x = don't care):
395 * e0 e1 dp p0 p1 ea es sl
396 * 0 0 x 0 0 0 0 0 initial, disabled state
397 * 0 0 x 0 1 1 0 0 port 1 online
398 * 0 0 x 1 0 1 0 0 port 0 online
399 * 0 0 x 1 1 1 0 0 both ports online
400 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
401 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
402 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
403 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
404 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
405 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
406 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
407 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
408 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
409 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
410 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
411 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
412 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
413 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
414 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
415 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
416 */
417static struct etr_eacr etr_eacr;
418static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
419static struct etr_aib etr_port0;
420static int etr_port0_uptodate;
421static struct etr_aib etr_port1;
422static int etr_port1_uptodate;
423static unsigned long etr_events;
424static struct timer_list etr_timer;
d54853ef
MS
425
426static void etr_timeout(unsigned long dummy);
ecdcc023
MS
427static void etr_work_fn(struct work_struct *work);
428static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 429
d54853ef
MS
430/*
431 * Reset ETR attachment.
432 */
433static void etr_reset(void)
434{
435 etr_eacr = (struct etr_eacr) {
436 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
437 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
438 .es = 0, .sl = 0 };
d2fec595 439 if (etr_setr(&etr_eacr) == 0) {
d54853ef 440 etr_tolec = get_clock();
d2fec595
MS
441 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
442 } else if (etr_port0_online || etr_port1_online) {
443 printk(KERN_WARNING "Running on non ETR capable "
444 "machine, only local mode available.\n");
445 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
446 }
447}
448
ecdcc023 449static int __init etr_init(void)
d54853ef
MS
450{
451 struct etr_aib aib;
452
d2fec595 453 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 454 return 0;
d54853ef
MS
455 /* Check if this machine has the steai instruction. */
456 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 457 etr_steai_available = 1;
d54853ef 458 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
459 if (etr_port0_online) {
460 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
ecdcc023 461 schedule_work(&etr_work);
d54853ef
MS
462 }
463 if (etr_port1_online) {
464 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
ecdcc023 465 schedule_work(&etr_work);
d54853ef 466 }
ecdcc023 467 return 0;
d54853ef
MS
468}
469
ecdcc023
MS
470arch_initcall(etr_init);
471
d54853ef
MS
472/*
473 * Two sorts of ETR machine checks. The architecture reads:
474 * "When a machine-check niterruption occurs and if a switch-to-local or
475 * ETR-sync-check interrupt request is pending but disabled, this pending
476 * disabled interruption request is indicated and is cleared".
477 * Which means that we can get etr_switch_to_local events from the machine
478 * check handler although the interruption condition is disabled. Lovely..
479 */
480
481/*
482 * Switch to local machine check. This is called when the last usable
483 * ETR port goes inactive. After switch to local the clock is not in sync.
484 */
485void etr_switch_to_local(void)
486{
487 if (!etr_eacr.sl)
488 return;
d2fec595
MS
489 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
490 disable_sync_clock(NULL);
d54853ef 491 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
ecdcc023 492 schedule_work(&etr_work);
d54853ef
MS
493}
494
495/*
496 * ETR sync check machine check. This is called when the ETR OTE and the
497 * local clock OTE are farther apart than the ETR sync check tolerance.
498 * After a ETR sync check the clock is not in sync. The machine check
499 * is broadcasted to all cpus at the same time.
500 */
501void etr_sync_check(void)
502{
503 if (!etr_eacr.es)
504 return;
d2fec595
MS
505 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
506 disable_sync_clock(NULL);
d54853ef 507 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
ecdcc023 508 schedule_work(&etr_work);
d54853ef
MS
509}
510
511/*
d2fec595 512 * ETR timing alert. There are two causes:
d54853ef
MS
513 * 1) port state change, check the usability of the port
514 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
515 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
516 * or ETR-data word 4 (edf4) has changed.
517 */
d2fec595 518static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 519{
d54853ef
MS
520 if (intparm->pc0)
521 /* ETR port 0 state change. */
522 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
523 if (intparm->pc1)
524 /* ETR port 1 state change. */
525 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
526 if (intparm->eai)
527 /*
528 * ETR port alert on either port 0, 1 or both.
529 * Both ports are not up-to-date now.
530 */
531 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
ecdcc023 532 schedule_work(&etr_work);
d54853ef
MS
533}
534
535static void etr_timeout(unsigned long dummy)
536{
537 set_bit(ETR_EVENT_UPDATE, &etr_events);
ecdcc023 538 schedule_work(&etr_work);
d54853ef
MS
539}
540
541/*
542 * Check if the etr mode is pss.
543 */
544static inline int etr_mode_is_pps(struct etr_eacr eacr)
545{
546 return eacr.es && !eacr.sl;
547}
548
549/*
550 * Check if the etr mode is etr.
551 */
552static inline int etr_mode_is_etr(struct etr_eacr eacr)
553{
554 return eacr.es && eacr.sl;
555}
556
557/*
558 * Check if the port can be used for TOD synchronization.
559 * For PPS mode the port has to receive OTEs. For ETR mode
560 * the port has to receive OTEs, the ETR stepping bit has to
561 * be zero and the validity bits for data frame 1, 2, and 3
562 * have to be 1.
563 */
564static int etr_port_valid(struct etr_aib *aib, int port)
565{
566 unsigned int psc;
567
568 /* Check that this port is receiving OTEs. */
569 if (aib->tsp == 0)
570 return 0;
571
572 psc = port ? aib->esw.psc1 : aib->esw.psc0;
573 if (psc == etr_lpsc_pps_mode)
574 return 1;
575 if (psc == etr_lpsc_operational_step)
576 return !aib->esw.y && aib->slsw.v1 &&
577 aib->slsw.v2 && aib->slsw.v3;
578 return 0;
579}
580
581/*
582 * Check if two ports are on the same network.
583 */
584static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
585{
586 // FIXME: any other fields we have to compare?
587 return aib1->edf1.net_id == aib2->edf1.net_id;
588}
589
590/*
591 * Wrapper for etr_stei that converts physical port states
592 * to logical port states to be consistent with the output
593 * of stetr (see etr_psc vs. etr_lpsc).
594 */
595static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
596{
597 BUG_ON(etr_steai(aib, func) != 0);
598 /* Convert port state to logical port state. */
599 if (aib->esw.psc0 == 1)
600 aib->esw.psc0 = 2;
601 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
602 aib->esw.psc0 = 1;
603 if (aib->esw.psc1 == 1)
604 aib->esw.psc1 = 2;
605 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
606 aib->esw.psc1 = 1;
607}
608
609/*
610 * Check if the aib a2 is still connected to the same attachment as
611 * aib a1, the etv values differ by one and a2 is valid.
612 */
613static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
614{
615 int state_a1, state_a2;
616
617 /* Paranoia check: e0/e1 should better be the same. */
618 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
619 a1->esw.eacr.e1 != a2->esw.eacr.e1)
620 return 0;
621
622 /* Still connected to the same etr ? */
623 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
624 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
625 if (state_a1 == etr_lpsc_operational_step) {
626 if (state_a2 != etr_lpsc_operational_step ||
627 a1->edf1.net_id != a2->edf1.net_id ||
628 a1->edf1.etr_id != a2->edf1.etr_id ||
629 a1->edf1.etr_pn != a2->edf1.etr_pn)
630 return 0;
631 } else if (state_a2 != etr_lpsc_pps_mode)
632 return 0;
633
634 /* The ETV value of a2 needs to be ETV of a1 + 1. */
635 if (a1->edf2.etv + 1 != a2->edf2.etv)
636 return 0;
637
638 if (!etr_port_valid(a2, p))
639 return 0;
640
641 return 1;
642}
643
d2fec595 644struct clock_sync_data {
5a62b192
HC
645 int in_sync;
646 unsigned long long fixup_cc;
d2fec595 647};
5a62b192 648
d2fec595 649static void clock_sync_cpu_start(void *dummy)
d54853ef 650{
d2fec595
MS
651 struct clock_sync_data *sync = dummy;
652
653 enable_sync_clock();
d54853ef
MS
654 /*
655 * This looks like a busy wait loop but it isn't. etr_sync_cpus
656 * is called on all other cpus while the TOD clocks is stopped.
657 * __udelay will stop the cpu on an enabled wait psw until the
658 * TOD is running again.
659 */
d2fec595 660 while (sync->in_sync == 0) {
d54853ef 661 __udelay(1);
6c732de2
HC
662 /*
663 * A different cpu changes *in_sync. Therefore use
664 * barrier() to force memory access.
665 */
666 barrier();
667 }
d2fec595 668 if (sync->in_sync != 1)
d54853ef 669 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 670 disable_sync_clock(NULL);
d54853ef
MS
671 /*
672 * This round of TOD syncing is done. Set the clock comparator
673 * to the next tick and let the processor continue.
674 */
d2fec595 675 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
676}
677
d2fec595 678static void clock_sync_cpu_end(void *dummy)
d54853ef
MS
679{
680}
681
682/*
683 * Sync the TOD clock using the port refered to by aibp. This port
684 * has to be enabled and the other port has to be disabled. The
685 * last eacr update has to be more than 1.6 seconds in the past.
686 */
687static int etr_sync_clock(struct etr_aib *aib, int port)
688{
689 struct etr_aib *sync_port;
d2fec595 690 struct clock_sync_data etr_sync;
5a62b192
HC
691 unsigned long long clock, old_clock, delay, delta;
692 int follows;
d54853ef
MS
693 int rc;
694
695 /* Check if the current aib is adjacent to the sync port aib. */
696 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
697 follows = etr_aib_follows(sync_port, aib, port);
698 memcpy(sync_port, aib, sizeof(*aib));
699 if (!follows)
700 return -EAGAIN;
701
702 /*
703 * Catch all other cpus and make them wait until we have
704 * successfully synced the clock. smp_call_function will
705 * return after all other cpus are in etr_sync_cpu_start.
706 */
5a62b192 707 memset(&etr_sync, 0, sizeof(etr_sync));
d54853ef 708 preempt_disable();
1a781a77 709 smp_call_function(clock_sync_cpu_start, &etr_sync, 0);
d54853ef 710 local_irq_disable();
d2fec595 711 enable_sync_clock();
d54853ef
MS
712
713 /* Set clock to next OTE. */
714 __ctl_set_bit(14, 21);
715 __ctl_set_bit(0, 29);
716 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 717 old_clock = get_clock();
d54853ef
MS
718 if (set_clock(clock) == 0) {
719 __udelay(1); /* Wait for the clock to start. */
720 __ctl_clear_bit(0, 29);
721 __ctl_clear_bit(14, 21);
722 etr_stetr(aib);
723 /* Adjust Linux timing variables. */
724 delay = (unsigned long long)
725 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 726 delta = adjust_time(old_clock, clock, delay);
5a62b192
HC
727 etr_sync.fixup_cc = delta;
728 fixup_clock_comparator(delta);
d54853ef
MS
729 /* Verify that the clock is properly set. */
730 if (!etr_aib_follows(sync_port, aib, port)) {
731 /* Didn't work. */
d2fec595 732 disable_sync_clock(NULL);
5a62b192 733 etr_sync.in_sync = -EAGAIN;
d54853ef
MS
734 rc = -EAGAIN;
735 } else {
5a62b192 736 etr_sync.in_sync = 1;
d54853ef
MS
737 rc = 0;
738 }
739 } else {
740 /* Could not set the clock ?!? */
741 __ctl_clear_bit(0, 29);
742 __ctl_clear_bit(14, 21);
d2fec595 743 disable_sync_clock(NULL);
5a62b192 744 etr_sync.in_sync = -EAGAIN;
d54853ef
MS
745 rc = -EAGAIN;
746 }
747 local_irq_enable();
1a781a77 748 smp_call_function(clock_sync_cpu_end, NULL, 0);
d54853ef
MS
749 preempt_enable();
750 return rc;
751}
752
753/*
754 * Handle the immediate effects of the different events.
755 * The port change event is used for online/offline changes.
756 */
757static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
758{
759 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
760 eacr.es = 0;
761 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
762 eacr.es = eacr.sl = 0;
763 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
764 etr_port0_uptodate = etr_port1_uptodate = 0;
765
766 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
767 if (eacr.e0)
768 /*
769 * Port change of an enabled port. We have to
770 * assume that this can have caused an stepping
771 * port switch.
772 */
773 etr_tolec = get_clock();
774 eacr.p0 = etr_port0_online;
775 if (!eacr.p0)
776 eacr.e0 = 0;
777 etr_port0_uptodate = 0;
778 }
779 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
780 if (eacr.e1)
781 /*
782 * Port change of an enabled port. We have to
783 * assume that this can have caused an stepping
784 * port switch.
785 */
786 etr_tolec = get_clock();
787 eacr.p1 = etr_port1_online;
788 if (!eacr.p1)
789 eacr.e1 = 0;
790 etr_port1_uptodate = 0;
791 }
792 clear_bit(ETR_EVENT_UPDATE, &etr_events);
793 return eacr;
794}
795
796/*
797 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
798 * one of the ports needs an update.
799 */
800static void etr_set_tolec_timeout(unsigned long long now)
801{
802 unsigned long micros;
803
804 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
805 (!etr_eacr.p1 || etr_port1_uptodate))
806 return;
807 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
808 micros = (micros > 1600000) ? 0 : 1600000 - micros;
809 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
810}
811
812/*
813 * Set up a time that expires after 1/2 second.
814 */
815static void etr_set_sync_timeout(void)
816{
817 mod_timer(&etr_timer, jiffies + HZ/2);
818}
819
820/*
821 * Update the aib information for one or both ports.
822 */
823static struct etr_eacr etr_handle_update(struct etr_aib *aib,
824 struct etr_eacr eacr)
825{
826 /* With both ports disabled the aib information is useless. */
827 if (!eacr.e0 && !eacr.e1)
828 return eacr;
829
ecdcc023 830 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
831 if (aib->esw.q == 0) {
832 /* Information for port 0 stored. */
833 if (eacr.p0 && !etr_port0_uptodate) {
834 etr_port0 = *aib;
835 if (etr_port0_online)
836 etr_port0_uptodate = 1;
837 }
838 } else {
839 /* Information for port 1 stored. */
840 if (eacr.p1 && !etr_port1_uptodate) {
841 etr_port1 = *aib;
842 if (etr_port0_online)
843 etr_port1_uptodate = 1;
844 }
845 }
846
847 /*
848 * Do not try to get the alternate port aib if the clock
849 * is not in sync yet.
850 */
d2fec595 851 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es)
d54853ef
MS
852 return eacr;
853
854 /*
855 * If steai is available we can get the information about
856 * the other port immediately. If only stetr is available the
857 * data-port bit toggle has to be used.
858 */
d2fec595 859 if (etr_steai_available) {
d54853ef
MS
860 if (eacr.p0 && !etr_port0_uptodate) {
861 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
862 etr_port0_uptodate = 1;
863 }
864 if (eacr.p1 && !etr_port1_uptodate) {
865 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
866 etr_port1_uptodate = 1;
867 }
868 } else {
869 /*
870 * One port was updated above, if the other
871 * port is not uptodate toggle dp bit.
872 */
873 if ((eacr.p0 && !etr_port0_uptodate) ||
874 (eacr.p1 && !etr_port1_uptodate))
875 eacr.dp ^= 1;
876 else
877 eacr.dp = 0;
878 }
879 return eacr;
880}
881
882/*
883 * Write new etr control register if it differs from the current one.
884 * Return 1 if etr_tolec has been updated as well.
885 */
886static void etr_update_eacr(struct etr_eacr eacr)
887{
888 int dp_changed;
889
890 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
891 /* No change, return. */
892 return;
893 /*
894 * The disable of an active port of the change of the data port
895 * bit can/will cause a change in the data port.
896 */
897 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
898 (etr_eacr.dp ^ eacr.dp) != 0;
899 etr_eacr = eacr;
900 etr_setr(&etr_eacr);
901 if (dp_changed)
902 etr_tolec = get_clock();
903}
904
905/*
906 * ETR tasklet. In this function you'll find the main logic. In
907 * particular this is the only function that calls etr_update_eacr(),
908 * it "controls" the etr control register.
909 */
ecdcc023 910static void etr_work_fn(struct work_struct *work)
d54853ef
MS
911{
912 unsigned long long now;
913 struct etr_eacr eacr;
914 struct etr_aib aib;
915 int sync_port;
916
917 /* Create working copy of etr_eacr. */
918 eacr = etr_eacr;
919
920 /* Check for the different events and their immediate effects. */
921 eacr = etr_handle_events(eacr);
922
923 /* Check if ETR is supposed to be active. */
924 eacr.ea = eacr.p0 || eacr.p1;
925 if (!eacr.ea) {
926 /* Both ports offline. Reset everything. */
927 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 928 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
929 del_timer_sync(&etr_timer);
930 etr_update_eacr(eacr);
d2fec595 931 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
932 return;
933 }
934
935 /* Store aib to get the current ETR status word. */
936 BUG_ON(etr_stetr(&aib) != 0);
937 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
938 now = get_clock();
939
940 /*
941 * Update the port information if the last stepping port change
942 * or data port change is older than 1.6 seconds.
943 */
944 if (now >= etr_tolec + (1600000 << 12))
945 eacr = etr_handle_update(&aib, eacr);
946
947 /*
948 * Select ports to enable. The prefered synchronization mode is PPS.
949 * If a port can be enabled depends on a number of things:
950 * 1) The port needs to be online and uptodate. A port is not
951 * disabled just because it is not uptodate, but it is only
952 * enabled if it is uptodate.
953 * 2) The port needs to have the same mode (pps / etr).
954 * 3) The port needs to be usable -> etr_port_valid() == 1
955 * 4) To enable the second port the clock needs to be in sync.
956 * 5) If both ports are useable and are ETR ports, the network id
957 * has to be the same.
958 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
959 */
960 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
961 eacr.sl = 0;
962 eacr.e0 = 1;
963 if (!etr_mode_is_pps(etr_eacr))
964 eacr.es = 0;
965 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
966 eacr.e1 = 0;
967 // FIXME: uptodate checks ?
968 else if (etr_port0_uptodate && etr_port1_uptodate)
969 eacr.e1 = 1;
970 sync_port = (etr_port0_uptodate &&
971 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
972 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
973 eacr.sl = 0;
974 eacr.e0 = 0;
975 eacr.e1 = 1;
976 if (!etr_mode_is_pps(etr_eacr))
977 eacr.es = 0;
978 sync_port = (etr_port1_uptodate &&
979 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
980 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
981 eacr.sl = 1;
982 eacr.e0 = 1;
983 if (!etr_mode_is_etr(etr_eacr))
984 eacr.es = 0;
985 if (!eacr.es || !eacr.p1 ||
986 aib.esw.psc1 != etr_lpsc_operational_alt)
987 eacr.e1 = 0;
988 else if (etr_port0_uptodate && etr_port1_uptodate &&
989 etr_compare_network(&etr_port0, &etr_port1))
990 eacr.e1 = 1;
991 sync_port = (etr_port0_uptodate &&
992 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
993 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
994 eacr.sl = 1;
995 eacr.e0 = 0;
996 eacr.e1 = 1;
997 if (!etr_mode_is_etr(etr_eacr))
998 eacr.es = 0;
999 sync_port = (etr_port1_uptodate &&
1000 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1001 } else {
1002 /* Both ports not usable. */
1003 eacr.es = eacr.sl = 0;
1004 sync_port = -1;
d2fec595 1005 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1006 }
1007
d2fec595
MS
1008 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
1009 eacr.es = 0;
1010
d54853ef
MS
1011 /*
1012 * If the clock is in sync just update the eacr and return.
1013 * If there is no valid sync port wait for a port update.
1014 */
d2fec595
MS
1015 if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) ||
1016 eacr.es || sync_port < 0) {
d54853ef
MS
1017 etr_update_eacr(eacr);
1018 etr_set_tolec_timeout(now);
1019 return;
1020 }
1021
1022 /*
1023 * Prepare control register for clock syncing
1024 * (reset data port bit, set sync check control.
1025 */
1026 eacr.dp = 0;
1027 eacr.es = 1;
1028
1029 /*
1030 * Update eacr and try to synchronize the clock. If the update
1031 * of eacr caused a stepping port switch (or if we have to
1032 * assume that a stepping port switch has occured) or the
1033 * clock syncing failed, reset the sync check control bit
1034 * and set up a timer to try again after 0.5 seconds
1035 */
1036 etr_update_eacr(eacr);
d2fec595 1037 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1038 if (now < etr_tolec + (1600000 << 12) ||
1039 etr_sync_clock(&aib, sync_port) != 0) {
1040 /* Sync failed. Try again in 1/2 second. */
1041 eacr.es = 0;
1042 etr_update_eacr(eacr);
d2fec595 1043 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1044 etr_set_sync_timeout();
1045 } else
1046 etr_set_tolec_timeout(now);
1047}
1048
1049/*
1050 * Sysfs interface functions
1051 */
1052static struct sysdev_class etr_sysclass = {
af5ca3f4 1053 .name = "etr",
d54853ef
MS
1054};
1055
1056static struct sys_device etr_port0_dev = {
1057 .id = 0,
1058 .cls = &etr_sysclass,
1059};
1060
1061static struct sys_device etr_port1_dev = {
1062 .id = 1,
1063 .cls = &etr_sysclass,
1064};
1065
1066/*
1067 * ETR class attributes
1068 */
1069static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
1070{
1071 return sprintf(buf, "%i\n", etr_port0.esw.p);
1072}
1073
1074static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1075
1076static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
1077{
1078 char *mode_str;
1079
1080 if (etr_mode_is_pps(etr_eacr))
1081 mode_str = "pps";
1082 else if (etr_mode_is_etr(etr_eacr))
1083 mode_str = "etr";
1084 else
1085 mode_str = "local";
1086 return sprintf(buf, "%s\n", mode_str);
1087}
1088
1089static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1090
1091/*
1092 * ETR port attributes
1093 */
1094static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1095{
1096 if (dev == &etr_port0_dev)
1097 return etr_port0_online ? &etr_port0 : NULL;
1098 else
1099 return etr_port1_online ? &etr_port1 : NULL;
1100}
1101
4a0b2b4d
AK
1102static ssize_t etr_online_show(struct sys_device *dev,
1103 struct sysdev_attribute *attr,
1104 char *buf)
d54853ef
MS
1105{
1106 unsigned int online;
1107
1108 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1109 return sprintf(buf, "%i\n", online);
1110}
1111
1112static ssize_t etr_online_store(struct sys_device *dev,
4a0b2b4d
AK
1113 struct sysdev_attribute *attr,
1114 const char *buf, size_t count)
d54853ef
MS
1115{
1116 unsigned int value;
1117
1118 value = simple_strtoul(buf, NULL, 0);
1119 if (value != 0 && value != 1)
1120 return -EINVAL;
d2fec595
MS
1121 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1122 return -EOPNOTSUPP;
d54853ef
MS
1123 if (dev == &etr_port0_dev) {
1124 if (etr_port0_online == value)
1125 return count; /* Nothing to do. */
1126 etr_port0_online = value;
1127 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
ecdcc023 1128 schedule_work(&etr_work);
d54853ef
MS
1129 } else {
1130 if (etr_port1_online == value)
1131 return count; /* Nothing to do. */
1132 etr_port1_online = value;
1133 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
ecdcc023 1134 schedule_work(&etr_work);
d54853ef
MS
1135 }
1136 return count;
1137}
1138
1139static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1140
4a0b2b4d
AK
1141static ssize_t etr_stepping_control_show(struct sys_device *dev,
1142 struct sysdev_attribute *attr,
1143 char *buf)
d54853ef
MS
1144{
1145 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1146 etr_eacr.e0 : etr_eacr.e1);
1147}
1148
1149static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1150
4a0b2b4d
AK
1151static ssize_t etr_mode_code_show(struct sys_device *dev,
1152 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1153{
1154 if (!etr_port0_online && !etr_port1_online)
1155 /* Status word is not uptodate if both ports are offline. */
1156 return -ENODATA;
1157 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1158 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1159}
1160
1161static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1162
4a0b2b4d
AK
1163static ssize_t etr_untuned_show(struct sys_device *dev,
1164 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1165{
1166 struct etr_aib *aib = etr_aib_from_dev(dev);
1167
1168 if (!aib || !aib->slsw.v1)
1169 return -ENODATA;
1170 return sprintf(buf, "%i\n", aib->edf1.u);
1171}
1172
1173static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1174
4a0b2b4d
AK
1175static ssize_t etr_network_id_show(struct sys_device *dev,
1176 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1177{
1178 struct etr_aib *aib = etr_aib_from_dev(dev);
1179
1180 if (!aib || !aib->slsw.v1)
1181 return -ENODATA;
1182 return sprintf(buf, "%i\n", aib->edf1.net_id);
1183}
1184
1185static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1186
4a0b2b4d
AK
1187static ssize_t etr_id_show(struct sys_device *dev,
1188 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1189{
1190 struct etr_aib *aib = etr_aib_from_dev(dev);
1191
1192 if (!aib || !aib->slsw.v1)
1193 return -ENODATA;
1194 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1195}
1196
1197static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1198
4a0b2b4d
AK
1199static ssize_t etr_port_number_show(struct sys_device *dev,
1200 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1201{
1202 struct etr_aib *aib = etr_aib_from_dev(dev);
1203
1204 if (!aib || !aib->slsw.v1)
1205 return -ENODATA;
1206 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1207}
1208
1209static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1210
4a0b2b4d
AK
1211static ssize_t etr_coupled_show(struct sys_device *dev,
1212 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1213{
1214 struct etr_aib *aib = etr_aib_from_dev(dev);
1215
1216 if (!aib || !aib->slsw.v3)
1217 return -ENODATA;
1218 return sprintf(buf, "%i\n", aib->edf3.c);
1219}
1220
1221static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1222
4a0b2b4d
AK
1223static ssize_t etr_local_time_show(struct sys_device *dev,
1224 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1225{
1226 struct etr_aib *aib = etr_aib_from_dev(dev);
1227
1228 if (!aib || !aib->slsw.v3)
1229 return -ENODATA;
1230 return sprintf(buf, "%i\n", aib->edf3.blto);
1231}
1232
1233static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1234
4a0b2b4d
AK
1235static ssize_t etr_utc_offset_show(struct sys_device *dev,
1236 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1237{
1238 struct etr_aib *aib = etr_aib_from_dev(dev);
1239
1240 if (!aib || !aib->slsw.v3)
1241 return -ENODATA;
1242 return sprintf(buf, "%i\n", aib->edf3.buo);
1243}
1244
1245static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1246
1247static struct sysdev_attribute *etr_port_attributes[] = {
1248 &attr_online,
1249 &attr_stepping_control,
1250 &attr_state_code,
1251 &attr_untuned,
1252 &attr_network,
1253 &attr_id,
1254 &attr_port,
1255 &attr_coupled,
1256 &attr_local_time,
1257 &attr_utc_offset,
1258 NULL
1259};
1260
1261static int __init etr_register_port(struct sys_device *dev)
1262{
1263 struct sysdev_attribute **attr;
1264 int rc;
1265
1266 rc = sysdev_register(dev);
1267 if (rc)
1268 goto out;
1269 for (attr = etr_port_attributes; *attr; attr++) {
1270 rc = sysdev_create_file(dev, *attr);
1271 if (rc)
1272 goto out_unreg;
1273 }
1274 return 0;
1275out_unreg:
1276 for (; attr >= etr_port_attributes; attr--)
1277 sysdev_remove_file(dev, *attr);
1278 sysdev_unregister(dev);
1279out:
1280 return rc;
1281}
1282
1283static void __init etr_unregister_port(struct sys_device *dev)
1284{
1285 struct sysdev_attribute **attr;
1286
1287 for (attr = etr_port_attributes; *attr; attr++)
1288 sysdev_remove_file(dev, *attr);
1289 sysdev_unregister(dev);
1290}
1291
1292static int __init etr_init_sysfs(void)
1293{
1294 int rc;
1295
1296 rc = sysdev_class_register(&etr_sysclass);
1297 if (rc)
1298 goto out;
1299 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1300 if (rc)
1301 goto out_unreg_class;
1302 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1303 if (rc)
1304 goto out_remove_stepping_port;
1305 rc = etr_register_port(&etr_port0_dev);
1306 if (rc)
1307 goto out_remove_stepping_mode;
1308 rc = etr_register_port(&etr_port1_dev);
1309 if (rc)
1310 goto out_remove_port0;
1311 return 0;
1312
1313out_remove_port0:
1314 etr_unregister_port(&etr_port0_dev);
1315out_remove_stepping_mode:
1316 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1317out_remove_stepping_port:
1318 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1319out_unreg_class:
1320 sysdev_class_unregister(&etr_sysclass);
1321out:
1322 return rc;
1da177e4
LT
1323}
1324
d54853ef 1325device_initcall(etr_init_sysfs);
d2fec595
MS
1326
1327/*
1328 * Server Time Protocol (STP) code.
1329 */
1330static int stp_online;
1331static struct stp_sstpi stp_info;
1332static void *stp_page;
1333
1334static void stp_work_fn(struct work_struct *work);
1335static DECLARE_WORK(stp_work, stp_work_fn);
1336
1337static int __init early_parse_stp(char *p)
1338{
1339 if (strncmp(p, "off", 3) == 0)
1340 stp_online = 0;
1341 else if (strncmp(p, "on", 2) == 0)
1342 stp_online = 1;
1343 return 0;
1344}
1345early_param("stp", early_parse_stp);
1346
1347/*
1348 * Reset STP attachment.
1349 */
8f847003 1350static void __init stp_reset(void)
d2fec595
MS
1351{
1352 int rc;
1353
1354 stp_page = alloc_bootmem_pages(PAGE_SIZE);
1355 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1356 if (rc == 0)
d2fec595
MS
1357 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1358 else if (stp_online) {
1359 printk(KERN_WARNING "Running on non STP capable machine.\n");
1360 free_bootmem((unsigned long) stp_page, PAGE_SIZE);
1361 stp_page = NULL;
1362 stp_online = 0;
1363 }
1364}
1365
1366static int __init stp_init(void)
1367{
1368 if (test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags) && stp_online)
1369 schedule_work(&stp_work);
1370 return 0;
1371}
1372
1373arch_initcall(stp_init);
1374
1375/*
1376 * STP timing alert. There are three causes:
1377 * 1) timing status change
1378 * 2) link availability change
1379 * 3) time control parameter change
1380 * In all three cases we are only interested in the clock source state.
1381 * If a STP clock source is now available use it.
1382 */
1383static void stp_timing_alert(struct stp_irq_parm *intparm)
1384{
1385 if (intparm->tsc || intparm->lac || intparm->tcpc)
1386 schedule_work(&stp_work);
1387}
1388
1389/*
1390 * STP sync check machine check. This is called when the timing state
1391 * changes from the synchronized state to the unsynchronized state.
1392 * After a STP sync check the clock is not in sync. The machine check
1393 * is broadcasted to all cpus at the same time.
1394 */
1395void stp_sync_check(void)
1396{
1397 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1398 return;
1399 disable_sync_clock(NULL);
1400 schedule_work(&stp_work);
1401}
1402
1403/*
1404 * STP island condition machine check. This is called when an attached
1405 * server attempts to communicate over an STP link and the servers
1406 * have matching CTN ids and have a valid stratum-1 configuration
1407 * but the configurations do not match.
1408 */
1409void stp_island_check(void)
1410{
1411 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1412 return;
1413 disable_sync_clock(NULL);
1414 schedule_work(&stp_work);
1415}
1416
1417/*
1418 * STP tasklet. Check for the STP state and take over the clock
1419 * synchronization if the STP clock source is usable.
1420 */
1421static void stp_work_fn(struct work_struct *work)
1422{
1423 struct clock_sync_data stp_sync;
1424 unsigned long long old_clock, delta;
1425 int rc;
1426
1427 if (!stp_online) {
1428 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
1429 return;
1430 }
1431
1432 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1433 if (rc)
1434 return;
1435
1436 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1437 if (rc || stp_info.c == 0)
1438 return;
1439
1440 /*
1441 * Catch all other cpus and make them wait until we have
1442 * successfully synced the clock. smp_call_function will
1443 * return after all other cpus are in clock_sync_cpu_start.
1444 */
1445 memset(&stp_sync, 0, sizeof(stp_sync));
1446 preempt_disable();
f6f88e9b 1447 smp_call_function(clock_sync_cpu_start, &stp_sync, 0);
d2fec595
MS
1448 local_irq_disable();
1449 enable_sync_clock();
1450
1451 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1452 if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
1453 schedule_work(&etr_work);
1454
1455 rc = 0;
1456 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1457 stp_info.todoff[2] || stp_info.todoff[3] ||
1458 stp_info.tmd != 2) {
1459 old_clock = get_clock();
1460 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1461 if (rc == 0) {
1462 delta = adjust_time(old_clock, get_clock(), 0);
1463 fixup_clock_comparator(delta);
1464 rc = chsc_sstpi(stp_page, &stp_info,
1465 sizeof(struct stp_sstpi));
1466 if (rc == 0 && stp_info.tmd != 2)
1467 rc = -EAGAIN;
1468 }
1469 }
1470 if (rc) {
1471 disable_sync_clock(NULL);
1472 stp_sync.in_sync = -EAGAIN;
1473 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1474 if (etr_port0_online || etr_port1_online)
1475 schedule_work(&etr_work);
1476 } else
1477 stp_sync.in_sync = 1;
1478
1479 local_irq_enable();
f6f88e9b 1480 smp_call_function(clock_sync_cpu_end, NULL, 0);
d2fec595
MS
1481 preempt_enable();
1482}
1483
1484/*
1485 * STP class sysfs interface functions
1486 */
1487static struct sysdev_class stp_sysclass = {
1488 .name = "stp",
1489};
1490
1491static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf)
1492{
1493 if (!stp_online)
1494 return -ENODATA;
1495 return sprintf(buf, "%016llx\n",
1496 *(unsigned long long *) stp_info.ctnid);
1497}
1498
1499static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1500
1501static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf)
1502{
1503 if (!stp_online)
1504 return -ENODATA;
1505 return sprintf(buf, "%i\n", stp_info.ctn);
1506}
1507
1508static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1509
1510static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf)
1511{
1512 if (!stp_online || !(stp_info.vbits & 0x2000))
1513 return -ENODATA;
1514 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1515}
1516
1517static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1518
1519static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf)
1520{
1521 if (!stp_online || !(stp_info.vbits & 0x8000))
1522 return -ENODATA;
1523 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1524}
1525
1526static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1527
1528static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf)
1529{
1530 if (!stp_online)
1531 return -ENODATA;
1532 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1533}
1534
1535static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1536
1537static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf)
1538{
1539 if (!stp_online || !(stp_info.vbits & 0x0800))
1540 return -ENODATA;
1541 return sprintf(buf, "%i\n", (int) stp_info.tto);
1542}
1543
1544static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1545
1546static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf)
1547{
1548 if (!stp_online || !(stp_info.vbits & 0x4000))
1549 return -ENODATA;
1550 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1551}
1552
1553static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1554 stp_time_zone_offset_show, NULL);
1555
1556static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf)
1557{
1558 if (!stp_online)
1559 return -ENODATA;
1560 return sprintf(buf, "%i\n", stp_info.tmd);
1561}
1562
1563static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1564
1565static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf)
1566{
1567 if (!stp_online)
1568 return -ENODATA;
1569 return sprintf(buf, "%i\n", stp_info.tst);
1570}
1571
1572static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1573
1574static ssize_t stp_online_show(struct sysdev_class *class, char *buf)
1575{
1576 return sprintf(buf, "%i\n", stp_online);
1577}
1578
1579static ssize_t stp_online_store(struct sysdev_class *class,
1580 const char *buf, size_t count)
1581{
1582 unsigned int value;
1583
1584 value = simple_strtoul(buf, NULL, 0);
1585 if (value != 0 && value != 1)
1586 return -EINVAL;
1587 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1588 return -EOPNOTSUPP;
1589 stp_online = value;
1590 schedule_work(&stp_work);
1591 return count;
1592}
1593
1594/*
1595 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1596 * stp/online but attr_online already exists in this file ..
1597 */
1598static struct sysdev_class_attribute attr_stp_online = {
1599 .attr = { .name = "online", .mode = 0600 },
1600 .show = stp_online_show,
1601 .store = stp_online_store,
1602};
1603
1604static struct sysdev_class_attribute *stp_attributes[] = {
1605 &attr_ctn_id,
1606 &attr_ctn_type,
1607 &attr_dst_offset,
1608 &attr_leap_seconds,
1609 &attr_stp_online,
1610 &attr_stratum,
1611 &attr_time_offset,
1612 &attr_time_zone_offset,
1613 &attr_timing_mode,
1614 &attr_timing_state,
1615 NULL
1616};
1617
1618static int __init stp_init_sysfs(void)
1619{
1620 struct sysdev_class_attribute **attr;
1621 int rc;
1622
1623 rc = sysdev_class_register(&stp_sysclass);
1624 if (rc)
1625 goto out;
1626 for (attr = stp_attributes; *attr; attr++) {
1627 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1628 if (rc)
1629 goto out_unreg;
1630 }
1631 return 0;
1632out_unreg:
1633 for (; attr >= stp_attributes; attr--)
1634 sysdev_class_remove_file(&stp_sysclass, *attr);
1635 sysdev_class_unregister(&stp_sysclass);
1636out:
1637 return rc;
1638}
1639
1640device_initcall(stp_init_sysfs);