Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
27f6b416 | 41 | #include <asm/vtimer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
a806170e | 48 | #include "entry.h" |
1da177e4 | 49 | |
8b646bd7 MS |
50 | enum { |
51 | ec_schedule = 0, | |
52 | ec_call_function, | |
53 | ec_call_function_single, | |
54 | ec_stop_cpu, | |
55 | }; | |
08d07968 | 56 | |
8b646bd7 | 57 | enum { |
08d07968 HC |
58 | CPU_STATE_STANDBY, |
59 | CPU_STATE_CONFIGURED, | |
60 | }; | |
61 | ||
8b646bd7 MS |
62 | struct pcpu { |
63 | struct cpu cpu; | |
8b646bd7 MS |
64 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
65 | unsigned long async_stack; /* async stack for the cpu */ | |
66 | unsigned long panic_stack; /* panic stack for the cpu */ | |
67 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
68 | int state; /* physical cpu state */ | |
50ab9a9a | 69 | int polarization; /* physical polarization */ |
8b646bd7 MS |
70 | u16 address; /* physical cpu address */ |
71 | }; | |
72 | ||
73 | static u8 boot_cpu_type; | |
74 | static u16 boot_cpu_address; | |
75 | static struct pcpu pcpu_devices[NR_CPUS]; | |
76 | ||
50ab9a9a HC |
77 | /* |
78 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
79 | * member of a pcpu data structure within the pcpu_devices arreay. | |
80 | */ | |
dbd70fb4 | 81 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 82 | |
8b646bd7 MS |
83 | /* |
84 | * Signal processor helper functions. | |
85 | */ | |
86 | static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status) | |
87 | { | |
88 | register unsigned int reg1 asm ("1") = parm; | |
89 | int cc; | |
08d07968 | 90 | |
8b646bd7 MS |
91 | asm volatile( |
92 | " sigp %1,%2,0(%3)\n" | |
93 | " ipm %0\n" | |
94 | " srl %0,28\n" | |
95 | : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); | |
96 | if (status && cc == 1) | |
97 | *status = reg1; | |
98 | return cc; | |
99 | } | |
1da177e4 | 100 | |
8b646bd7 | 101 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 102 | { |
8b646bd7 | 103 | int cc; |
5c0b912e | 104 | |
8b646bd7 | 105 | while (1) { |
c5e3acd6 | 106 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 107 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
108 | return cc; |
109 | cpu_relax(); | |
5c0b912e | 110 | } |
5c0b912e HC |
111 | } |
112 | ||
8b646bd7 | 113 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 114 | { |
8b646bd7 MS |
115 | int cc, retry; |
116 | ||
117 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 118 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 119 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
120 | break; |
121 | if (retry >= 3) | |
122 | udelay(10); | |
123 | } | |
124 | return cc; | |
125 | } | |
126 | ||
127 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
128 | { | |
41459d36 | 129 | u32 uninitialized_var(status); |
c5e3acd6 | 130 | |
a9ae32c3 | 131 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 132 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 133 | return 0; |
c5e3acd6 | 134 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
135 | } |
136 | ||
137 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 138 | { |
a9ae32c3 | 139 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 140 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 141 | return 1; |
524b24ad HC |
142 | /* Status stored condition code is equivalent to cpu not running. */ |
143 | return 0; | |
a93b8ec1 HC |
144 | } |
145 | ||
1943f53c | 146 | /* |
8b646bd7 | 147 | * Find struct pcpu by cpu address. |
1943f53c | 148 | */ |
8b646bd7 | 149 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
150 | { |
151 | int cpu; | |
152 | ||
8b646bd7 MS |
153 | for_each_cpu(cpu, mask) |
154 | if (pcpu_devices[cpu].address == address) | |
155 | return pcpu_devices + cpu; | |
156 | return NULL; | |
157 | } | |
158 | ||
159 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
160 | { | |
161 | int order; | |
162 | ||
163 | set_bit(ec_bit, &pcpu->ec_mask); | |
164 | order = pcpu_running(pcpu) ? | |
a9ae32c3 | 165 | SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; |
8b646bd7 MS |
166 | pcpu_sigp_retry(pcpu, order, 0); |
167 | } | |
168 | ||
169 | static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) | |
170 | { | |
171 | struct _lowcore *lc; | |
172 | ||
173 | if (pcpu != &pcpu_devices[0]) { | |
174 | pcpu->lowcore = (struct _lowcore *) | |
175 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
176 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
177 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
178 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
179 | goto out; | |
1943f53c | 180 | } |
8b646bd7 MS |
181 | lc = pcpu->lowcore; |
182 | memcpy(lc, &S390_lowcore, 512); | |
183 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
dc7ee00d MS |
184 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE |
185 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
186 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE | |
187 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
188 | lc->cpu_nr = cpu; |
189 | #ifndef CONFIG_64BIT | |
190 | if (MACHINE_HAS_IEEE) { | |
191 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
192 | if (!lc->extended_save_area_addr) | |
193 | goto out; | |
194 | } | |
195 | #else | |
196 | if (vdso_alloc_per_cpu(lc)) | |
197 | goto out; | |
198 | #endif | |
199 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 200 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
201 | return 0; |
202 | out: | |
203 | if (pcpu != &pcpu_devices[0]) { | |
204 | free_page(pcpu->panic_stack); | |
205 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
206 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
207 | } | |
208 | return -ENOMEM; | |
1943f53c MH |
209 | } |
210 | ||
9d0f46af HC |
211 | #ifdef CONFIG_HOTPLUG_CPU |
212 | ||
8b646bd7 | 213 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 214 | { |
a9ae32c3 | 215 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
216 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
217 | #ifndef CONFIG_64BIT | |
218 | if (MACHINE_HAS_IEEE) { | |
219 | struct _lowcore *lc = pcpu->lowcore; | |
220 | ||
221 | free_page((unsigned long) lc->extended_save_area_addr); | |
222 | lc->extended_save_area_addr = 0; | |
223 | } | |
224 | #else | |
225 | vdso_free_per_cpu(pcpu->lowcore); | |
226 | #endif | |
227 | if (pcpu != &pcpu_devices[0]) { | |
228 | free_page(pcpu->panic_stack); | |
229 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
230 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
231 | } | |
232 | } | |
233 | ||
9d0f46af HC |
234 | #endif /* CONFIG_HOTPLUG_CPU */ |
235 | ||
8b646bd7 MS |
236 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
237 | { | |
238 | struct _lowcore *lc = pcpu->lowcore; | |
239 | ||
240 | atomic_inc(&init_mm.context.attach_count); | |
241 | lc->cpu_nr = cpu; | |
242 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
243 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
244 | lc->machine_flags = S390_lowcore.machine_flags; | |
245 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
246 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
247 | __ctl_store(lc->cregs_save_area, 0, 15); | |
248 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
249 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
250 | MAX_FACILITY_BIT/8); | |
251 | } | |
252 | ||
253 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
254 | { | |
255 | struct _lowcore *lc = pcpu->lowcore; | |
256 | struct thread_info *ti = task_thread_info(tsk); | |
257 | ||
dc7ee00d MS |
258 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
259 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
260 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
261 | lc->current_task = (unsigned long) tsk; | |
262 | lc->user_timer = ti->user_timer; | |
263 | lc->system_timer = ti->system_timer; | |
264 | lc->steal_timer = 0; | |
265 | } | |
266 | ||
267 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
268 | { | |
269 | struct _lowcore *lc = pcpu->lowcore; | |
270 | ||
271 | lc->restart_stack = lc->kernel_stack; | |
272 | lc->restart_fn = (unsigned long) func; | |
273 | lc->restart_data = (unsigned long) data; | |
274 | lc->restart_source = -1UL; | |
a9ae32c3 | 275 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
276 | } |
277 | ||
278 | /* | |
279 | * Call function via PSW restart on pcpu and stop the current cpu. | |
280 | */ | |
281 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
282 | void *data, unsigned long stack) | |
283 | { | |
061da3df | 284 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 285 | unsigned long source_cpu = stap(); |
8b646bd7 MS |
286 | |
287 | __load_psw_mask(psw_kernel_bits); | |
fbe76568 | 288 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
289 | func(data); /* should not return */ |
290 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 291 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 292 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
293 | mem_assign_absolute(lc->restart_stack, stack); |
294 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
295 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
296 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 297 | asm volatile( |
eb546195 | 298 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 299 | " brc 2,0b # busy, try again\n" |
eb546195 | 300 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 301 | " brc 2,1b # busy, try again\n" |
fbe76568 | 302 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
303 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
304 | : "0", "1", "cc"); | |
8b646bd7 MS |
305 | for (;;) ; |
306 | } | |
307 | ||
308 | /* | |
309 | * Call function on an online CPU. | |
310 | */ | |
311 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
312 | { | |
313 | struct pcpu *pcpu; | |
314 | ||
315 | /* Use the current cpu if it is online. */ | |
316 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
317 | if (!pcpu) | |
318 | /* Use the first online cpu. */ | |
319 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
320 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
321 | } | |
322 | ||
323 | /* | |
324 | * Call function on the ipl CPU. | |
325 | */ | |
326 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
327 | { | |
c6da39f2 MH |
328 | pcpu_delegate(&pcpu_devices[0], func, data, |
329 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
330 | } |
331 | ||
332 | int smp_find_processor_id(u16 address) | |
333 | { | |
334 | int cpu; | |
335 | ||
336 | for_each_present_cpu(cpu) | |
337 | if (pcpu_devices[cpu].address == address) | |
338 | return cpu; | |
339 | return -1; | |
2c2df118 HC |
340 | } |
341 | ||
8b646bd7 | 342 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 343 | { |
8b646bd7 MS |
344 | return pcpu_running(pcpu_devices + cpu); |
345 | } | |
346 | ||
347 | void smp_yield(void) | |
348 | { | |
349 | if (MACHINE_HAS_DIAG44) | |
350 | asm volatile("diag 0,0,0x44"); | |
2c2df118 HC |
351 | } |
352 | ||
8b646bd7 | 353 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 354 | { |
8b646bd7 MS |
355 | if (MACHINE_HAS_DIAG9C) |
356 | asm volatile("diag %0,0,0x9c" | |
357 | : : "d" (pcpu_devices[cpu].address)); | |
358 | else if (MACHINE_HAS_DIAG44) | |
359 | asm volatile("diag 0,0,0x44"); | |
360 | } | |
361 | ||
362 | /* | |
363 | * Send cpus emergency shutdown signal. This gives the cpus the | |
364 | * opportunity to complete outstanding interrupts. | |
365 | */ | |
366 | void smp_emergency_stop(cpumask_t *cpumask) | |
367 | { | |
368 | u64 end; | |
369 | int cpu; | |
370 | ||
1aae0560 | 371 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
372 | for_each_cpu(cpu, cpumask) { |
373 | struct pcpu *pcpu = pcpu_devices + cpu; | |
374 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
375 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
376 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 377 | get_tod_clock() < end) |
8b646bd7 MS |
378 | cpu_relax(); |
379 | } | |
1aae0560 | 380 | while (get_tod_clock() < end) { |
8b646bd7 MS |
381 | for_each_cpu(cpu, cpumask) |
382 | if (pcpu_stopped(pcpu_devices + cpu)) | |
383 | cpumask_clear_cpu(cpu, cpumask); | |
384 | if (cpumask_empty(cpumask)) | |
385 | break; | |
85ac7ca5 | 386 | cpu_relax(); |
8b646bd7 | 387 | } |
85ac7ca5 MS |
388 | } |
389 | ||
8b646bd7 MS |
390 | /* |
391 | * Stop all cpus but the current one. | |
392 | */ | |
677d7623 | 393 | void smp_send_stop(void) |
1da177e4 | 394 | { |
85ac7ca5 MS |
395 | cpumask_t cpumask; |
396 | int cpu; | |
1da177e4 | 397 | |
677d7623 | 398 | /* Disable all interrupts/machine checks */ |
b50511e4 | 399 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 400 | trace_hardirqs_off(); |
1da177e4 | 401 | |
3ab121ab | 402 | debug_set_critical(); |
85ac7ca5 MS |
403 | cpumask_copy(&cpumask, cpu_online_mask); |
404 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
405 | ||
8b646bd7 MS |
406 | if (oops_in_progress) |
407 | smp_emergency_stop(&cpumask); | |
1da177e4 | 408 | |
85ac7ca5 MS |
409 | /* stop all processors */ |
410 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 411 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 412 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 413 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
414 | cpu_relax(); |
415 | } | |
416 | } | |
417 | ||
8b646bd7 MS |
418 | /* |
419 | * Stop the current cpu. | |
420 | */ | |
421 | void smp_stop_cpu(void) | |
422 | { | |
a9ae32c3 | 423 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 MS |
424 | for (;;) ; |
425 | } | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * This is the main routine where commands issued by other | |
429 | * cpus are handled. | |
430 | */ | |
9acf73b7 | 431 | static void smp_handle_ext_call(void) |
1da177e4 | 432 | { |
39ce010d | 433 | unsigned long bits; |
1da177e4 | 434 | |
9acf73b7 HC |
435 | /* handle bit signal external calls */ |
436 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
437 | if (test_bit(ec_stop_cpu, &bits)) |
438 | smp_stop_cpu(); | |
184748cc PZ |
439 | if (test_bit(ec_schedule, &bits)) |
440 | scheduler_ipi(); | |
39ce010d | 441 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a | 442 | generic_smp_call_function_interrupt(); |
ca9fc75a HC |
443 | if (test_bit(ec_call_function_single, &bits)) |
444 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 445 | } |
85ac7ca5 | 446 | |
9acf73b7 HC |
447 | static void do_ext_call_interrupt(struct ext_code ext_code, |
448 | unsigned int param32, unsigned long param64) | |
449 | { | |
450 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
451 | smp_handle_ext_call(); | |
1da177e4 LT |
452 | } |
453 | ||
630cd046 | 454 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
455 | { |
456 | int cpu; | |
457 | ||
630cd046 | 458 | for_each_cpu(cpu, mask) |
8b646bd7 | 459 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function); |
ca9fc75a HC |
460 | } |
461 | ||
462 | void arch_send_call_function_single_ipi(int cpu) | |
463 | { | |
8b646bd7 | 464 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
465 | } |
466 | ||
347a8dc3 | 467 | #ifndef CONFIG_64BIT |
1da177e4 LT |
468 | /* |
469 | * this function sends a 'purge tlb' signal to another CPU. | |
470 | */ | |
a806170e | 471 | static void smp_ptlb_callback(void *info) |
1da177e4 | 472 | { |
ba8a9229 | 473 | __tlb_flush_local(); |
1da177e4 LT |
474 | } |
475 | ||
476 | void smp_ptlb_all(void) | |
477 | { | |
15c8b6c1 | 478 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
479 | } |
480 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 481 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
482 | |
483 | /* | |
484 | * this function sends a 'reschedule' IPI to another CPU. | |
485 | * it goes straight through and wastes no time serializing | |
486 | * anything. Worst case is that we lose a reschedule ... | |
487 | */ | |
488 | void smp_send_reschedule(int cpu) | |
489 | { | |
8b646bd7 | 490 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
491 | } |
492 | ||
493 | /* | |
494 | * parameter area for the set/clear control bit callbacks | |
495 | */ | |
94c12cc7 | 496 | struct ec_creg_mask_parms { |
8b646bd7 MS |
497 | unsigned long orval; |
498 | unsigned long andval; | |
499 | int cr; | |
94c12cc7 | 500 | }; |
1da177e4 LT |
501 | |
502 | /* | |
503 | * callback for setting/clearing control bits | |
504 | */ | |
39ce010d HC |
505 | static void smp_ctl_bit_callback(void *info) |
506 | { | |
94c12cc7 | 507 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 508 | unsigned long cregs[16]; |
39ce010d | 509 | |
94c12cc7 | 510 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 511 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 512 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
513 | } |
514 | ||
515 | /* | |
516 | * Set a bit in a control register of all cpus | |
517 | */ | |
94c12cc7 MS |
518 | void smp_ctl_set_bit(int cr, int bit) |
519 | { | |
8b646bd7 | 520 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 521 | |
15c8b6c1 | 522 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 523 | } |
39ce010d | 524 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
525 | |
526 | /* | |
527 | * Clear a bit in a control register of all cpus | |
528 | */ | |
94c12cc7 MS |
529 | void smp_ctl_clear_bit(int cr, int bit) |
530 | { | |
8b646bd7 | 531 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 532 | |
15c8b6c1 | 533 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 534 | } |
39ce010d | 535 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 536 | |
60a0c68d | 537 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 538 | |
8b646bd7 MS |
539 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
540 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
541 | ||
542 | static void __init smp_get_save_area(int cpu, u16 address) | |
411ed322 | 543 | { |
8b646bd7 MS |
544 | void *lc = pcpu_devices[0].lowcore; |
545 | struct save_area *save_area; | |
546 | ||
60a0c68d | 547 | if (is_kdump_kernel()) |
411ed322 | 548 | return; |
8b646bd7 MS |
549 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
550 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
551 | return; | |
285f6722 | 552 | if (cpu >= NR_CPUS) { |
8b646bd7 MS |
553 | pr_warning("CPU %i exceeds the maximum %i and is excluded " |
554 | "from the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 555 | return; |
411ed322 | 556 | } |
8b646bd7 MS |
557 | save_area = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
558 | if (!save_area) | |
559 | panic("could not allocate memory for save area\n"); | |
560 | zfcpdump_save_areas[cpu] = save_area; | |
561 | #ifdef CONFIG_CRASH_DUMP | |
562 | if (address == boot_cpu_address) { | |
563 | /* Copy the registers of the boot cpu. */ | |
564 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
565 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
566 | return; | |
567 | } | |
568 | #endif | |
569 | /* Get the registers of a non-boot cpu. */ | |
a9ae32c3 | 570 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
8b646bd7 | 571 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); |
411ed322 MH |
572 | } |
573 | ||
8b646bd7 | 574 | int smp_store_status(int cpu) |
08d07968 | 575 | { |
8b646bd7 | 576 | struct pcpu *pcpu; |
08d07968 | 577 | |
8b646bd7 | 578 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
579 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
580 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 581 | return -EIO; |
08d07968 HC |
582 | return 0; |
583 | } | |
584 | ||
8b646bd7 | 585 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 586 | |
8b646bd7 | 587 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 588 | |
8b646bd7 | 589 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 590 | |
50ab9a9a HC |
591 | void smp_cpu_set_polarization(int cpu, int val) |
592 | { | |
593 | pcpu_devices[cpu].polarization = val; | |
594 | } | |
595 | ||
596 | int smp_cpu_get_polarization(int cpu) | |
597 | { | |
598 | return pcpu_devices[cpu].polarization; | |
599 | } | |
600 | ||
8b646bd7 | 601 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 602 | { |
8b646bd7 | 603 | static int use_sigp_detection; |
08d07968 | 604 | struct sclp_cpu_info *info; |
8b646bd7 MS |
605 | int address; |
606 | ||
607 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
608 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
609 | use_sigp_detection = 1; | |
610 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
611 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
612 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
613 | continue; |
614 | info->cpu[info->configured].address = address; | |
615 | info->configured++; | |
616 | } | |
617 | info->combined = info->configured; | |
08d07968 | 618 | } |
8b646bd7 | 619 | return info; |
08d07968 HC |
620 | } |
621 | ||
eba61970 | 622 | static int __cpuinit smp_add_present_cpu(int cpu); |
8b646bd7 | 623 | |
eba61970 HC |
624 | static int __cpuinit __smp_rescan_cpus(struct sclp_cpu_info *info, |
625 | int sysfs_add) | |
08d07968 | 626 | { |
8b646bd7 | 627 | struct pcpu *pcpu; |
08d07968 | 628 | cpumask_t avail; |
8b646bd7 | 629 | int cpu, nr, i; |
08d07968 | 630 | |
8b646bd7 | 631 | nr = 0; |
0f1959f5 | 632 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
633 | cpu = cpumask_first(&avail); |
634 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
635 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
636 | continue; | |
637 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
638 | continue; | |
639 | pcpu = pcpu_devices + cpu; | |
640 | pcpu->address = info->cpu[i].address; | |
a4eeea4e | 641 | pcpu->state = (i >= info->configured) ? |
8b646bd7 | 642 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; |
50ab9a9a | 643 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
644 | set_cpu_present(cpu, true); |
645 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
646 | set_cpu_present(cpu, false); | |
647 | else | |
648 | nr++; | |
649 | cpu = cpumask_next(cpu, &avail); | |
650 | } | |
651 | return nr; | |
1da177e4 LT |
652 | } |
653 | ||
48483b32 HC |
654 | static void __init smp_detect_cpus(void) |
655 | { | |
656 | unsigned int cpu, c_cpus, s_cpus; | |
657 | struct sclp_cpu_info *info; | |
48483b32 | 658 | |
8b646bd7 | 659 | info = smp_get_cpu_info(); |
48483b32 HC |
660 | if (!info) |
661 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
662 | if (info->has_cpu_type) { |
663 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
664 | if (info->cpu[cpu].address != boot_cpu_address) |
665 | continue; | |
666 | /* The boot cpu dictates the cpu type. */ | |
667 | boot_cpu_type = info->cpu[cpu].type; | |
668 | break; | |
48483b32 HC |
669 | } |
670 | } | |
8b646bd7 | 671 | c_cpus = s_cpus = 0; |
48483b32 | 672 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 673 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 674 | continue; |
8b646bd7 MS |
675 | if (cpu < info->configured) { |
676 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
677 | c_cpus++; | |
678 | } else | |
48483b32 | 679 | s_cpus++; |
48483b32 | 680 | } |
395d31d4 | 681 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 682 | get_online_cpus(); |
8b646bd7 | 683 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 684 | put_online_cpus(); |
8b646bd7 | 685 | kfree(info); |
48483b32 HC |
686 | } |
687 | ||
1da177e4 | 688 | /* |
39ce010d | 689 | * Activate a secondary processor. |
1da177e4 | 690 | */ |
8b646bd7 | 691 | static void __cpuinit smp_start_secondary(void *cpuvoid) |
1da177e4 | 692 | { |
1aae0560 | 693 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
694 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
695 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
696 | S390_lowcore.restart_data = 0; | |
697 | S390_lowcore.restart_source = -1UL; | |
698 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
699 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
700 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); | |
39ce010d | 701 | cpu_init(); |
5bfb5d69 | 702 | preempt_disable(); |
39ce010d | 703 | init_cpu_timer(); |
39ce010d | 704 | init_cpu_vtimer(); |
29b08d2b | 705 | pfault_init(); |
e545a614 | 706 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 707 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 708 | inc_irq_stat(CPU_RST); |
1da177e4 | 709 | local_irq_enable(); |
52c00659 | 710 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
711 | } |
712 | ||
1da177e4 | 713 | /* Upping and downing of CPUs */ |
8239c25f | 714 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 715 | { |
8b646bd7 MS |
716 | struct pcpu *pcpu; |
717 | int rc; | |
1da177e4 | 718 | |
8b646bd7 MS |
719 | pcpu = pcpu_devices + cpu; |
720 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 721 | return -EIO; |
a9ae32c3 HC |
722 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
723 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 724 | return -EIO; |
e80e7813 | 725 | |
8b646bd7 MS |
726 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
727 | if (rc) | |
728 | return rc; | |
729 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 730 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 731 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
732 | while (!cpu_online(cpu)) |
733 | cpu_relax(); | |
734 | return 0; | |
735 | } | |
736 | ||
48483b32 | 737 | static int __init setup_possible_cpus(char *s) |
255acee7 | 738 | { |
8b646bd7 | 739 | int max, cpu; |
255acee7 | 740 | |
8b646bd7 MS |
741 | if (kstrtoint(s, 0, &max) < 0) |
742 | return 0; | |
88e01285 | 743 | init_cpu_possible(cpumask_of(0)); |
8b646bd7 | 744 | for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++) |
def6cfb7 | 745 | set_cpu_possible(cpu, true); |
37a33026 HC |
746 | return 0; |
747 | } | |
748 | early_param("possible_cpus", setup_possible_cpus); | |
749 | ||
48483b32 HC |
750 | #ifdef CONFIG_HOTPLUG_CPU |
751 | ||
39ce010d | 752 | int __cpu_disable(void) |
1da177e4 | 753 | { |
8b646bd7 | 754 | unsigned long cregs[16]; |
1da177e4 | 755 | |
9acf73b7 HC |
756 | /* Handle possible pending IPIs */ |
757 | smp_handle_ext_call(); | |
8b646bd7 MS |
758 | set_cpu_online(smp_processor_id(), false); |
759 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 760 | pfault_fini(); |
8b646bd7 MS |
761 | /* Disable interrupt sources via control register. */ |
762 | __ctl_store(cregs, 0, 15); | |
763 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
764 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
765 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
766 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
767 | return 0; |
768 | } | |
769 | ||
39ce010d | 770 | void __cpu_die(unsigned int cpu) |
1da177e4 | 771 | { |
8b646bd7 MS |
772 | struct pcpu *pcpu; |
773 | ||
1da177e4 | 774 | /* Wait until target cpu is down */ |
8b646bd7 MS |
775 | pcpu = pcpu_devices + cpu; |
776 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 777 | cpu_relax(); |
8b646bd7 | 778 | pcpu_free_lowcore(pcpu); |
050eef36 | 779 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
780 | } |
781 | ||
b456d94a | 782 | void __noreturn cpu_die(void) |
1da177e4 LT |
783 | { |
784 | idle_task_exit(); | |
a9ae32c3 | 785 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 786 | for (;;) ; |
1da177e4 LT |
787 | } |
788 | ||
255acee7 HC |
789 | #endif /* CONFIG_HOTPLUG_CPU */ |
790 | ||
1da177e4 LT |
791 | void __init smp_prepare_cpus(unsigned int max_cpus) |
792 | { | |
39ce010d HC |
793 | /* request the 0x1201 emergency signal external interrupt */ |
794 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
795 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
796 | /* request the 0x1202 external call external interrupt */ |
797 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
798 | panic("Couldn't request external interrupt 0x1202"); | |
8b646bd7 | 799 | smp_detect_cpus(); |
1da177e4 LT |
800 | } |
801 | ||
ea1f4eec | 802 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 803 | { |
8b646bd7 MS |
804 | struct pcpu *pcpu = pcpu_devices; |
805 | ||
806 | boot_cpu_address = stap(); | |
8b646bd7 MS |
807 | pcpu->state = CPU_STATE_CONFIGURED; |
808 | pcpu->address = boot_cpu_address; | |
809 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
dc7ee00d MS |
810 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE |
811 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
812 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE | |
813 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
1da177e4 | 814 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 815 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
816 | set_cpu_present(0, true); |
817 | set_cpu_online(0, true); | |
1da177e4 LT |
818 | } |
819 | ||
ea1f4eec | 820 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 821 | { |
1da177e4 LT |
822 | } |
823 | ||
02beaccc HC |
824 | void __init smp_setup_processor_id(void) |
825 | { | |
826 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
827 | } |
828 | ||
1da177e4 LT |
829 | /* |
830 | * the frequency of the profiling timer can be changed | |
831 | * by writing a multiplier value into /proc/profile. | |
832 | * | |
833 | * usually you want to run this on all CPUs ;) | |
834 | */ | |
835 | int setup_profiling_timer(unsigned int multiplier) | |
836 | { | |
39ce010d | 837 | return 0; |
1da177e4 LT |
838 | } |
839 | ||
08d07968 | 840 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 841 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 842 | struct device_attribute *attr, char *buf) |
08d07968 HC |
843 | { |
844 | ssize_t count; | |
845 | ||
846 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 847 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
848 | mutex_unlock(&smp_cpu_state_mutex); |
849 | return count; | |
850 | } | |
851 | ||
8a25a2fd | 852 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
853 | struct device_attribute *attr, |
854 | const char *buf, size_t count) | |
08d07968 | 855 | { |
8b646bd7 MS |
856 | struct pcpu *pcpu; |
857 | int cpu, val, rc; | |
08d07968 HC |
858 | char delim; |
859 | ||
860 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
861 | return -EINVAL; | |
862 | if (val != 0 && val != 1) | |
863 | return -EINVAL; | |
9d40d2e3 | 864 | get_online_cpus(); |
0b18d318 | 865 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 866 | rc = -EBUSY; |
2c2df118 | 867 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 868 | cpu = dev->id; |
2c2df118 | 869 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 870 | goto out; |
8b646bd7 | 871 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
872 | rc = 0; |
873 | switch (val) { | |
874 | case 0: | |
8b646bd7 MS |
875 | if (pcpu->state != CPU_STATE_CONFIGURED) |
876 | break; | |
877 | rc = sclp_cpu_deconfigure(pcpu->address); | |
878 | if (rc) | |
879 | break; | |
880 | pcpu->state = CPU_STATE_STANDBY; | |
50ab9a9a | 881 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 882 | topology_expect_change(); |
08d07968 HC |
883 | break; |
884 | case 1: | |
8b646bd7 MS |
885 | if (pcpu->state != CPU_STATE_STANDBY) |
886 | break; | |
887 | rc = sclp_cpu_configure(pcpu->address); | |
888 | if (rc) | |
889 | break; | |
890 | pcpu->state = CPU_STATE_CONFIGURED; | |
50ab9a9a | 891 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 892 | topology_expect_change(); |
08d07968 HC |
893 | break; |
894 | default: | |
895 | break; | |
896 | } | |
897 | out: | |
08d07968 | 898 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 899 | put_online_cpus(); |
08d07968 HC |
900 | return rc ? rc : count; |
901 | } | |
8a25a2fd | 902 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
903 | #endif /* CONFIG_HOTPLUG_CPU */ |
904 | ||
8a25a2fd KS |
905 | static ssize_t show_cpu_address(struct device *dev, |
906 | struct device_attribute *attr, char *buf) | |
08d07968 | 907 | { |
8b646bd7 | 908 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 909 | } |
8a25a2fd | 910 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 911 | |
08d07968 HC |
912 | static struct attribute *cpu_common_attrs[] = { |
913 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 914 | &dev_attr_configure.attr, |
08d07968 | 915 | #endif |
8a25a2fd | 916 | &dev_attr_address.attr, |
08d07968 HC |
917 | NULL, |
918 | }; | |
919 | ||
920 | static struct attribute_group cpu_common_attr_group = { | |
921 | .attrs = cpu_common_attrs, | |
922 | }; | |
1da177e4 | 923 | |
8a25a2fd KS |
924 | static ssize_t show_idle_count(struct device *dev, |
925 | struct device_attribute *attr, char *buf) | |
fae8b22d | 926 | { |
4c1051e3 | 927 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
fae8b22d | 928 | unsigned long long idle_count; |
e98bbaaf | 929 | unsigned int sequence; |
fae8b22d | 930 | |
4c1051e3 MS |
931 | do { |
932 | sequence = ACCESS_ONCE(idle->sequence); | |
933 | idle_count = ACCESS_ONCE(idle->idle_count); | |
27f6b416 | 934 | if (ACCESS_ONCE(idle->clock_idle_enter)) |
4c1051e3 | 935 | idle_count++; |
d4f2a840 | 936 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
fae8b22d HC |
937 | return sprintf(buf, "%llu\n", idle_count); |
938 | } | |
8a25a2fd | 939 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 940 | |
8a25a2fd KS |
941 | static ssize_t show_idle_time(struct device *dev, |
942 | struct device_attribute *attr, char *buf) | |
fae8b22d | 943 | { |
4c1051e3 MS |
944 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
945 | unsigned long long now, idle_time, idle_enter, idle_exit; | |
e98bbaaf | 946 | unsigned int sequence; |
fae8b22d | 947 | |
4c1051e3 | 948 | do { |
1aae0560 | 949 | now = get_tod_clock(); |
4c1051e3 MS |
950 | sequence = ACCESS_ONCE(idle->sequence); |
951 | idle_time = ACCESS_ONCE(idle->idle_time); | |
27f6b416 MS |
952 | idle_enter = ACCESS_ONCE(idle->clock_idle_enter); |
953 | idle_exit = ACCESS_ONCE(idle->clock_idle_exit); | |
d4f2a840 | 954 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
4c1051e3 | 955 | idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0; |
6f430924 | 956 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 957 | } |
8a25a2fd | 958 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 959 | |
08d07968 | 960 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
961 | &dev_attr_idle_count.attr, |
962 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
963 | NULL, |
964 | }; | |
965 | ||
08d07968 HC |
966 | static struct attribute_group cpu_online_attr_group = { |
967 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
968 | }; |
969 | ||
2fc2d1e9 HC |
970 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
971 | unsigned long action, void *hcpu) | |
972 | { | |
973 | unsigned int cpu = (unsigned int)(long)hcpu; | |
8b646bd7 | 974 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 975 | struct device *s = &c->dev; |
d882ba69 | 976 | int err = 0; |
2fc2d1e9 | 977 | |
1c725922 | 978 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 979 | case CPU_ONLINE: |
d882ba69 | 980 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
981 | break; |
982 | case CPU_DEAD: | |
08d07968 | 983 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
984 | break; |
985 | } | |
d882ba69 | 986 | return notifier_from_errno(err); |
2fc2d1e9 HC |
987 | } |
988 | ||
eba61970 | 989 | static int __cpuinit smp_add_present_cpu(int cpu) |
08d07968 | 990 | { |
8b646bd7 | 991 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 992 | struct device *s = &c->dev; |
08d07968 HC |
993 | int rc; |
994 | ||
995 | c->hotpluggable = 1; | |
996 | rc = register_cpu(c, cpu); | |
997 | if (rc) | |
998 | goto out; | |
999 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1000 | if (rc) | |
1001 | goto out_cpu; | |
83a24e32 HC |
1002 | if (cpu_online(cpu)) { |
1003 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1004 | if (rc) | |
1005 | goto out_online; | |
1006 | } | |
1007 | rc = topology_cpu_init(c); | |
1008 | if (rc) | |
1009 | goto out_topology; | |
1010 | return 0; | |
1011 | ||
1012 | out_topology: | |
1013 | if (cpu_online(cpu)) | |
1014 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1015 | out_online: | |
08d07968 HC |
1016 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1017 | out_cpu: | |
1018 | #ifdef CONFIG_HOTPLUG_CPU | |
1019 | unregister_cpu(c); | |
1020 | #endif | |
1021 | out: | |
1022 | return rc; | |
1023 | } | |
1024 | ||
1025 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1026 | |
67060d9c | 1027 | int __ref smp_rescan_cpus(void) |
08d07968 | 1028 | { |
8b646bd7 MS |
1029 | struct sclp_cpu_info *info; |
1030 | int nr; | |
08d07968 | 1031 | |
8b646bd7 MS |
1032 | info = smp_get_cpu_info(); |
1033 | if (!info) | |
1034 | return -ENOMEM; | |
9d40d2e3 | 1035 | get_online_cpus(); |
0b18d318 | 1036 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1037 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1038 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1039 | put_online_cpus(); |
8b646bd7 MS |
1040 | kfree(info); |
1041 | if (nr) | |
c10fde0d | 1042 | topology_schedule_update(); |
8b646bd7 | 1043 | return 0; |
1e489518 HC |
1044 | } |
1045 | ||
8a25a2fd KS |
1046 | static ssize_t __ref rescan_store(struct device *dev, |
1047 | struct device_attribute *attr, | |
c9be0a36 | 1048 | const char *buf, |
1e489518 HC |
1049 | size_t count) |
1050 | { | |
1051 | int rc; | |
1052 | ||
1053 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1054 | return rc ? rc : count; |
1055 | } | |
8a25a2fd | 1056 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1057 | #endif /* CONFIG_HOTPLUG_CPU */ |
1058 | ||
83a24e32 | 1059 | static int __init s390_smp_init(void) |
1da177e4 | 1060 | { |
83a24e32 | 1061 | int cpu, rc; |
2fc2d1e9 | 1062 | |
7755d6b2 | 1063 | hotcpu_notifier(smp_cpu_notify, 0); |
08d07968 | 1064 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1065 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1066 | if (rc) |
1067 | return rc; | |
1068 | #endif | |
1069 | for_each_present_cpu(cpu) { | |
1070 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1071 | if (rc) |
1072 | return rc; | |
1da177e4 LT |
1073 | } |
1074 | return 0; | |
1075 | } | |
83a24e32 | 1076 | subsys_initcall(s390_smp_init); |