[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / s390 / kernel / base.S

/*
 *  arch/s390/kernel/base.S
 *
 *    Copyright IBM Corp. 2006, 2007
 *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
 *		 Michael Holzheu <holzheu@de.ibm.com>
 */

#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/ptrace.h>
#include <asm/sigp.h>

#ifdef CONFIG_64BIT

ENTRY(s390_base_mcck_handler)
	basr	%r13,0
0:	lg	%r15,__LC_PANIC_STACK	# load panic stack
	aghi	%r15,-STACK_FRAME_OVERHEAD
	larl	%r1,s390_base_mcck_handler_fn
	lg	%r1,0(%r1)
	ltgr	%r1,%r1
	jz	1f
	basr	%r14,%r1
1:	la	%r1,4095
	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
	lpswe	__LC_MCK_OLD_PSW

	.section .bss
	.align 8
	.globl	s390_base_mcck_handler_fn
s390_base_mcck_handler_fn:
	.quad	0
	.previous

ENTRY(s390_base_ext_handler)
	stmg	%r0,%r15,__LC_SAVE_AREA_ASYNC
	basr	%r13,0
0:	aghi	%r15,-STACK_FRAME_OVERHEAD
	larl	%r1,s390_base_ext_handler_fn
	lg	%r1,0(%r1)
	ltgr	%r1,%r1
	jz	1f
	basr	%r14,%r1
1:	lmg	%r0,%r15,__LC_SAVE_AREA_ASYNC
	ni	__LC_EXT_OLD_PSW+1,0xfd	# clear wait state bit
	lpswe	__LC_EXT_OLD_PSW

	.section .bss
	.align 8
	.globl s390_base_ext_handler_fn
s390_base_ext_handler_fn:
	.quad	0
	.previous

ENTRY(s390_base_pgm_handler)
	stmg	%r0,%r15,__LC_SAVE_AREA_SYNC
	basr	%r13,0
0:	aghi	%r15,-STACK_FRAME_OVERHEAD
	larl	%r1,s390_base_pgm_handler_fn
	lg	%r1,0(%r1)
	ltgr	%r1,%r1
	jz	1f
	basr	%r14,%r1
	lmg	%r0,%r15,__LC_SAVE_AREA_SYNC
	lpswe	__LC_PGM_OLD_PSW
1:	lpswe	disabled_wait_psw-0b(%r13)

	.align	8
disabled_wait_psw:
	.quad	0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler

	.section .bss
	.align 8
	.globl s390_base_pgm_handler_fn
s390_base_pgm_handler_fn:
	.quad	0
	.previous

#
# Calls diag 308 subcode 1 and continues execution
#
# The following conditions must be ensured before calling this function:
# * Prefix register = 0
# * Lowcore protection is disabled
#
ENTRY(diag308_reset)
	larl	%r4,.Lctlregs		# Save control registers
	stctg	%c0,%c15,0(%r4)
	larl	%r4,.Lfpctl		# Floating point control register
	stfpc	0(%r4)
	larl	%r4,.Lcontinue_psw	# Save PSW flags
	epsw	%r2,%r3
	stm	%r2,%r3,0(%r4)
	larl	%r4,.Lrestart_psw	# Setup restart PSW at absolute 0
	lghi	%r3,0
	lg	%r4,0(%r4)		# Save PSW
	sturg	%r4,%r3			# Use sturg, because of large pages
	lghi	%r1,1
	diag	%r1,%r1,0x308
.Lrestart_part2:
	lhi	%r0,0			# Load r0 with zero
	lhi	%r1,2			# Use mode 2 = ESAME (dump)
	sigp	%r1,%r0,SIGP_SET_ARCHITECTURE	# Switch to ESAME mode
	sam64				# Switch to 64 bit addressing mode
	larl	%r4,.Lctlregs		# Restore control registers
	lctlg	%c0,%c15,0(%r4)
	larl	%r4,.Lfpctl		# Restore floating point ctl register
	lfpc	0(%r4)
	larl	%r4,.Lcontinue_psw	# Restore PSW flags
	lpswe	0(%r4)
.Lcontinue:
	br	%r14
.align 16
.Lrestart_psw:
	.long	0x00080000,0x80000000 + .Lrestart_part2

	.section .data..nosave,"aw",@progbits
.align 8
.Lcontinue_psw:
	.quad	0,.Lcontinue
	.previous

	.section .bss
.align 8
.Lctlregs:
	.rept	16
	.quad	0
	.endr
.Lfpctl:
	.long	0
	.previous

#else /* CONFIG_64BIT */

ENTRY(s390_base_mcck_handler)
	basr	%r13,0
0:	l	%r15,__LC_PANIC_STACK	# load panic stack
	ahi	%r15,-STACK_FRAME_OVERHEAD
	l	%r1,2f-0b(%r13)
	l	%r1,0(%r1)
	ltr	%r1,%r1
	jz	1f
	basr	%r14,%r1
1:	lm	%r0,%r15,__LC_GPREGS_SAVE_AREA
	lpsw	__LC_MCK_OLD_PSW

2:	.long	s390_base_mcck_handler_fn

	.section .bss
	.align 4
	.globl	s390_base_mcck_handler_fn
s390_base_mcck_handler_fn:
	.long	0
	.previous

ENTRY(s390_base_ext_handler)
	stm	%r0,%r15,__LC_SAVE_AREA_ASYNC
	basr	%r13,0
0:	ahi	%r15,-STACK_FRAME_OVERHEAD
	l	%r1,2f-0b(%r13)
	l	%r1,0(%r1)
	ltr	%r1,%r1
	jz	1f
	basr	%r14,%r1
1:	lm	%r0,%r15,__LC_SAVE_AREA_ASYNC
	ni	__LC_EXT_OLD_PSW+1,0xfd	# clear wait state bit
	lpsw	__LC_EXT_OLD_PSW

2:	.long	s390_base_ext_handler_fn

	.section .bss
	.align 4
	.globl	s390_base_ext_handler_fn
s390_base_ext_handler_fn:
	.long	0
	.previous

ENTRY(s390_base_pgm_handler)
	stm	%r0,%r15,__LC_SAVE_AREA_SYNC
	basr	%r13,0
0:	ahi	%r15,-STACK_FRAME_OVERHEAD
	l	%r1,2f-0b(%r13)
	l	%r1,0(%r1)
	ltr	%r1,%r1
	jz	1f
	basr	%r14,%r1
	lm	%r0,%r15,__LC_SAVE_AREA_SYNC
	lpsw	__LC_PGM_OLD_PSW

1:	lpsw	disabled_wait_psw-0b(%r13)

2:	.long	s390_base_pgm_handler_fn

disabled_wait_psw:
	.align	8
	.long	0x000a0000,0x00000000 + s390_base_pgm_handler

	.section .bss
	.align 4
	.globl	s390_base_pgm_handler_fn
s390_base_pgm_handler_fn:
	.long	0
	.previous

#endif /* CONFIG_64BIT */
Commit	Line	Data
ab14de6c HC	1	/*
	2	* arch/s390/kernel/base.S
	3	*
a53c8fab	4	* Copyright IBM Corp. 2006, 2007
ab14de6c HC	5	* Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
	6	* Michael Holzheu <holzheu@de.ibm.com>
	7	*/
	8
144d634a	9	#include <linux/linkage.h>
cbb870c8	10	#include <asm/asm-offsets.h>
ab14de6c	11	#include <asm/ptrace.h>
eb546195	12	#include <asm/sigp.h>
ab14de6c HC	13
	14	#ifdef CONFIG_64BIT
	15
144d634a	16	ENTRY(s390_base_mcck_handler)
ab14de6c HC	17	basr %r13,0
	18	0: lg %r15,__LC_PANIC_STACK # load panic stack
	19	aghi %r15,-STACK_FRAME_OVERHEAD
	20	larl %r1,s390_base_mcck_handler_fn
	21	lg %r1,0(%r1)
	22	ltgr %r1,%r1
	23	jz 1f
	24	basr %r14,%r1
	25	1: la %r1,4095
	26	lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
	27	lpswe __LC_MCK_OLD_PSW
	28
	29	.section .bss
144d634a	30	.align 8
ab14de6c HC	31	.globl s390_base_mcck_handler_fn
	32	s390_base_mcck_handler_fn:
	33	.quad 0
	34	.previous
	35
144d634a	36	ENTRY(s390_base_ext_handler)
c5328901	37	stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
ab14de6c HC	38	basr %r13,0
	39	0: aghi %r15,-STACK_FRAME_OVERHEAD
	40	larl %r1,s390_base_ext_handler_fn
	41	lg %r1,0(%r1)
	42	ltgr %r1,%r1
	43	jz 1f
	44	basr %r14,%r1
c5328901	45	1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
ab14de6c HC	46	ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
	47	lpswe __LC_EXT_OLD_PSW
	48
	49	.section .bss
144d634a	50	.align 8
ab14de6c HC	51	.globl s390_base_ext_handler_fn
	52	s390_base_ext_handler_fn:
	53	.quad 0
	54	.previous
	55
144d634a	56	ENTRY(s390_base_pgm_handler)
c5328901	57	stmg %r0,%r15,__LC_SAVE_AREA_SYNC
ab14de6c HC	58	basr %r13,0
	59	0: aghi %r15,-STACK_FRAME_OVERHEAD
	60	larl %r1,s390_base_pgm_handler_fn
	61	lg %r1,0(%r1)
	62	ltgr %r1,%r1
	63	jz 1f
	64	basr %r14,%r1
c5328901	65	lmg %r0,%r15,__LC_SAVE_AREA_SYNC
ab14de6c HC	66	lpswe __LC_PGM_OLD_PSW
	67	1: lpswe disabled_wait_psw-0b(%r13)
	68
	69	.align 8
	70	disabled_wait_psw:
	71	.quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
	72
	73	.section .bss
144d634a	74	.align 8
ab14de6c HC	75	.globl s390_base_pgm_handler_fn
	76	s390_base_pgm_handler_fn:
	77	.quad 0
	78	.previous
	79
9dc7356e MH	80	#
	81	# Calls diag 308 subcode 1 and continues execution
	82	#
	83	# The following conditions must be ensured before calling this function:
	84	# * Prefix register = 0
	85	# * Lowcore protection is disabled
	86	#
	87	ENTRY(diag308_reset)
	88	larl %r4,.Lctlregs # Save control registers
	89	stctg %c0,%c15,0(%r4)
60a0c68d MH	90	larl %r4,.Lfpctl # Floating point control register
60a0c68d MH	91	stfpc 0(%r4)
fa7c0043 MH	92	larl %r4,.Lcontinue_psw # Save PSW flags
	93	epsw %r2,%r3
	94	stm %r2,%r3,0(%r4)
9dc7356e MH	95	larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
	96	lghi %r3,0
	97	lg %r4,0(%r4) # Save PSW
	98	sturg %r4,%r3 # Use sturg, because of large pages
	99	lghi %r1,1
	100	diag %r1,%r1,0x308
	101	.Lrestart_part2:
	102	lhi %r0,0 # Load r0 with zero
	103	lhi %r1,2 # Use mode 2 = ESAME (dump)
eb546195	104	sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
9dc7356e MH	105	sam64 # Switch to 64 bit addressing mode
	106	larl %r4,.Lctlregs # Restore control registers
	107	lctlg %c0,%c15,0(%r4)
60a0c68d MH	108	larl %r4,.Lfpctl # Restore floating point ctl register
60a0c68d MH	109	lfpc 0(%r4)
fa7c0043 MH	110	larl %r4,.Lcontinue_psw # Restore PSW flags
	111	lpswe 0(%r4)
	112	.Lcontinue:
9dc7356e MH	113	br %r14
	114	.align 16
	115	.Lrestart_psw:
	116	.long 0x00080000,0x80000000 + .Lrestart_part2
	117
fa7c0043 MH	118	.section .data..nosave,"aw",@progbits
	119	.align 8
	120	.Lcontinue_psw:
	121	.quad 0,.Lcontinue
	122	.previous
	123
9dc7356e MH	124	.section .bss
	125	.align 8
	126	.Lctlregs:
	127	.rept 16
	128	.quad 0
	129	.endr
60a0c68d MH	130	.Lfpctl:
60a0c68d MH	131	.long 0
9dc7356e MH	132	.previous
9dc7356e MH	133
ab14de6c HC	134	#else /* CONFIG_64BIT */
ab14de6c HC	135
144d634a	136	ENTRY(s390_base_mcck_handler)
ab14de6c HC	137	basr %r13,0
	138	0: l %r15,__LC_PANIC_STACK # load panic stack
	139	ahi %r15,-STACK_FRAME_OVERHEAD
	140	l %r1,2f-0b(%r13)
	141	l %r1,0(%r1)
	142	ltr %r1,%r1
	143	jz 1f
	144	basr %r14,%r1
	145	1: lm %r0,%r15,__LC_GPREGS_SAVE_AREA
	146	lpsw __LC_MCK_OLD_PSW
	147
	148	2: .long s390_base_mcck_handler_fn
	149
	150	.section .bss
144d634a	151	.align 4
ab14de6c HC	152	.globl s390_base_mcck_handler_fn
	153	s390_base_mcck_handler_fn:
	154	.long 0
	155	.previous
	156
144d634a	157	ENTRY(s390_base_ext_handler)
c5328901	158	stm %r0,%r15,__LC_SAVE_AREA_ASYNC
ab14de6c HC	159	basr %r13,0
	160	0: ahi %r15,-STACK_FRAME_OVERHEAD
	161	l %r1,2f-0b(%r13)
	162	l %r1,0(%r1)
	163	ltr %r1,%r1
	164	jz 1f
	165	basr %r14,%r1
c5328901	166	1: lm %r0,%r15,__LC_SAVE_AREA_ASYNC
ab14de6c HC	167	ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
	168	lpsw __LC_EXT_OLD_PSW
	169
	170	2: .long s390_base_ext_handler_fn
	171
	172	.section .bss
144d634a	173	.align 4
ab14de6c HC	174	.globl s390_base_ext_handler_fn
	175	s390_base_ext_handler_fn:
	176	.long 0
	177	.previous
	178
144d634a	179	ENTRY(s390_base_pgm_handler)
c5328901	180	stm %r0,%r15,__LC_SAVE_AREA_SYNC
ab14de6c HC	181	basr %r13,0
	182	0: ahi %r15,-STACK_FRAME_OVERHEAD
	183	l %r1,2f-0b(%r13)
	184	l %r1,0(%r1)
	185	ltr %r1,%r1
	186	jz 1f
	187	basr %r14,%r1
c5328901	188	lm %r0,%r15,__LC_SAVE_AREA_SYNC
ab14de6c HC	189	lpsw __LC_PGM_OLD_PSW
	190
	191	1: lpsw disabled_wait_psw-0b(%r13)
	192
	193	2: .long s390_base_pgm_handler_fn
	194
	195	disabled_wait_psw:
	196	.align 8
	197	.long 0x000a0000,0x00000000 + s390_base_pgm_handler
	198
	199	.section .bss
144d634a	200	.align 4
ab14de6c HC	201	.globl s390_base_pgm_handler_fn
	202	s390_base_pgm_handler_fn:
	203	.long 0
	204	.previous
	205
	206	#endif /* CONFIG_64BIT */