projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* Board information for the SBCPowerQUICCII, which should be generic for |
| 2 | * all 8260 boards. The IMMR is now given to us so the hard define | |
| 3 | * will soon be removed. All of the clock values are computed from | |
| 4 | * the configuration SCMR and the Power-On-Reset word. | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __PPC_SBC82xx_H__ | |
| 8 | #define __PPC_SBC82xx_H__ | |
| 9 | ||
| 10 | #include <asm/ppcboot.h> | |
| 11 | ||
| 12 | #define CPM_MAP_ADDR 0xf0000000 | |
| 13 | ||
| 14 | #define SBC82xx_TODC_NVRAM_ADDR 0xd0000000 | |
| 15 | ||
| 16 | #define SBC82xx_MACADDR_NVRAM_FCC1 0x220000c9 /* JP6B */ | |
| 17 | #define SBC82xx_MACADDR_NVRAM_SCC1 0x220000cf /* JP6A */ | |
| 18 | #define SBC82xx_MACADDR_NVRAM_FCC2 0x220000d5 /* JP7A */ | |
| 19 | #define SBC82xx_MACADDR_NVRAM_FCC3 0x220000db /* JP7B */ | |
| 20 | ||
| 21 | /* For our show_cpuinfo hooks. */ | |
| 22 | #define CPUINFO_VENDOR "Wind River" | |
| 23 | #define CPUINFO_MACHINE "SBC PowerQUICC II" | |
| 24 | ||
| 25 | #define BOOTROM_RESTART_ADDR ((uint)0x40000104) | |
| 26 | ||
| 27 | #define SBC82xx_PC_IRQA (NR_SIU_INTS+0) | |
| 28 | #define SBC82xx_PC_IRQB (NR_SIU_INTS+1) | |
| 29 | #define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2) | |
| 30 | #define SBC82xx_ATM_IRQ (NR_SIU_INTS+3) | |
| 31 | #define SBC82xx_PIRQA (NR_SIU_INTS+4) | |
| 32 | #define SBC82xx_PIRQB (NR_SIU_INTS+5) | |
| 33 | #define SBC82xx_PIRQC (NR_SIU_INTS+6) | |
| 34 | #define SBC82xx_PIRQD (NR_SIU_INTS+7) | |
| 35 | ||
| 36 | #endif /* __PPC_SBC82xx_H__ */ |