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1da177e4 LT |
1 | /* |
2 | * arch/ppc/platform/85xx/sbc85xx.c | |
3 | * | |
4 | * WindRiver PowerQUICC III SBC85xx board common routines | |
5 | * | |
6 | * Copyright 2002, 2003 Motorola Inc. | |
7 | * Copyright 2004 Red Hat, Inc. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/config.h> | |
16 | #include <linux/stddef.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/kdev_t.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/console.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/seq_file.h> | |
28 | #include <linux/serial.h> | |
29 | #include <linux/module.h> | |
30 | ||
31 | #include <asm/system.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/time.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/machdep.h> | |
38 | #include <asm/prom.h> | |
39 | #include <asm/open_pic.h> | |
40 | #include <asm/bootinfo.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/mpc85xx.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/immap_85xx.h> | |
45 | #include <asm/ppc_sys.h> | |
46 | ||
47 | #include <mm/mmu_decl.h> | |
48 | ||
49 | #include <platforms/85xx/sbc85xx.h> | |
50 | ||
51 | unsigned char __res[sizeof (bd_t)]; | |
52 | ||
53 | #ifndef CONFIG_PCI | |
54 | unsigned long isa_io_base = 0; | |
55 | unsigned long isa_mem_base = 0; | |
56 | unsigned long pci_dram_offset = 0; | |
57 | #endif | |
58 | ||
59 | extern unsigned long total_memory; /* in mm/init */ | |
60 | ||
61 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ | |
62 | ||
63 | static u_char sbc8560_openpic_initsenses[] __initdata = { | |
64 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ | |
65 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */ | |
66 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */ | |
67 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */ | |
68 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */ | |
69 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */ | |
70 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */ | |
71 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */ | |
72 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */ | |
73 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */ | |
74 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */ | |
75 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */ | |
76 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */ | |
77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */ | |
78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */ | |
79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */ | |
80 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */ | |
81 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */ | |
82 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */ | |
83 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */ | |
84 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */ | |
85 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */ | |
86 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */ | |
87 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */ | |
88 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */ | |
89 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */ | |
90 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */ | |
91 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */ | |
92 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */ | |
93 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */ | |
94 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */ | |
95 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */ | |
96 | 0x0, /* External 0: */ | |
97 | 0x0, /* External 1: */ | |
98 | #if defined(CONFIG_PCI) | |
99 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 0 */ | |
100 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 1 */ | |
101 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 2 */ | |
102 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PCI slot 3 */ | |
103 | #else | |
104 | 0x0, /* External 2: */ | |
105 | 0x0, /* External 3: */ | |
106 | 0x0, /* External 4: */ | |
107 | 0x0, /* External 5: */ | |
108 | #endif | |
109 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 6: PHY */ | |
110 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */ | |
111 | 0x0, /* External 8: */ | |
112 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: PHY */ | |
113 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 10: PHY */ | |
114 | 0x0, /* External 11: */ | |
115 | }; | |
116 | ||
117 | /* ************************************************************************ */ | |
118 | int | |
119 | sbc8560_show_cpuinfo(struct seq_file *m) | |
120 | { | |
121 | uint pvid, svid, phid1; | |
122 | uint memsize = total_memory; | |
123 | bd_t *binfo = (bd_t *) __res; | |
124 | unsigned int freq; | |
125 | ||
126 | /* get the core frequency */ | |
127 | freq = binfo->bi_intfreq; | |
128 | ||
129 | pvid = mfspr(SPRN_PVR); | |
130 | svid = mfspr(SPRN_SVR); | |
131 | ||
132 | seq_printf(m, "Vendor\t\t: Wind River\n"); | |
133 | seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name); | |
134 | seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); | |
135 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); | |
136 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
137 | ||
138 | /* Display cpu Pll setting */ | |
139 | phid1 = mfspr(SPRN_HID1); | |
140 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | |
141 | ||
142 | /* Display the amount of memory */ | |
143 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | void __init | |
149 | sbc8560_init_IRQ(void) | |
150 | { | |
151 | bd_t *binfo = (bd_t *) __res; | |
152 | /* Determine the Physical Address of the OpenPIC regs */ | |
153 | phys_addr_t OpenPIC_PAddr = | |
154 | binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; | |
155 | OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); | |
156 | OpenPIC_InitSenses = sbc8560_openpic_initsenses; | |
157 | OpenPIC_NumInitSenses = sizeof (sbc8560_openpic_initsenses); | |
158 | ||
159 | /* Skip reserved space and internal sources */ | |
160 | openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); | |
161 | /* Map PIC IRQs 0-11 */ | |
162 | openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); | |
163 | ||
164 | /* we let openpic interrupts starting from an offset, to | |
165 | * leave space for cascading interrupts underneath. | |
166 | */ | |
167 | openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); | |
168 | ||
169 | return; | |
170 | } | |
171 | ||
172 | /* | |
173 | * interrupt routing | |
174 | */ | |
175 | ||
176 | #ifdef CONFIG_PCI | |
177 | int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, | |
178 | unsigned char pin) | |
179 | { | |
180 | static char pci_irq_table[][4] = | |
181 | /* | |
182 | * PCI IDSEL/INTPIN->INTLINE | |
183 | * A B C D | |
184 | */ | |
185 | { | |
186 | {PIRQA, PIRQB, PIRQC, PIRQD}, | |
187 | {PIRQD, PIRQA, PIRQB, PIRQC}, | |
188 | {PIRQC, PIRQD, PIRQA, PIRQB}, | |
189 | {PIRQB, PIRQC, PIRQD, PIRQA}, | |
190 | }; | |
191 | ||
192 | const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4; | |
193 | return PCI_IRQ_TABLE_LOOKUP; | |
194 | } | |
195 | ||
196 | int mpc85xx_exclude_device(u_char bus, u_char devfn) | |
197 | { | |
198 | if (bus == 0 && PCI_SLOT(devfn) == 0) | |
199 | return PCIBIOS_DEVICE_NOT_FOUND; | |
200 | else | |
201 | return PCIBIOS_SUCCESSFUL; | |
202 | } | |
203 | #endif /* CONFIG_PCI */ |