[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / sysdev / uic.c

/*
 * arch/powerpc/sysdev/uic.c
 *
 * IBM PowerPC 4xx Universal Interrupt Controller
 *
 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/sysdev.h>
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/dcr.h>

#define NR_UIC_INTS	32

#define UIC_SR		0x0
#define UIC_ER		0x2
#define UIC_CR		0x3
#define UIC_PR		0x4
#define UIC_TR		0x5
#define UIC_MSR		0x6
#define UIC_VR		0x7
#define UIC_VCR		0x8

#define uic_irq_to_hw(virq)	(irq_map[virq].hwirq)

struct uic *primary_uic;

struct uic {
	int index;
	int dcrbase;

	spinlock_t lock;

	/* The remapper for this UIC */
	struct irq_host	*irqhost;
};

static void uic_unmask_irq(unsigned int virq)
{
	struct irq_desc *desc = irq_to_desc(virq);
	struct uic *uic = get_irq_chip_data(virq);
	unsigned int src = uic_irq_to_hw(virq);
	unsigned long flags;
	u32 er, sr;

	sr = 1 << (31-src);
	spin_lock_irqsave(&uic->lock, flags);
	/* ack level-triggered interrupts here */
	if (desc->status & IRQ_LEVEL)
		mtdcr(uic->dcrbase + UIC_SR, sr);
	er = mfdcr(uic->dcrbase + UIC_ER);
	er |= sr;
	mtdcr(uic->dcrbase + UIC_ER, er);
	spin_unlock_irqrestore(&uic->lock, flags);
}

static void uic_mask_irq(unsigned int virq)
{
	struct uic *uic = get_irq_chip_data(virq);
	unsigned int src = uic_irq_to_hw(virq);
	unsigned long flags;
	u32 er;

	spin_lock_irqsave(&uic->lock, flags);
	er = mfdcr(uic->dcrbase + UIC_ER);
	er &= ~(1 << (31 - src));
	mtdcr(uic->dcrbase + UIC_ER, er);
	spin_unlock_irqrestore(&uic->lock, flags);
}

static void uic_ack_irq(unsigned int virq)
{
	struct uic *uic = get_irq_chip_data(virq);
	unsigned int src = uic_irq_to_hw(virq);
	unsigned long flags;

	spin_lock_irqsave(&uic->lock, flags);
	mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
	spin_unlock_irqrestore(&uic->lock, flags);
}

static void uic_mask_ack_irq(unsigned int virq)
{
	struct irq_desc *desc = irq_to_desc(virq);
	struct uic *uic = get_irq_chip_data(virq);
	unsigned int src = uic_irq_to_hw(virq);
	unsigned long flags;
	u32 er, sr;

	sr = 1 << (31-src);
	spin_lock_irqsave(&uic->lock, flags);
	er = mfdcr(uic->dcrbase + UIC_ER);
	er &= ~sr;
	mtdcr(uic->dcrbase + UIC_ER, er);
 	/* On the UIC, acking (i.e. clearing the SR bit)
	 * a level irq will have no effect if the interrupt
	 * is still asserted by the device, even if
	 * the interrupt is already masked. Therefore
	 * we only ack the egde interrupts here, while
	 * level interrupts are ack'ed after the actual
	 * isr call in the uic_unmask_irq()
	 */
	if (!(desc->status & IRQ_LEVEL))
		mtdcr(uic->dcrbase + UIC_SR, sr);
	spin_unlock_irqrestore(&uic->lock, flags);
}

static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
{
	struct uic *uic = get_irq_chip_data(virq);
	unsigned int src = uic_irq_to_hw(virq);
	struct irq_desc *desc = irq_to_desc(virq);
	unsigned long flags;
	int trigger, polarity;
	u32 tr, pr, mask;

	switch (flow_type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_NONE:
		uic_mask_irq(virq);
		return 0;

	case IRQ_TYPE_EDGE_RISING:
		trigger = 1; polarity = 1;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		trigger = 1; polarity = 0;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		trigger = 0; polarity = 1;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		trigger = 0; polarity = 0;
		break;
	default:
		return -EINVAL;
	}

	mask = ~(1 << (31 - src));

	spin_lock_irqsave(&uic->lock, flags);
	tr = mfdcr(uic->dcrbase + UIC_TR);
	pr = mfdcr(uic->dcrbase + UIC_PR);
	tr = (tr & mask) | (trigger << (31-src));
	pr = (pr & mask) | (polarity << (31-src));

	mtdcr(uic->dcrbase + UIC_PR, pr);
	mtdcr(uic->dcrbase + UIC_TR, tr);

	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
	if (!trigger)
		desc->status |= IRQ_LEVEL;

	spin_unlock_irqrestore(&uic->lock, flags);

	return 0;
}

static struct irq_chip uic_irq_chip = {
	.name		= " UIC  ",
	.unmask		= uic_unmask_irq,
	.mask		= uic_mask_irq,
 	.mask_ack	= uic_mask_ack_irq,
	.ack		= uic_ack_irq,
	.set_type	= uic_set_irq_type,
};

static int uic_host_map(struct irq_host *h, unsigned int virq,
			irq_hw_number_t hw)
{
	struct uic *uic = h->host_data;

	set_irq_chip_data(virq, uic);
	/* Despite the name, handle_level_irq() works for both level
	 * and edge irqs on UIC.  FIXME: check this is correct */
	set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);

	/* Set default irq type */
	set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
			  const u32 *intspec, unsigned int intsize,
			  irq_hw_number_t *out_hwirq, unsigned int *out_type)

{
	/* UIC intspecs must have 2 cells */
	BUG_ON(intsize != 2);
	*out_hwirq = intspec[0];
	*out_type = intspec[1];
	return 0;
}

static struct irq_host_ops uic_host_ops = {
	.map	= uic_host_map,
	.xlate	= uic_host_xlate,
};

void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
	struct uic *uic = get_irq_data(virq);
	u32 msr;
	int src;
	int subvirq;

	raw_spin_lock(&desc->lock);
	if (desc->status & IRQ_LEVEL)
		desc->chip->mask(virq);
	else
		desc->chip->mask_ack(virq);
	raw_spin_unlock(&desc->lock);

	msr = mfdcr(uic->dcrbase + UIC_MSR);
	if (!msr) /* spurious interrupt */
		goto uic_irq_ret;

	src = 32 - ffs(msr);

	subvirq = irq_linear_revmap(uic->irqhost, src);
	generic_handle_irq(subvirq);

uic_irq_ret:
	raw_spin_lock(&desc->lock);
	if (desc->status & IRQ_LEVEL)
		desc->chip->ack(virq);
	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
		desc->chip->unmask(virq);
	raw_spin_unlock(&desc->lock);
}

static struct uic * __init uic_init_one(struct device_node *node)
{
	struct uic *uic;
	const u32 *indexp, *dcrreg;
	int len;

	BUG_ON(! of_device_is_compatible(node, "ibm,uic"));

	uic = kzalloc(sizeof(*uic), GFP_KERNEL);
	if (! uic)
		return NULL; /* FIXME: panic? */

	spin_lock_init(&uic->lock);
	indexp = of_get_property(node, "cell-index", &len);
	if (!indexp || (len != sizeof(u32))) {
		printk(KERN_ERR "uic: Device node %s has missing or invalid "
		       "cell-index property\n", node->full_name);
		return NULL;
	}
	uic->index = *indexp;

	dcrreg = of_get_property(node, "dcr-reg", &len);
	if (!dcrreg || (len != 2*sizeof(u32))) {
		printk(KERN_ERR "uic: Device node %s has missing or invalid "
		       "dcr-reg property\n", node->full_name);
		return NULL;
	}
	uic->dcrbase = *dcrreg;

	uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
				      NR_UIC_INTS, &uic_host_ops, -1);
	if (! uic->irqhost)
		return NULL; /* FIXME: panic? */

	uic->irqhost->host_data = uic;

	/* Start with all interrupts disabled, level and non-critical */
	mtdcr(uic->dcrbase + UIC_ER, 0);
	mtdcr(uic->dcrbase + UIC_CR, 0);
	mtdcr(uic->dcrbase + UIC_TR, 0);
	/* Clear any pending interrupts, in case the firmware left some */
	mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);

	printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
		NR_UIC_INTS, uic->dcrbase);

	return uic;
}

void __init uic_init_tree(void)
{
	struct device_node *np;
	struct uic *uic;
	const u32 *interrupts;

	/* First locate and initialize the top-level UIC */
	for_each_compatible_node(np, NULL, "ibm,uic") {
		interrupts = of_get_property(np, "interrupts", NULL);
		if (!interrupts)
			break;
	}

	BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
		      * top-level interrupt controller */
	primary_uic = uic_init_one(np);
	if (!primary_uic)
		panic("Unable to initialize primary UIC %s\n", np->full_name);

	irq_set_default_host(primary_uic->irqhost);
	of_node_put(np);

	/* The scan again for cascaded UICs */
	for_each_compatible_node(np, NULL, "ibm,uic") {
		interrupts = of_get_property(np, "interrupts", NULL);
		if (interrupts) {
			/* Secondary UIC */
			int cascade_virq;

			uic = uic_init_one(np);
			if (! uic)
				panic("Unable to initialize a secondary UIC %s\n",
				      np->full_name);

			cascade_virq = irq_of_parse_and_map(np, 0);

			set_irq_data(cascade_virq, uic);
			set_irq_chained_handler(cascade_virq, uic_irq_cascade);

			/* FIXME: setup critical cascade?? */
		}
	}
}

/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
unsigned int uic_get_irq(void)
{
	u32 msr;
	int src;

	BUG_ON(! primary_uic);

	msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
	src = 32 - ffs(msr);

	return irq_linear_revmap(primary_uic->irqhost, src);
}
Commit	Line	Data
e58923ed DG	1	/*
	2	* arch/powerpc/sysdev/uic.c
	3	*
	4	* IBM PowerPC 4xx Universal Interrupt Controller
	5	*
	6	* Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/errno.h>
	16	#include <linux/reboot.h>
	17	#include <linux/slab.h>
	18	#include <linux/stddef.h>
	19	#include <linux/sched.h>
	20	#include <linux/signal.h>
	21	#include <linux/sysdev.h>
	22	#include <linux/device.h>
	23	#include <linux/bootmem.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/irq.h>
	26	#include <linux/interrupt.h>
868afce2	27	#include <linux/kernel_stat.h>
e58923ed DG	28	#include <asm/irq.h>
	29	#include <asm/io.h>
	30	#include <asm/prom.h>
	31	#include <asm/dcr.h>
	32
	33	#define NR_UIC_INTS 32
	34
	35	#define UIC_SR 0x0
	36	#define UIC_ER 0x2
	37	#define UIC_CR 0x3
	38	#define UIC_PR 0x4
	39	#define UIC_TR 0x5
	40	#define UIC_MSR 0x6
	41	#define UIC_VR 0x7
	42	#define UIC_VCR 0x8
	43
	44	#define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
	45
	46	struct uic *primary_uic;
	47
	48	struct uic {
	49	int index;
	50	int dcrbase;
	51
	52	spinlock_t lock;
	53
	54	/* The remapper for this UIC */
	55	struct irq_host *irqhost;
e58923ed DG	56	};
	57
	58	static void uic_unmask_irq(unsigned int virq)
	59	{
6cff46f4	60	struct irq_desc *desc = irq_to_desc(virq);
e58923ed DG	61	struct uic *uic = get_irq_chip_data(virq);
	62	unsigned int src = uic_irq_to_hw(virq);
	63	unsigned long flags;
c8090563	64	u32 er, sr;
e58923ed	65
c8090563	66	sr = 1 << (31-src);
e58923ed	67	spin_lock_irqsave(&uic->lock, flags);
c8090563 VB	68	/* ack level-triggered interrupts here */
	69	if (desc->status & IRQ_LEVEL)
	70	mtdcr(uic->dcrbase + UIC_SR, sr);
e58923ed	71	er = mfdcr(uic->dcrbase + UIC_ER);
c8090563	72	er \|= sr;
e58923ed DG	73	mtdcr(uic->dcrbase + UIC_ER, er);
	74	spin_unlock_irqrestore(&uic->lock, flags);
	75	}
	76
	77	static void uic_mask_irq(unsigned int virq)
	78	{
	79	struct uic *uic = get_irq_chip_data(virq);
	80	unsigned int src = uic_irq_to_hw(virq);
	81	unsigned long flags;
	82	u32 er;
	83
	84	spin_lock_irqsave(&uic->lock, flags);
	85	er = mfdcr(uic->dcrbase + UIC_ER);
	86	er &= ~(1 << (31 - src));
	87	mtdcr(uic->dcrbase + UIC_ER, er);
	88	spin_unlock_irqrestore(&uic->lock, flags);
	89	}
	90
	91	static void uic_ack_irq(unsigned int virq)
	92	{
	93	struct uic *uic = get_irq_chip_data(virq);
	94	unsigned int src = uic_irq_to_hw(virq);
	95	unsigned long flags;
	96
	97	spin_lock_irqsave(&uic->lock, flags);
	98	mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
	99	spin_unlock_irqrestore(&uic->lock, flags);
	100	}
	101
b8b799a4 VB	102	static void uic_mask_ack_irq(unsigned int virq)
b8b799a4 VB	103	{
6cff46f4	104	struct irq_desc *desc = irq_to_desc(virq);
b8b799a4 VB	105	struct uic *uic = get_irq_chip_data(virq);
	106	unsigned int src = uic_irq_to_hw(virq);
	107	unsigned long flags;
	108	u32 er, sr;
	109
	110	sr = 1 << (31-src);
	111	spin_lock_irqsave(&uic->lock, flags);
	112	er = mfdcr(uic->dcrbase + UIC_ER);
	113	er &= ~sr;
	114	mtdcr(uic->dcrbase + UIC_ER, er);
c8090563 VB	115	/* On the UIC, acking (i.e. clearing the SR bit)
	116	* a level irq will have no effect if the interrupt
	117	* is still asserted by the device, even if
	118	* the interrupt is already masked. Therefore
	119	* we only ack the egde interrupts here, while
	120	* level interrupts are ack'ed after the actual
	121	* isr call in the uic_unmask_irq()
	122	*/
	123	if (!(desc->status & IRQ_LEVEL))
	124	mtdcr(uic->dcrbase + UIC_SR, sr);
b8b799a4 VB	125	spin_unlock_irqrestore(&uic->lock, flags);
	126	}
	127
e58923ed DG	128	static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
	129	{
	130	struct uic *uic = get_irq_chip_data(virq);
	131	unsigned int src = uic_irq_to_hw(virq);
6cff46f4	132	struct irq_desc *desc = irq_to_desc(virq);
e58923ed DG	133	unsigned long flags;
	134	int trigger, polarity;
	135	u32 tr, pr, mask;
	136
	137	switch (flow_type & IRQ_TYPE_SENSE_MASK) {
	138	case IRQ_TYPE_NONE:
	139	uic_mask_irq(virq);
	140	return 0;
	141
	142	case IRQ_TYPE_EDGE_RISING:
	143	trigger = 1; polarity = 1;
	144	break;
	145	case IRQ_TYPE_EDGE_FALLING:
	146	trigger = 1; polarity = 0;
	147	break;
	148	case IRQ_TYPE_LEVEL_HIGH:
	149	trigger = 0; polarity = 1;
	150	break;
	151	case IRQ_TYPE_LEVEL_LOW:
	152	trigger = 0; polarity = 0;
	153	break;
	154	default:
	155	return -EINVAL;
	156	}
	157
	158	mask = ~(1 << (31 - src));
	159
	160	spin_lock_irqsave(&uic->lock, flags);
	161	tr = mfdcr(uic->dcrbase + UIC_TR);
	162	pr = mfdcr(uic->dcrbase + UIC_PR);
	163	tr = (tr & mask) \| (trigger << (31-src));
	164	pr = (pr & mask) \| (polarity << (31-src));
	165
	166	mtdcr(uic->dcrbase + UIC_PR, pr);
	167	mtdcr(uic->dcrbase + UIC_TR, tr);
	168
	169	desc->status &= ~(IRQ_TYPE_SENSE_MASK \| IRQ_LEVEL);
	170	desc->status \|= flow_type & IRQ_TYPE_SENSE_MASK;
4dc7b4b0	171	if (!trigger)
e58923ed DG	172	desc->status \|= IRQ_LEVEL;
	173
	174	spin_unlock_irqrestore(&uic->lock, flags);
	175
	176	return 0;
	177	}
	178
	179	static struct irq_chip uic_irq_chip = {
b27df672	180	.name = " UIC ",
e58923ed DG	181	.unmask = uic_unmask_irq,
e58923ed DG	182	.mask = uic_mask_irq,
b8b799a4	183	.mask_ack = uic_mask_ack_irq,
e58923ed DG	184	.ack = uic_ack_irq,
	185	.set_type = uic_set_irq_type,
	186	};
	187
e58923ed DG	188	static int uic_host_map(struct irq_host *h, unsigned int virq,
	189	irq_hw_number_t hw)
	190	{
	191	struct uic *uic = h->host_data;
	192
	193	set_irq_chip_data(virq, uic);
	194	/* Despite the name, handle_level_irq() works for both level
	195	* and edge irqs on UIC. FIXME: check this is correct */
c8090563	196	set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
e58923ed DG	197
	198	/* Set default irq type */
	199	set_irq_type(virq, IRQ_TYPE_NONE);
	200
	201	return 0;
	202	}
	203
	204	static int uic_host_xlate(struct irq_host h, struct device_node ct,
40d50cf7	205	const u32 *intspec, unsigned int intsize,
e58923ed DG	206	irq_hw_number_t out_hwirq, unsigned int out_type)
	207
	208	{
	209	/* UIC intspecs must have 2 cells */
	210	BUG_ON(intsize != 2);
	211	*out_hwirq = intspec[0];
	212	*out_type = intspec[1];
	213	return 0;
	214	}
	215
	216	static struct irq_host_ops uic_host_ops = {
e58923ed DG	217	.map = uic_host_map,
	218	.xlate = uic_host_xlate,
	219	};
	220
5aac48dc	221	void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
e58923ed	222	{
5aac48dc	223	struct uic *uic = get_irq_data(virq);
e58923ed DG	224	u32 msr;
	225	int src;
	226	int subvirq;
	227
239007b8	228	raw_spin_lock(&desc->lock);
5aac48dc VB	229	if (desc->status & IRQ_LEVEL)
	230	desc->chip->mask(virq);
	231	else
	232	desc->chip->mask_ack(virq);
239007b8	233	raw_spin_unlock(&desc->lock);
5aac48dc	234
e58923ed	235	msr = mfdcr(uic->dcrbase + UIC_MSR);
553fdff6	236	if (!msr) /* spurious interrupt */
5aac48dc	237	goto uic_irq_ret;
553fdff6	238
e58923ed DG	239	src = 32 - ffs(msr);
	240
	241	subvirq = irq_linear_revmap(uic->irqhost, src);
	242	generic_handle_irq(subvirq);
	243
5aac48dc	244	uic_irq_ret:
239007b8	245	raw_spin_lock(&desc->lock);
5aac48dc VB	246	if (desc->status & IRQ_LEVEL)
	247	desc->chip->ack(virq);
	248	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
	249	desc->chip->unmask(virq);
239007b8	250	raw_spin_unlock(&desc->lock);
e58923ed DG	251	}
	252
	253	static struct uic * __init uic_init_one(struct device_node *node)
	254	{
	255	struct uic *uic;
	256	const u32 indexp, dcrreg;
	257	int len;
	258
55b61fec	259	BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
e58923ed	260
ea96025a	261	uic = kzalloc(sizeof(*uic), GFP_KERNEL);
e58923ed DG	262	if (! uic)
	263	return NULL; /* FIXME: panic? */
	264
e58923ed	265	spin_lock_init(&uic->lock);
12d371a6	266	indexp = of_get_property(node, "cell-index", &len);
e58923ed DG	267	if (!indexp \|\| (len != sizeof(u32))) {
	268	printk(KERN_ERR "uic: Device node %s has missing or invalid "
	269	"cell-index property\n", node->full_name);
	270	return NULL;
	271	}
	272	uic->index = *indexp;
	273
12d371a6	274	dcrreg = of_get_property(node, "dcr-reg", &len);
e58923ed DG	275	if (!dcrreg \|\| (len != 2*sizeof(u32))) {
	276	printk(KERN_ERR "uic: Device node %s has missing or invalid "
	277	"dcr-reg property\n", node->full_name);
	278	return NULL;
	279	}
	280	uic->dcrbase = *dcrreg;
	281
19fc65b5	282	uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
52964f87	283	NR_UIC_INTS, &uic_host_ops, -1);
19fc65b5	284	if (! uic->irqhost)
e58923ed	285	return NULL; /* FIXME: panic? */
e58923ed DG	286
	287	uic->irqhost->host_data = uic;
	288
	289	/* Start with all interrupts disabled, level and non-critical */
	290	mtdcr(uic->dcrbase + UIC_ER, 0);
	291	mtdcr(uic->dcrbase + UIC_CR, 0);
	292	mtdcr(uic->dcrbase + UIC_TR, 0);
	293	/* Clear any pending interrupts, in case the firmware left some */
	294	mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
	295
	296	printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
	297	NR_UIC_INTS, uic->dcrbase);
	298
	299	return uic;
	300	}
	301
	302	void __init uic_init_tree(void)
	303	{
	304	struct device_node *np;
	305	struct uic *uic;
	306	const u32 *interrupts;
	307
	308	/* First locate and initialize the top-level UIC */
26cb7d8b	309	for_each_compatible_node(np, NULL, "ibm,uic") {
12d371a6	310	interrupts = of_get_property(np, "interrupts", NULL);
26cb7d8b	311	if (!interrupts)
e58923ed	312	break;
e58923ed DG	313	}
	314
	315	BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
	316	* top-level interrupt controller */
	317	primary_uic = uic_init_one(np);
26cb7d8b	318	if (!primary_uic)
e58923ed DG	319	panic("Unable to initialize primary UIC %s\n", np->full_name);
	320
	321	irq_set_default_host(primary_uic->irqhost);
	322	of_node_put(np);
	323
	324	/* The scan again for cascaded UICs */
26cb7d8b	325	for_each_compatible_node(np, NULL, "ibm,uic") {
12d371a6	326	interrupts = of_get_property(np, "interrupts", NULL);
e58923ed DG	327	if (interrupts) {
	328	/* Secondary UIC */
	329	int cascade_virq;
e58923ed DG	330
	331	uic = uic_init_one(np);
	332	if (! uic)
	333	panic("Unable to initialize a secondary UIC %s\n",
	334	np->full_name);
	335
	336	cascade_virq = irq_of_parse_and_map(np, 0);
	337
5aac48dc VB	338	set_irq_data(cascade_virq, uic);
5aac48dc VB	339	set_irq_chained_handler(cascade_virq, uic_irq_cascade);
e58923ed DG	340
	341	/* FIXME: setup critical cascade?? */
	342	}
e58923ed DG	343	}
	344	}
	345
	346	/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
	347	unsigned int uic_get_irq(void)
	348	{
	349	u32 msr;
	350	int src;
	351
	352	BUG_ON(! primary_uic);
	353
	354	msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
	355	src = 32 - ffs(msr);
	356
	357	return irq_linear_revmap(primary_uic->irqhost, src);
	358	}