treewide: Convert uses of struct resource to resource_size(ptr)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / sysdev / mpc8xx_pic.c
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f2a0bd37
VB
1#include <linux/kernel.h>
2#include <linux/module.h>
3#include <linux/stddef.h>
4#include <linux/init.h>
5#include <linux/sched.h>
6#include <linux/signal.h>
7#include <linux/irq.h>
8#include <linux/dma-mapping.h>
9#include <asm/prom.h>
10#include <asm/irq.h>
11#include <asm/io.h>
12#include <asm/8xx_immap.h>
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VB
13
14#include "mpc8xx_pic.h"
15
16
17#define PIC_VEC_SPURRIOUS 15
18
19extern int cpm_get_irq(struct pt_regs *regs);
20
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VB
21static struct irq_host *mpc8xx_pic_host;
22#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
23static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
fb533d0c 24static sysconf8xx_t __iomem *siu_reg;
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25
26int cpm_get_irq(struct pt_regs *regs);
27
febd4017 28static void mpc8xx_unmask_irq(struct irq_data *d)
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VB
29{
30 int bit, word;
476eb491 31 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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32
33 bit = irq_nr & 0x1f;
34 word = irq_nr >> 5;
35
36 ppc_cached_irq_mask[word] |= (1 << (31-bit));
37 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
38}
39
febd4017 40static void mpc8xx_mask_irq(struct irq_data *d)
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41{
42 int bit, word;
476eb491 43 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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44
45 bit = irq_nr & 0x1f;
46 word = irq_nr >> 5;
47
48 ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
49 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
50}
51
febd4017 52static void mpc8xx_ack(struct irq_data *d)
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VB
53{
54 int bit;
476eb491 55 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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56
57 bit = irq_nr & 0x1f;
58 out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
59}
60
febd4017 61static void mpc8xx_end_irq(struct irq_data *d)
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VB
62{
63 int bit, word;
476eb491 64 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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65
66 bit = irq_nr & 0x1f;
67 word = irq_nr >> 5;
68
69 ppc_cached_irq_mask[word] |= (1 << (31-bit));
70 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
71}
72
febd4017 73static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
f2a0bd37 74{
f2a0bd37 75 if (flow_type & IRQ_TYPE_EDGE_FALLING) {
476eb491 76 irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
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VB
77 unsigned int siel = in_be32(&siu_reg->sc_siel);
78
79 /* only external IRQ senses are programmable */
80 if ((hw & 1) == 0) {
81 siel |= (0x80000000 >> hw);
82 out_be32(&siu_reg->sc_siel, siel);
b3cf2bb3 83 __irq_set_handler_locked(d->irq, handle_edge_irq);
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84 }
85 }
86 return 0;
87}
88
89static struct irq_chip mpc8xx_pic = {
fc380c0c 90 .name = "MPC8XX SIU",
febd4017
LB
91 .irq_unmask = mpc8xx_unmask_irq,
92 .irq_mask = mpc8xx_mask_irq,
93 .irq_ack = mpc8xx_ack,
94 .irq_eoi = mpc8xx_end_irq,
95 .irq_set_type = mpc8xx_set_irq_type,
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VB
96};
97
98unsigned int mpc8xx_get_irq(void)
99{
100 int irq;
101
102 /* For MPC8xx, read the SIVEC register and shift the bits down
103 * to get the irq number.
104 */
105 irq = in_be32(&siu_reg->sc_sivec) >> 26;
106
107 if (irq == PIC_VEC_SPURRIOUS)
108 irq = NO_IRQ;
109
110 return irq_linear_revmap(mpc8xx_pic_host, irq);
111
112}
113
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114static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
115 irq_hw_number_t hw)
116{
117 pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
118
119 /* Set default irq handle */
ec775d0e 120 irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
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121 return 0;
122}
123
124
125static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
40d50cf7 126 const u32 *intspec, unsigned int intsize,
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127 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
128{
129 static unsigned char map_pic_senses[4] = {
130 IRQ_TYPE_EDGE_RISING,
131 IRQ_TYPE_LEVEL_LOW,
132 IRQ_TYPE_LEVEL_HIGH,
133 IRQ_TYPE_EDGE_FALLING,
134 };
135
136 *out_hwirq = intspec[0];
137 if (intsize > 1 && intspec[1] < 4)
138 *out_flags = map_pic_senses[intspec[1]];
139 else
140 *out_flags = IRQ_TYPE_NONE;
141
142 return 0;
143}
144
145
146static struct irq_host_ops mpc8xx_pic_host_ops = {
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147 .map = mpc8xx_pic_host_map,
148 .xlate = mpc8xx_pic_host_xlate,
149};
150
151int mpc8xx_pic_init(void)
152{
153 struct resource res;
fb533d0c 154 struct device_node *np;
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155 int ret;
156
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157 np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
158 if (np == NULL)
159 np = of_find_node_by_type(NULL, "mpc8xx-pic");
f2a0bd37 160 if (np == NULL) {
fb533d0c 161 printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
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162 return -ENOMEM;
163 }
164
f2a0bd37 165 ret = of_address_to_resource(np, 0, &res);
f2a0bd37 166 if (ret)
52964f87 167 goto out;
f2a0bd37 168
28f65c11 169 siu_reg = ioremap(res.start, resource_size(&res));
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JL
170 if (siu_reg == NULL) {
171 ret = -EINVAL;
172 goto out;
173 }
f2a0bd37 174
b1725c93 175 mpc8xx_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
52964f87 176 64, &mpc8xx_pic_host_ops, 64);
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VB
177 if (mpc8xx_pic_host == NULL) {
178 printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
179 ret = -ENOMEM;
b1725c93 180 goto out;
f2a0bd37 181 }
b1725c93 182 return 0;
f2a0bd37 183
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ME
184out:
185 of_node_put(np);
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186 return ret;
187}