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34e36c15 | 1 | /* |
6820fead | 2 | * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. |
34e36c15 JJ |
3 | * |
4 | * Author: Tony Li <tony.li@freescale.com> | |
5 | * Jason Jin <Jason.jin@freescale.com> | |
6 | * | |
7 | * The hwirq alloc and free code reuse from sysdev/mpic_msi.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | */ | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bootmem.h> | |
34e36c15 JJ |
17 | #include <linux/msi.h> |
18 | #include <linux/pci.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
34e36c15 JJ |
20 | #include <linux/of_platform.h> |
21 | #include <sysdev/fsl_soc.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/hw_irq.h> | |
24 | #include <asm/ppc-pci.h> | |
02adac60 | 25 | #include <asm/mpic.h> |
446bc1ff TT |
26 | #include <asm/fsl_hcalls.h> |
27 | ||
34e36c15 | 28 | #include "fsl_msi.h" |
b8f44ec2 | 29 | #include "fsl_pci.h" |
34e36c15 | 30 | |
6cce76dc | 31 | static LIST_HEAD(msi_head); |
694a7a36 | 32 | |
34e36c15 JJ |
33 | struct fsl_msi_feature { |
34 | u32 fsl_pic_ip; | |
2bcd1c0c | 35 | u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */ |
34e36c15 JJ |
36 | }; |
37 | ||
02adac60 LY |
38 | struct fsl_msi_cascade_data { |
39 | struct fsl_msi *msi_data; | |
40 | int index; | |
41 | }; | |
34e36c15 JJ |
42 | |
43 | static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) | |
44 | { | |
45 | return in_be32(base + (reg >> 2)); | |
46 | } | |
47 | ||
34e36c15 JJ |
48 | /* |
49 | * We do not need this actually. The MSIR register has been read once | |
50 | * in the cascade interrupt. So, this MSI interrupt has been acked | |
51 | */ | |
37e16615 | 52 | static void fsl_msi_end_irq(struct irq_data *d) |
34e36c15 JJ |
53 | { |
54 | } | |
55 | ||
56 | static struct irq_chip fsl_msi_chip = { | |
1c9db525 TG |
57 | .irq_mask = mask_msi_irq, |
58 | .irq_unmask = unmask_msi_irq, | |
37e16615 | 59 | .irq_ack = fsl_msi_end_irq, |
fc380c0c | 60 | .name = "FSL-MSI", |
34e36c15 JJ |
61 | }; |
62 | ||
bae1d8f1 | 63 | static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq, |
34e36c15 JJ |
64 | irq_hw_number_t hw) |
65 | { | |
80818813 | 66 | struct fsl_msi *msi_data = h->host_data; |
34e36c15 JJ |
67 | struct irq_chip *chip = &fsl_msi_chip; |
68 | ||
98488db9 | 69 | irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); |
34e36c15 | 70 | |
ec775d0e TG |
71 | irq_set_chip_data(virq, msi_data); |
72 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); | |
34e36c15 JJ |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
9f70b8eb | 77 | static const struct irq_domain_ops fsl_msi_host_ops = { |
34e36c15 JJ |
78 | .map = fsl_msi_host_map, |
79 | }; | |
80 | ||
34e36c15 JJ |
81 | static int fsl_msi_init_allocator(struct fsl_msi *msi_data) |
82 | { | |
692d1037 | 83 | int rc; |
34e36c15 | 84 | |
7e7ab367 ME |
85 | rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, |
86 | msi_data->irqhost->of_node); | |
87 | if (rc) | |
88 | return rc; | |
34e36c15 | 89 | |
7e7ab367 ME |
90 | rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); |
91 | if (rc < 0) { | |
92 | msi_bitmap_free(&msi_data->bitmap); | |
93 | return rc; | |
34e36c15 JJ |
94 | } |
95 | ||
34e36c15 | 96 | return 0; |
34e36c15 JJ |
97 | } |
98 | ||
99 | static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) | |
100 | { | |
101 | if (type == PCI_CAP_ID_MSIX) | |
102 | pr_debug("fslmsi: MSI-X untested, trying anyway.\n"); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |
108 | { | |
109 | struct msi_desc *entry; | |
80818813 | 110 | struct fsl_msi *msi_data; |
892e053c | 111 | irq_hw_number_t hwirq; |
34e36c15 JJ |
112 | |
113 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
114 | if (entry->irq == NO_IRQ) | |
115 | continue; | |
892e053c | 116 | hwirq = virq_to_hw(entry->irq); |
d1921bcd | 117 | msi_data = irq_get_chip_data(entry->irq); |
ec775d0e | 118 | irq_set_msi_desc(entry->irq, NULL); |
34e36c15 | 119 | irq_dispose_mapping(entry->irq); |
892e053c | 120 | msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); |
34e36c15 JJ |
121 | } |
122 | ||
123 | return; | |
124 | } | |
125 | ||
126 | static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, | |
80818813 LCB |
127 | struct msi_msg *msg, |
128 | struct fsl_msi *fsl_msi_data) | |
34e36c15 | 129 | { |
80818813 | 130 | struct fsl_msi *msi_data = fsl_msi_data; |
3da34aae | 131 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
2bcd1c0c TT |
132 | u64 address; /* Physical address of the MSIIR */ |
133 | int len; | |
6cce76dc | 134 | const __be64 *reg; |
2bcd1c0c TT |
135 | |
136 | /* If the msi-address-64 property exists, then use it */ | |
137 | reg = of_get_property(hose->dn, "msi-address-64", &len); | |
138 | if (reg && (len == sizeof(u64))) | |
139 | address = be64_to_cpup(reg); | |
140 | else | |
141 | address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset; | |
34e36c15 | 142 | |
2bcd1c0c TT |
143 | msg->address_lo = lower_32_bits(address); |
144 | msg->address_hi = upper_32_bits(address); | |
3da34aae | 145 | |
34e36c15 JJ |
146 | msg->data = hwirq; |
147 | ||
148 | pr_debug("%s: allocated srs: %d, ibs: %d\n", | |
149 | __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); | |
150 | } | |
151 | ||
152 | static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
153 | { | |
895d603f TT |
154 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
155 | struct device_node *np; | |
156 | phandle phandle = 0; | |
694a7a36 | 157 | int rc, hwirq = -ENOMEM; |
34e36c15 JJ |
158 | unsigned int virq; |
159 | struct msi_desc *entry; | |
160 | struct msi_msg msg; | |
80818813 | 161 | struct fsl_msi *msi_data; |
34e36c15 | 162 | |
895d603f TT |
163 | /* |
164 | * If the PCI node has an fsl,msi property, then we need to use it | |
165 | * to find the specific MSI. | |
166 | */ | |
167 | np = of_parse_phandle(hose->dn, "fsl,msi", 0); | |
168 | if (np) { | |
446bc1ff TT |
169 | if (of_device_is_compatible(np, "fsl,mpic-msi") || |
170 | of_device_is_compatible(np, "fsl,vmpic-msi")) | |
895d603f TT |
171 | phandle = np->phandle; |
172 | else { | |
446bc1ff TT |
173 | dev_err(&pdev->dev, |
174 | "node %s has an invalid fsl,msi phandle %u\n", | |
175 | hose->dn->full_name, np->phandle); | |
895d603f TT |
176 | return -EINVAL; |
177 | } | |
178 | } | |
179 | ||
34e36c15 | 180 | list_for_each_entry(entry, &pdev->msi_list, list) { |
895d603f TT |
181 | /* |
182 | * Loop over all the MSI devices until we find one that has an | |
183 | * available interrupt. | |
184 | */ | |
694a7a36 | 185 | list_for_each_entry(msi_data, &msi_head, list) { |
895d603f TT |
186 | /* |
187 | * If the PCI node has an fsl,msi property, then we | |
188 | * restrict our search to the corresponding MSI node. | |
189 | * The simplest way is to skip over MSI nodes with the | |
190 | * wrong phandle. Under the Freescale hypervisor, this | |
191 | * has the additional benefit of skipping over MSI | |
192 | * nodes that are not mapped in the PAMU. | |
193 | */ | |
194 | if (phandle && (phandle != msi_data->phandle)) | |
195 | continue; | |
196 | ||
694a7a36 LY |
197 | hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); |
198 | if (hwirq >= 0) | |
199 | break; | |
200 | } | |
80818813 | 201 | |
34e36c15 JJ |
202 | if (hwirq < 0) { |
203 | rc = hwirq; | |
446bc1ff | 204 | dev_err(&pdev->dev, "could not allocate MSI interrupt\n"); |
34e36c15 JJ |
205 | goto out_free; |
206 | } | |
207 | ||
208 | virq = irq_create_mapping(msi_data->irqhost, hwirq); | |
209 | ||
210 | if (virq == NO_IRQ) { | |
446bc1ff | 211 | dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq); |
7e7ab367 | 212 | msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); |
34e36c15 JJ |
213 | rc = -ENOSPC; |
214 | goto out_free; | |
215 | } | |
d1921bcd | 216 | /* chip_data is msi_data via host->hostdata in host->map() */ |
ec775d0e | 217 | irq_set_msi_desc(virq, entry); |
34e36c15 | 218 | |
80818813 | 219 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); |
34e36c15 JJ |
220 | write_msi_msg(virq, &msg); |
221 | } | |
222 | return 0; | |
223 | ||
224 | out_free: | |
694a7a36 | 225 | /* free by the caller of this function */ |
34e36c15 JJ |
226 | return rc; |
227 | } | |
228 | ||
692d1037 | 229 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
34e36c15 | 230 | { |
ddaedd1c TG |
231 | struct irq_chip *chip = irq_desc_get_chip(desc); |
232 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
34e36c15 | 233 | unsigned int cascade_irq; |
02adac60 | 234 | struct fsl_msi *msi_data; |
34e36c15 JJ |
235 | int msir_index = -1; |
236 | u32 msir_value = 0; | |
237 | u32 intr_index; | |
238 | u32 have_shift = 0; | |
02adac60 LY |
239 | struct fsl_msi_cascade_data *cascade_data; |
240 | ||
d1921bcd | 241 | cascade_data = irq_get_handler_data(irq); |
02adac60 | 242 | msi_data = cascade_data->msi_data; |
34e36c15 | 243 | |
239007b8 | 244 | raw_spin_lock(&desc->lock); |
34e36c15 | 245 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
37e16615 | 246 | if (chip->irq_mask_ack) |
ddaedd1c | 247 | chip->irq_mask_ack(idata); |
34e36c15 | 248 | else { |
ddaedd1c TG |
249 | chip->irq_mask(idata); |
250 | chip->irq_ack(idata); | |
34e36c15 JJ |
251 | } |
252 | } | |
253 | ||
ddaedd1c | 254 | if (unlikely(irqd_irq_inprogress(idata))) |
34e36c15 JJ |
255 | goto unlock; |
256 | ||
02adac60 | 257 | msir_index = cascade_data->index; |
34e36c15 JJ |
258 | |
259 | if (msir_index >= NR_MSI_REG) | |
260 | cascade_irq = NO_IRQ; | |
261 | ||
ddaedd1c | 262 | irqd_set_chained_irq_inprogress(idata); |
80818813 | 263 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
34e36c15 JJ |
264 | case FSL_PIC_IP_MPIC: |
265 | msir_value = fsl_msi_read(msi_data->msi_regs, | |
266 | msir_index * 0x10); | |
267 | break; | |
268 | case FSL_PIC_IP_IPIC: | |
269 | msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); | |
270 | break; | |
305bcf26 SW |
271 | #ifdef CONFIG_EPAPR_PARAVIRT |
272 | case FSL_PIC_IP_VMPIC: { | |
273 | unsigned int ret; | |
446bc1ff TT |
274 | ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value); |
275 | if (ret) { | |
276 | pr_err("fsl-msi: fh_vmpic_get_msir() failed for " | |
277 | "irq %u (ret=%u)\n", irq, ret); | |
278 | msir_value = 0; | |
279 | } | |
280 | break; | |
34e36c15 | 281 | } |
305bcf26 SW |
282 | #endif |
283 | } | |
34e36c15 JJ |
284 | |
285 | while (msir_value) { | |
286 | intr_index = ffs(msir_value) - 1; | |
287 | ||
288 | cascade_irq = irq_linear_revmap(msi_data->irqhost, | |
692d1037 AV |
289 | msir_index * IRQS_PER_MSI_REG + |
290 | intr_index + have_shift); | |
34e36c15 JJ |
291 | if (cascade_irq != NO_IRQ) |
292 | generic_handle_irq(cascade_irq); | |
692d1037 AV |
293 | have_shift += intr_index + 1; |
294 | msir_value = msir_value >> (intr_index + 1); | |
34e36c15 | 295 | } |
ddaedd1c | 296 | irqd_clr_chained_irq_inprogress(idata); |
34e36c15 JJ |
297 | |
298 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | |
299 | case FSL_PIC_IP_MPIC: | |
446bc1ff | 300 | case FSL_PIC_IP_VMPIC: |
ddaedd1c | 301 | chip->irq_eoi(idata); |
34e36c15 JJ |
302 | break; |
303 | case FSL_PIC_IP_IPIC: | |
ddaedd1c TG |
304 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
305 | chip->irq_unmask(idata); | |
34e36c15 JJ |
306 | break; |
307 | } | |
308 | unlock: | |
239007b8 | 309 | raw_spin_unlock(&desc->lock); |
34e36c15 JJ |
310 | } |
311 | ||
a454dc50 | 312 | static int fsl_of_msi_remove(struct platform_device *ofdev) |
48059993 | 313 | { |
6c4c82e2 | 314 | struct fsl_msi *msi = platform_get_drvdata(ofdev); |
48059993 LY |
315 | int virq, i; |
316 | struct fsl_msi_cascade_data *cascade_data; | |
317 | ||
318 | if (msi->list.prev != NULL) | |
319 | list_del(&msi->list); | |
320 | for (i = 0; i < NR_MSI_REG; i++) { | |
321 | virq = msi->msi_virqs[i]; | |
322 | if (virq != NO_IRQ) { | |
ec775d0e | 323 | cascade_data = irq_get_handler_data(virq); |
48059993 LY |
324 | kfree(cascade_data); |
325 | irq_dispose_mapping(virq); | |
326 | } | |
327 | } | |
328 | if (msi->bitmap.bitmap) | |
329 | msi_bitmap_free(&msi->bitmap); | |
446bc1ff TT |
330 | if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) |
331 | iounmap(msi->msi_regs); | |
48059993 LY |
332 | kfree(msi); |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
58631ad1 SAS |
337 | static struct lock_class_key fsl_msi_irq_class; |
338 | ||
cad5cef6 GKH |
339 | static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, |
340 | int offset, int irq_index) | |
6820fead SW |
341 | { |
342 | struct fsl_msi_cascade_data *cascade_data = NULL; | |
343 | int virt_msir; | |
344 | ||
345 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); | |
346 | if (virt_msir == NO_IRQ) { | |
347 | dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n", | |
348 | __func__, irq_index); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL); | |
353 | if (!cascade_data) { | |
354 | dev_err(&dev->dev, "No memory for MSI cascade data\n"); | |
355 | return -ENOMEM; | |
356 | } | |
58631ad1 | 357 | irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class); |
6820fead | 358 | msi->msi_virqs[irq_index] = virt_msir; |
22285118 | 359 | cascade_data->index = offset; |
6820fead | 360 | cascade_data->msi_data = msi; |
ec775d0e TG |
361 | irq_set_handler_data(virt_msir, cascade_data); |
362 | irq_set_chained_handler(virt_msir, fsl_msi_cascade); | |
6820fead SW |
363 | |
364 | return 0; | |
365 | } | |
366 | ||
b1608d69 | 367 | static const struct of_device_id fsl_of_msi_ids[]; |
cad5cef6 | 368 | static int fsl_of_msi_probe(struct platform_device *dev) |
34e36c15 | 369 | { |
b1608d69 | 370 | const struct of_device_id *match; |
34e36c15 JJ |
371 | struct fsl_msi *msi; |
372 | struct resource res; | |
6820fead | 373 | int err, i, j, irq_index, count; |
34e36c15 | 374 | int rc; |
34e36c15 | 375 | const u32 *p; |
f318f1d7 | 376 | const struct fsl_msi_feature *features; |
061ca4ad LY |
377 | int len; |
378 | u32 offset; | |
6820fead | 379 | static const u32 all_avail[] = { 0, NR_MSI_IRQS }; |
34e36c15 | 380 | |
b1608d69 GL |
381 | match = of_match_device(fsl_of_msi_ids, &dev->dev); |
382 | if (!match) | |
00006124 | 383 | return -EINVAL; |
b1608d69 | 384 | features = match->data; |
00006124 | 385 | |
34e36c15 JJ |
386 | printk(KERN_DEBUG "Setting up Freescale MSI support\n"); |
387 | ||
388 | msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); | |
389 | if (!msi) { | |
390 | dev_err(&dev->dev, "No memory for MSI structure\n"); | |
48059993 | 391 | return -ENOMEM; |
34e36c15 | 392 | } |
6c4c82e2 | 393 | platform_set_drvdata(dev, msi); |
34e36c15 | 394 | |
a8db8cf0 GL |
395 | msi->irqhost = irq_domain_add_linear(dev->dev.of_node, |
396 | NR_MSI_IRQS, &fsl_msi_host_ops, msi); | |
34e36c15 | 397 | |
34e36c15 JJ |
398 | if (msi->irqhost == NULL) { |
399 | dev_err(&dev->dev, "No memory for MSI irqhost\n"); | |
34e36c15 JJ |
400 | err = -ENOMEM; |
401 | goto error_out; | |
402 | } | |
403 | ||
446bc1ff TT |
404 | /* |
405 | * Under the Freescale hypervisor, the msi nodes don't have a 'reg' | |
406 | * property. Instead, we use hypercalls to access the MSI. | |
407 | */ | |
408 | if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) { | |
409 | err = of_address_to_resource(dev->dev.of_node, 0, &res); | |
410 | if (err) { | |
411 | dev_err(&dev->dev, "invalid resource for node %s\n", | |
61c7a080 | 412 | dev->dev.of_node->full_name); |
446bc1ff TT |
413 | goto error_out; |
414 | } | |
34e36c15 | 415 | |
446bc1ff TT |
416 | msi->msi_regs = ioremap(res.start, resource_size(&res)); |
417 | if (!msi->msi_regs) { | |
b53804c7 | 418 | err = -ENOMEM; |
446bc1ff TT |
419 | dev_err(&dev->dev, "could not map node %s\n", |
420 | dev->dev.of_node->full_name); | |
421 | goto error_out; | |
422 | } | |
423 | msi->msiir_offset = | |
424 | features->msiir_offset + (res.start & 0xfffff); | |
34e36c15 JJ |
425 | } |
426 | ||
692d1037 | 427 | msi->feature = features->fsl_pic_ip; |
34e36c15 | 428 | |
895d603f TT |
429 | /* |
430 | * Remember the phandle, so that we can match with any PCI nodes | |
431 | * that have an "fsl,msi" property. | |
432 | */ | |
433 | msi->phandle = dev->dev.of_node->phandle; | |
434 | ||
34e36c15 JJ |
435 | rc = fsl_msi_init_allocator(msi); |
436 | if (rc) { | |
437 | dev_err(&dev->dev, "Error allocating MSI bitmap\n"); | |
438 | goto error_out; | |
439 | } | |
440 | ||
6820fead SW |
441 | p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); |
442 | if (p && len % (2 * sizeof(u32)) != 0) { | |
443 | dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n", | |
444 | __func__); | |
34e36c15 JJ |
445 | err = -EINVAL; |
446 | goto error_out; | |
447 | } | |
6820fead | 448 | |
22285118 | 449 | if (!p) { |
6820fead | 450 | p = all_avail; |
22285118 TT |
451 | len = sizeof(all_avail); |
452 | } | |
6820fead SW |
453 | |
454 | for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { | |
455 | if (p[i * 2] % IRQS_PER_MSI_REG || | |
456 | p[i * 2 + 1] % IRQS_PER_MSI_REG) { | |
457 | printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n", | |
458 | __func__, dev->dev.of_node->full_name, | |
459 | p[i * 2 + 1], p[i * 2]); | |
460 | err = -EINVAL; | |
461 | goto error_out; | |
462 | } | |
463 | ||
464 | offset = p[i * 2] / IRQS_PER_MSI_REG; | |
465 | count = p[i * 2 + 1] / IRQS_PER_MSI_REG; | |
466 | ||
467 | for (j = 0; j < count; j++, irq_index++) { | |
22285118 | 468 | err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index); |
6820fead | 469 | if (err) |
02adac60 | 470 | goto error_out; |
34e36c15 JJ |
471 | } |
472 | } | |
473 | ||
694a7a36 | 474 | list_add_tail(&msi->list, &msi_head); |
34e36c15 | 475 | |
80818813 LCB |
476 | /* The multiple setting ppc_md.setup_msi_irqs will not harm things */ |
477 | if (!ppc_md.setup_msi_irqs) { | |
478 | ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; | |
479 | ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; | |
480 | ppc_md.msi_check_device = fsl_msi_check_device; | |
481 | } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) { | |
482 | dev_err(&dev->dev, "Different MSI driver already installed!\n"); | |
483 | err = -ENODEV; | |
484 | goto error_out; | |
485 | } | |
34e36c15 JJ |
486 | return 0; |
487 | error_out: | |
48059993 | 488 | fsl_of_msi_remove(dev); |
34e36c15 JJ |
489 | return err; |
490 | } | |
491 | ||
492 | static const struct fsl_msi_feature mpic_msi_feature = { | |
493 | .fsl_pic_ip = FSL_PIC_IP_MPIC, | |
494 | .msiir_offset = 0x140, | |
495 | }; | |
496 | ||
497 | static const struct fsl_msi_feature ipic_msi_feature = { | |
498 | .fsl_pic_ip = FSL_PIC_IP_IPIC, | |
499 | .msiir_offset = 0x38, | |
500 | }; | |
501 | ||
446bc1ff TT |
502 | static const struct fsl_msi_feature vmpic_msi_feature = { |
503 | .fsl_pic_ip = FSL_PIC_IP_VMPIC, | |
504 | .msiir_offset = 0, | |
505 | }; | |
506 | ||
34e36c15 JJ |
507 | static const struct of_device_id fsl_of_msi_ids[] = { |
508 | { | |
509 | .compatible = "fsl,mpic-msi", | |
a99cc82b | 510 | .data = &mpic_msi_feature, |
34e36c15 JJ |
511 | }, |
512 | { | |
513 | .compatible = "fsl,ipic-msi", | |
a99cc82b | 514 | .data = &ipic_msi_feature, |
34e36c15 | 515 | }, |
305bcf26 | 516 | #ifdef CONFIG_EPAPR_PARAVIRT |
446bc1ff TT |
517 | { |
518 | .compatible = "fsl,vmpic-msi", | |
a99cc82b | 519 | .data = &vmpic_msi_feature, |
446bc1ff | 520 | }, |
305bcf26 | 521 | #endif |
34e36c15 JJ |
522 | {} |
523 | }; | |
524 | ||
00006124 | 525 | static struct platform_driver fsl_of_msi_driver = { |
4018294b GL |
526 | .driver = { |
527 | .name = "fsl-msi", | |
528 | .owner = THIS_MODULE, | |
529 | .of_match_table = fsl_of_msi_ids, | |
530 | }, | |
34e36c15 | 531 | .probe = fsl_of_msi_probe, |
48059993 | 532 | .remove = fsl_of_msi_remove, |
34e36c15 JJ |
533 | }; |
534 | ||
535 | static __init int fsl_of_msi_init(void) | |
536 | { | |
00006124 | 537 | return platform_driver_register(&fsl_of_msi_driver); |
34e36c15 JJ |
538 | } |
539 | ||
540 | subsys_initcall(fsl_of_msi_init); |