powerpc/book3e: Fix CPU feature handling on e5500 in 32-bit mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / sysdev / fsl_lbc.c
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1/*
2 * Freescale LBC and UPM routines.
3 *
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4 * Copyright © 2007-2008 MontaVista Software, Inc.
5 * Copyright © 2010 Freescale Semiconductor
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6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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8 * Author: Jack Lan <Jack.Lan@freescale.com>
9 * Author: Roy Zang <tie-fei.zang@freescale.com>
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10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
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17#include <linux/init.h>
18#include <linux/module.h>
acaa7aa3 19#include <linux/kernel.h>
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20#include <linux/compiler.h>
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/io.h>
acaa7aa3 24#include <linux/of.h>
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25#include <linux/slab.h>
26#include <linux/platform_device.h>
27#include <linux/interrupt.h>
28#include <linux/mod_devicetable.h>
c0da99d5 29#include <asm/prom.h>
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30#include <asm/fsl_lbc.h>
31
c0da99d5 32static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
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33struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
34EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
acaa7aa3 35
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36/**
37 * fsl_lbc_addr - convert the base address
38 * @addr_base: base address of the memory bank
39 *
40 * This function converts a base address of lbc into the right format for the
41 * BR register. If the SOC has eLBC then it returns 32bit physical address
42 * else it convers a 34bit local bus physical address to correct format of
43 * 32bit address for BR register (Example: MPC8641).
44 */
45u32 fsl_lbc_addr(phys_addr_t addr_base)
46{
47 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
48 u32 addr = addr_base & 0xffff8000;
49
50 if (of_device_is_compatible(np, "fsl,elbc"))
51 return addr;
52
53 return addr | ((addr_base & 0x300000000ull) >> 19);
54}
55EXPORT_SYMBOL(fsl_lbc_addr);
56
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57/**
58 * fsl_lbc_find - find Localbus bank
59 * @addr_base: base address of the memory bank
60 *
61 * This function walks LBC banks comparing "Base address" field of the BR
62 * registers with the supplied addr_base argument. When bases match this
63 * function returns bank number (starting with 0), otherwise it returns
64 * appropriate errno value.
65 */
66int fsl_lbc_find(phys_addr_t addr_base)
67{
68 int i;
3ab8f2a2 69 struct fsl_lbc_regs __iomem *lbc;
acaa7aa3 70
3ab8f2a2 71 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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72 return -ENODEV;
73
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74 lbc = fsl_lbc_ctrl_dev->regs;
75 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
76 __be32 br = in_be32(&lbc->bank[i].br);
77 __be32 or = in_be32(&lbc->bank[i].or);
acaa7aa3 78
0b824d2b 79 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
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80 return i;
81 }
82
83 return -ENOENT;
84}
85EXPORT_SYMBOL(fsl_lbc_find);
86
87/**
88 * fsl_upm_find - find pre-programmed UPM via base address
89 * @addr_base: base address of the memory bank controlled by the UPM
90 * @upm: pointer to the allocated fsl_upm structure
91 *
92 * This function fills fsl_upm structure so you can use it with the rest of
93 * UPM API. On success this function returns 0, otherwise it returns
94 * appropriate errno value.
95 */
96int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
97{
98 int bank;
99 __be32 br;
3ab8f2a2 100 struct fsl_lbc_regs __iomem *lbc;
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101
102 bank = fsl_lbc_find(addr_base);
103 if (bank < 0)
104 return bank;
105
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106 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
107 return -ENODEV;
108
109 lbc = fsl_lbc_ctrl_dev->regs;
110 br = in_be32(&lbc->bank[bank].br);
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111
112 switch (br & BR_MSEL) {
113 case BR_MS_UPMA:
3ab8f2a2 114 upm->mxmr = &lbc->mamr;
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115 break;
116 case BR_MS_UPMB:
3ab8f2a2 117 upm->mxmr = &lbc->mbmr;
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118 break;
119 case BR_MS_UPMC:
3ab8f2a2 120 upm->mxmr = &lbc->mcmr;
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121 break;
122 default:
123 return -EINVAL;
124 }
125
126 switch (br & BR_PS) {
127 case BR_PS_8:
128 upm->width = 8;
129 break;
130 case BR_PS_16:
131 upm->width = 16;
132 break;
133 case BR_PS_32:
134 upm->width = 32;
135 break;
136 default:
137 return -EINVAL;
138 }
139
140 return 0;
141}
142EXPORT_SYMBOL(fsl_upm_find);
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143
144/**
145 * fsl_upm_run_pattern - actually run an UPM pattern
146 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
147 * @io_base: remapped pointer to where memory access should happen
148 * @mar: MAR register content during pattern execution
149 *
150 * This function triggers dummy write to the memory specified by the io_base,
151 * thus UPM pattern actually executed. Note that mar usage depends on the
152 * pre-programmed AMX bits in the UPM RAM.
153 */
154int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
155{
156 int ret = 0;
157 unsigned long flags;
158
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159 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
160 return -ENODEV;
161
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162 spin_lock_irqsave(&fsl_lbc_lock, flags);
163
3ab8f2a2 164 out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
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165
166 switch (upm->width) {
167 case 8:
168 out_8(io_base, 0x0);
169 break;
170 case 16:
171 out_be16(io_base, 0x0);
172 break;
173 case 32:
174 out_be32(io_base, 0x0);
175 break;
176 default:
177 ret = -EINVAL;
178 break;
179 }
180
181 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
182
183 return ret;
184}
185EXPORT_SYMBOL(fsl_upm_run_pattern);
3ab8f2a2 186
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187static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
188 struct device_node *node)
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189{
190 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
191
192 /* clear event registers */
193 setbits32(&lbc->ltesr, LTESR_CLEAR);
194 out_be32(&lbc->lteatr, 0);
195 out_be32(&lbc->ltear, 0);
196 out_be32(&lbc->lteccr, LTECCR_CLEAR);
197 out_be32(&lbc->ltedr, LTEDR_ENABLE);
198
199 /* Enable interrupts for any detected events */
200 out_be32(&lbc->lteir, LTEIR_ENABLE);
201
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202 /* Set the monitor timeout value to the maximum for erratum A001 */
203 if (of_device_is_compatible(node, "fsl,elbc"))
204 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
205
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206 return 0;
207}
208
209/*
210 * NOTE: This interrupt is used to report localbus events of various kinds,
211 * such as transaction errors on the chipselects.
212 */
213
214static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
215{
216 struct fsl_lbc_ctrl *ctrl = data;
217 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
218 u32 status;
219
220 status = in_be32(&lbc->ltesr);
221 if (!status)
222 return IRQ_NONE;
223
224 out_be32(&lbc->ltesr, LTESR_CLEAR);
225 out_be32(&lbc->lteatr, 0);
226 out_be32(&lbc->ltear, 0);
227 ctrl->irq_status = status;
228
229 if (status & LTESR_BM)
230 dev_err(ctrl->dev, "Local bus monitor time-out: "
231 "LTESR 0x%08X\n", status);
232 if (status & LTESR_WP)
233 dev_err(ctrl->dev, "Write protect error: "
234 "LTESR 0x%08X\n", status);
235 if (status & LTESR_ATMW)
236 dev_err(ctrl->dev, "Atomic write error: "
237 "LTESR 0x%08X\n", status);
238 if (status & LTESR_ATMR)
239 dev_err(ctrl->dev, "Atomic read error: "
240 "LTESR 0x%08X\n", status);
241 if (status & LTESR_CS)
242 dev_err(ctrl->dev, "Chip select error: "
243 "LTESR 0x%08X\n", status);
244 if (status & LTESR_UPM)
245 ;
246 if (status & LTESR_FCT) {
247 dev_err(ctrl->dev, "FCM command time-out: "
248 "LTESR 0x%08X\n", status);
249 smp_wmb();
250 wake_up(&ctrl->irq_wait);
251 }
252 if (status & LTESR_PAR) {
253 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
254 "LTESR 0x%08X\n", status);
255 smp_wmb();
256 wake_up(&ctrl->irq_wait);
257 }
258 if (status & LTESR_CC) {
259 smp_wmb();
260 wake_up(&ctrl->irq_wait);
261 }
262 if (status & ~LTESR_MASK)
263 dev_err(ctrl->dev, "Unknown error: "
264 "LTESR 0x%08X\n", status);
265 return IRQ_HANDLED;
266}
267
268/*
269 * fsl_lbc_ctrl_probe
270 *
271 * called by device layer when it finds a device matching
272 * one our driver can handled. This code allocates all of
273 * the resources needed for the controller only. The
274 * resources for the NAND banks themselves are allocated
275 * in the chip probe function.
276*/
277
278static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
279{
280 int ret;
281
282 if (!dev->dev.of_node) {
283 dev_err(&dev->dev, "Device OF-Node is NULL");
284 return -EFAULT;
285 }
286
287 fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
288 if (!fsl_lbc_ctrl_dev)
289 return -ENOMEM;
290
291 dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
292
293 spin_lock_init(&fsl_lbc_ctrl_dev->lock);
294 init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
295
296 fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
297 if (!fsl_lbc_ctrl_dev->regs) {
298 dev_err(&dev->dev, "failed to get memory region\n");
299 ret = -ENODEV;
300 goto err;
301 }
302
303 fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
304 if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
305 dev_err(&dev->dev, "failed to get irq resource\n");
306 ret = -ENODEV;
307 goto err;
308 }
309
310 fsl_lbc_ctrl_dev->dev = &dev->dev;
311
d08e4457 312 ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
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313 if (ret < 0)
314 goto err;
315
316 ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
317 "fsl-lbc", fsl_lbc_ctrl_dev);
318 if (ret != 0) {
319 dev_err(&dev->dev, "failed to install irq (%d)\n",
320 fsl_lbc_ctrl_dev->irq);
321 ret = fsl_lbc_ctrl_dev->irq;
322 goto err;
323 }
324
325 return 0;
326
327err:
328 iounmap(fsl_lbc_ctrl_dev->regs);
329 kfree(fsl_lbc_ctrl_dev);
330 return ret;
331}
332
333static const struct of_device_id fsl_lbc_match[] = {
334 { .compatible = "fsl,elbc", },
335 { .compatible = "fsl,pq3-localbus", },
336 { .compatible = "fsl,pq2-localbus", },
337 { .compatible = "fsl,pq2pro-localbus", },
338 {},
339};
340
341static struct platform_driver fsl_lbc_ctrl_driver = {
342 .driver = {
343 .name = "fsl-lbc",
344 .of_match_table = fsl_lbc_match,
345 },
346 .probe = fsl_lbc_ctrl_probe,
347};
348
349static int __init fsl_lbc_init(void)
350{
351 return platform_driver_register(&fsl_lbc_ctrl_driver);
352}
353module_init(fsl_lbc_init);