Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation | |
69376502 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
69376502 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
69376502 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
6dee3fb9 | 20 | #include <linux/delay.h> |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/list.h> | |
1da177e4 LT |
23 | #include <linux/pci.h> |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/rbtree.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/spinlock.h> | |
69376502 | 28 | #include <asm/atomic.h> |
1da177e4 | 29 | #include <asm/eeh.h> |
172ca926 | 30 | #include <asm/eeh_event.h> |
1da177e4 LT |
31 | #include <asm/io.h> |
32 | #include <asm/machdep.h> | |
172ca926 | 33 | #include <asm/ppc-pci.h> |
1da177e4 | 34 | #include <asm/rtas.h> |
1da177e4 LT |
35 | |
36 | #undef DEBUG | |
37 | ||
38 | /** Overview: | |
39 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
40 | * dealing with PCI bus errors that can't be dealt with within the | |
41 | * usual PCI framework, except by check-stopping the CPU. Systems | |
42 | * that are designed for high-availability/reliability cannot afford | |
43 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
44 | * An EEH-capable bridge operates by converting a detected error | |
45 | * into a "slot freeze", taking the PCI adapter off-line, making | |
46 | * the slot behave, from the OS'es point of view, as if the slot | |
47 | * were "empty": all reads return 0xff's and all writes are silently | |
48 | * ignored. EEH slot isolation events can be triggered by parity | |
49 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
50 | * which in turn might be caused by low voltage on the bus, dust, |
51 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
52 | * |
53 | * Note, however, that one of the leading causes of EEH slot | |
54 | * freeze events are buggy device drivers, buggy device microcode, | |
55 | * or buggy device hardware. This is because any attempt by the | |
56 | * device to bus-master data to a memory address that is not | |
57 | * assigned to the device will trigger a slot freeze. (The idea | |
58 | * is to prevent devices-gone-wild from corrupting system memory). | |
59 | * Buggy hardware/drivers will have a miserable time co-existing | |
60 | * with EEH. | |
61 | * | |
62 | * Ideally, a PCI device driver, when suspecting that an isolation | |
63 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
64 | * whether this is the case, and then take appropriate steps to | |
65 | * reset the PCI slot, the PCI device, and then resume operations. | |
66 | * However, until that day, the checking is done here, with the | |
67 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
68 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
69 | * and sent out for processing. | |
70 | */ | |
71 | ||
5c1344e9 | 72 | /* If a device driver keeps reading an MMIO register in an interrupt |
1da177e4 LT |
73 | * handler after a slot isolation event has occurred, we assume it |
74 | * is broken and panic. This sets the threshold for how many read | |
75 | * attempts we allow before panicking. | |
76 | */ | |
5c1344e9 | 77 | #define EEH_MAX_FAILS 100000 |
1da177e4 LT |
78 | |
79 | /* RTAS tokens */ | |
80 | static int ibm_set_eeh_option; | |
81 | static int ibm_set_slot_reset; | |
82 | static int ibm_read_slot_reset_state; | |
83 | static int ibm_read_slot_reset_state2; | |
84 | static int ibm_slot_error_detail; | |
25e591f6 | 85 | static int ibm_get_config_addr_info; |
21e464dd | 86 | static int ibm_configure_bridge; |
1da177e4 | 87 | |
1e28a7dd DW |
88 | int eeh_subsystem_enabled; |
89 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 90 | |
fd761fd8 LV |
91 | /* Lock to avoid races due to multiple reports of an error */ |
92 | static DEFINE_SPINLOCK(confirm_error_lock); | |
93 | ||
1da177e4 LT |
94 | /* Buffer for reporting slot-error-detail rtas calls */ |
95 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; | |
96 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
97 | static int eeh_error_buf_size; | |
98 | ||
99 | /* System monitoring statistics */ | |
257ffc64 LV |
100 | static unsigned long no_device; |
101 | static unsigned long no_dn; | |
102 | static unsigned long no_cfg_addr; | |
103 | static unsigned long ignored_check; | |
104 | static unsigned long total_mmio_ffs; | |
105 | static unsigned long false_positives; | |
106 | static unsigned long ignored_failures; | |
107 | static unsigned long slot_resets; | |
1da177e4 | 108 | |
7684b40c LV |
109 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
110 | ||
1da177e4 | 111 | /* --------------------------------------------------------------- */ |
5d5a0936 | 112 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 113 | |
df7242b1 LV |
114 | void eeh_slot_error_detail (struct pci_dn *pdn, int severity) |
115 | { | |
fcb7543e | 116 | int config_addr; |
df7242b1 LV |
117 | unsigned long flags; |
118 | int rc; | |
119 | ||
120 | /* Log the error with the rtas logger */ | |
121 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
122 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
123 | ||
fcb7543e LV |
124 | /* Use PE configuration address, if present */ |
125 | config_addr = pdn->eeh_config_addr; | |
126 | if (pdn->eeh_pe_config_addr) | |
127 | config_addr = pdn->eeh_pe_config_addr; | |
128 | ||
df7242b1 | 129 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 130 | 8, 1, NULL, config_addr, |
df7242b1 LV |
131 | BUID_HI(pdn->phb->buid), |
132 | BUID_LO(pdn->phb->buid), NULL, 0, | |
133 | virt_to_phys(slot_errbuf), | |
134 | eeh_error_buf_size, | |
135 | severity); | |
136 | ||
137 | if (rc == 0) | |
138 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
139 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
140 | } | |
141 | ||
1da177e4 LT |
142 | /** |
143 | * read_slot_reset_state - Read the reset state of a device node's slot | |
144 | * @dn: device node to read | |
145 | * @rets: array to return results in | |
146 | */ | |
69376502 | 147 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
148 | { |
149 | int token, outputs; | |
fcb7543e | 150 | int config_addr; |
1da177e4 LT |
151 | |
152 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
153 | token = ibm_read_slot_reset_state2; | |
154 | outputs = 4; | |
155 | } else { | |
156 | token = ibm_read_slot_reset_state; | |
69376502 | 157 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
158 | outputs = 3; |
159 | } | |
160 | ||
fcb7543e LV |
161 | /* Use PE configuration address, if present */ |
162 | config_addr = pdn->eeh_config_addr; | |
163 | if (pdn->eeh_pe_config_addr) | |
164 | config_addr = pdn->eeh_pe_config_addr; | |
165 | ||
166 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 167 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | /** |
171 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 172 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
173 | */ |
174 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
175 | { | |
176 | pte_t *ptep; | |
177 | unsigned long pa; | |
178 | ||
20cee16c | 179 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
180 | if (!ptep) |
181 | return token; | |
182 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
183 | ||
184 | return pa | (token & (PAGE_SIZE-1)); | |
185 | } | |
186 | ||
fd761fd8 LV |
187 | /** |
188 | * Return the "partitionable endpoint" (pe) under which this device lies | |
189 | */ | |
9fb40eb8 | 190 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
191 | { |
192 | while ((dn->parent) && PCI_DN(dn->parent) && | |
193 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
194 | dn = dn->parent; | |
195 | } | |
196 | return dn; | |
197 | } | |
198 | ||
199 | /** Mark all devices that are peers of this device as failed. | |
200 | * Mark the device driver too, so that it can see the failure | |
201 | * immediately; this is critical, since some drivers poll | |
202 | * status registers in interrupts ... If a driver is polling, | |
203 | * and the slot is frozen, then the driver can deadlock in | |
204 | * an interrupt context, which is bad. | |
205 | */ | |
206 | ||
d9564ad1 | 207 | static void __eeh_mark_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
208 | { |
209 | while (dn) { | |
d9564ad1 | 210 | if (PCI_DN(dn)) { |
77bd7415 LV |
211 | /* Mark the pci device driver too */ |
212 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
213 | |
214 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
215 | ||
77bd7415 LV |
216 | if (dev && dev->driver) |
217 | dev->error_state = pci_channel_io_frozen; | |
218 | ||
d9564ad1 LV |
219 | if (dn->child) |
220 | __eeh_mark_slot (dn->child, mode_flag); | |
221 | } | |
fd761fd8 LV |
222 | dn = dn->sibling; |
223 | } | |
224 | } | |
225 | ||
d9564ad1 LV |
226 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
227 | { | |
022d51b1 | 228 | struct pci_dev *dev; |
d9564ad1 | 229 | dn = find_device_pe (dn); |
3914ac7b LV |
230 | |
231 | /* Back up one, since config addrs might be shared */ | |
232 | if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr) | |
233 | dn = dn->parent; | |
234 | ||
d9564ad1 | 235 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
236 | |
237 | /* Mark the pci device too */ | |
238 | dev = PCI_DN(dn)->pcidev; | |
239 | if (dev) | |
240 | dev->error_state = pci_channel_io_frozen; | |
241 | ||
d9564ad1 LV |
242 | __eeh_mark_slot (dn->child, mode_flag); |
243 | } | |
244 | ||
245 | static void __eeh_clear_slot (struct device_node *dn, int mode_flag) | |
fd761fd8 LV |
246 | { |
247 | while (dn) { | |
d9564ad1 LV |
248 | if (PCI_DN(dn)) { |
249 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
250 | PCI_DN(dn)->eeh_check_count = 0; | |
251 | if (dn->child) | |
252 | __eeh_clear_slot (dn->child, mode_flag); | |
253 | } | |
fd761fd8 LV |
254 | dn = dn->sibling; |
255 | } | |
256 | } | |
257 | ||
d9564ad1 | 258 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
259 | { |
260 | unsigned long flags; | |
261 | spin_lock_irqsave(&confirm_error_lock, flags); | |
3914ac7b | 262 | |
d9564ad1 | 263 | dn = find_device_pe (dn); |
3914ac7b LV |
264 | |
265 | /* Back up one, since config addrs might be shared */ | |
266 | if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr) | |
267 | dn = dn->parent; | |
268 | ||
d9564ad1 LV |
269 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
270 | PCI_DN(dn)->eeh_check_count = 0; | |
271 | __eeh_clear_slot (dn->child, mode_flag); | |
fd761fd8 LV |
272 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
273 | } | |
274 | ||
1da177e4 LT |
275 | /** |
276 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
277 | * @dn device node | |
278 | * @dev pci device, if known | |
279 | * | |
280 | * Check for an EEH failure for the given device node. Call this | |
281 | * routine if the result of a read was all 0xff's and you want to | |
282 | * find out if this is due to an EEH slot freeze. This routine | |
283 | * will query firmware for the EEH status. | |
284 | * | |
285 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 286 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
287 | * |
288 | * It is safe to call this routine in an interrupt context. | |
289 | */ | |
290 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
291 | { | |
292 | int ret; | |
293 | int rets[3]; | |
294 | unsigned long flags; | |
1635317f | 295 | struct pci_dn *pdn; |
77bd7415 | 296 | enum pci_channel_state state; |
fd761fd8 | 297 | int rc = 0; |
1da177e4 | 298 | |
257ffc64 | 299 | total_mmio_ffs++; |
1da177e4 LT |
300 | |
301 | if (!eeh_subsystem_enabled) | |
302 | return 0; | |
303 | ||
177bc936 | 304 | if (!dn) { |
257ffc64 | 305 | no_dn++; |
1da177e4 | 306 | return 0; |
177bc936 | 307 | } |
69376502 | 308 | pdn = PCI_DN(dn); |
1da177e4 LT |
309 | |
310 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 311 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 312 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 313 | ignored_check++; |
177bc936 | 314 | #ifdef DEBUG |
f8632c82 LV |
315 | printk ("EEH:ignored check (%x) for %s %s\n", |
316 | pdn->eeh_mode, pci_name (dev), dn->full_name); | |
177bc936 | 317 | #endif |
1da177e4 LT |
318 | return 0; |
319 | } | |
320 | ||
fcb7543e | 321 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 322 | no_cfg_addr++; |
1da177e4 LT |
323 | return 0; |
324 | } | |
325 | ||
fd761fd8 LV |
326 | /* If we already have a pending isolation event for this |
327 | * slot, we know it's bad already, we don't need to check. | |
328 | * Do this checking under a lock; as multiple PCI devices | |
329 | * in one slot might report errors simultaneously, and we | |
330 | * only want one error recovery routine running. | |
1da177e4 | 331 | */ |
fd761fd8 LV |
332 | spin_lock_irqsave(&confirm_error_lock, flags); |
333 | rc = 1; | |
1635317f | 334 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 LV |
335 | pdn->eeh_check_count ++; |
336 | if (pdn->eeh_check_count >= EEH_MAX_FAILS) { | |
337 | printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n", | |
338 | pdn->eeh_check_count); | |
339 | dump_stack(); | |
d0e70341 | 340 | msleep(5000); |
5c1344e9 | 341 | |
1da177e4 | 342 | /* re-read the slot reset state */ |
69376502 | 343 | if (read_slot_reset_state(pdn, rets) != 0) |
1da177e4 | 344 | rets[0] = -1; /* reset state unknown */ |
5c1344e9 LV |
345 | |
346 | /* If we are here, then we hit an infinite loop. Stop. */ | |
347 | panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev)); | |
1da177e4 | 348 | } |
fd761fd8 | 349 | goto dn_unlock; |
1da177e4 LT |
350 | } |
351 | ||
352 | /* | |
353 | * Now test for an EEH failure. This is VERY expensive. | |
354 | * Note that the eeh_config_addr may be a parent device | |
355 | * in the case of a device behind a bridge, or it may be | |
356 | * function zero of a multi-function device. | |
357 | * In any case they must share a common PHB. | |
358 | */ | |
69376502 | 359 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
360 | |
361 | /* If the call to firmware failed, punt */ | |
362 | if (ret != 0) { | |
363 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
364 | ret, dn->full_name); | |
257ffc64 | 365 | false_positives++; |
fd761fd8 LV |
366 | rc = 0; |
367 | goto dn_unlock; | |
76e6faf7 LV |
368 | } |
369 | ||
39d16e29 LV |
370 | /* Note that config-io to empty slots may fail; |
371 | * they are empty when they don't have children. */ | |
372 | if ((rets[0] == 5) && (dn->child == NULL)) { | |
373 | false_positives++; | |
374 | rc = 0; | |
375 | goto dn_unlock; | |
376 | } | |
377 | ||
76e6faf7 LV |
378 | /* If EEH is not supported on this device, punt. */ |
379 | if (rets[1] != 1) { | |
380 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
381 | ret, dn->full_name); | |
257ffc64 | 382 | false_positives++; |
fd761fd8 LV |
383 | rc = 0; |
384 | goto dn_unlock; | |
76e6faf7 LV |
385 | } |
386 | ||
387 | /* If not the kind of error we know about, punt. */ | |
388 | if (rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { | |
257ffc64 | 389 | false_positives++; |
fd761fd8 LV |
390 | rc = 0; |
391 | goto dn_unlock; | |
76e6faf7 LV |
392 | } |
393 | ||
257ffc64 | 394 | slot_resets++; |
fd761fd8 LV |
395 | |
396 | /* Avoid repeated reports of this failure, including problems | |
397 | * with other functions on this device, and functions under | |
398 | * bridges. */ | |
d9564ad1 | 399 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
fd761fd8 | 400 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 401 | |
77bd7415 LV |
402 | state = pci_channel_io_normal; |
403 | if ((rets[0] == 2) || (rets[0] == 4)) | |
404 | state = pci_channel_io_frozen; | |
405 | if (rets[0] == 5) | |
406 | state = pci_channel_io_perm_failure; | |
407 | eeh_send_failure_event (dn, dev, state, rets[2]); | |
408 | ||
1da177e4 LT |
409 | /* Most EEH events are due to device driver bugs. Having |
410 | * a stack trace will help the device-driver authors figure | |
411 | * out what happened. So print that out. */ | |
76e6faf7 | 412 | if (rets[0] != 5) dump_stack(); |
fd761fd8 LV |
413 | return 1; |
414 | ||
415 | dn_unlock: | |
416 | spin_unlock_irqrestore(&confirm_error_lock, flags); | |
417 | return rc; | |
1da177e4 LT |
418 | } |
419 | ||
fd761fd8 | 420 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
421 | |
422 | /** | |
423 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
424 | * @token i/o token, should be address in the form 0xA.... | |
425 | * @val value, should be all 1's (XXX why do we need this arg??) | |
426 | * | |
1da177e4 LT |
427 | * Check for an EEH failure at the given token address. Call this |
428 | * routine if the result of a read was all 0xff's and you want to | |
429 | * find out if this is due to an EEH slot freeze event. This routine | |
430 | * will query firmware for the EEH status. | |
431 | * | |
432 | * Note this routine is safe to call in an interrupt context. | |
433 | */ | |
434 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
435 | { | |
436 | unsigned long addr; | |
437 | struct pci_dev *dev; | |
438 | struct device_node *dn; | |
439 | ||
440 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
441 | addr = eeh_token_to_phys((unsigned long __force) token); | |
442 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 443 | if (!dev) { |
257ffc64 | 444 | no_device++; |
1da177e4 | 445 | return val; |
177bc936 | 446 | } |
1da177e4 LT |
447 | |
448 | dn = pci_device_to_OF_node(dev); | |
449 | eeh_dn_check_failure (dn, dev); | |
450 | ||
451 | pci_dev_put(dev); | |
452 | return val; | |
453 | } | |
454 | ||
455 | EXPORT_SYMBOL(eeh_check_failure); | |
456 | ||
6dee3fb9 LV |
457 | /* ------------------------------------------------------------- */ |
458 | /* The code below deals with error recovery */ | |
459 | ||
cb5b5624 LV |
460 | /** |
461 | * eeh_slot_availability - returns error status of slot | |
462 | * @pdn pci device node | |
463 | * | |
464 | * Return negative value if a permanent error, else return | |
6dee3fb9 LV |
465 | * a number of milliseconds to wait until the PCI slot is |
466 | * ready to be used. | |
467 | */ | |
468 | static int | |
469 | eeh_slot_availability(struct pci_dn *pdn) | |
470 | { | |
471 | int rc; | |
472 | int rets[3]; | |
473 | ||
474 | rc = read_slot_reset_state(pdn, rets); | |
475 | ||
476 | if (rc) return rc; | |
477 | ||
478 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
b6495c0c | 479 | if (rets[0] == 0) return 0; /* Oll Korrect */ |
6dee3fb9 LV |
480 | if (rets[0] == 5) { |
481 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
482 | return rets[2]; /* number of millisecs to wait */ | |
483 | } | |
b6495c0c LV |
484 | if (rets[0] == 1) |
485 | return 250; | |
486 | ||
487 | printk (KERN_ERR "EEH: Slot unavailable: rc=%d, rets=%d %d %d\n", | |
488 | rc, rets[0], rets[1], rets[2]); | |
e1029263 | 489 | return -2; |
6dee3fb9 LV |
490 | } |
491 | ||
47b5c838 LV |
492 | /** |
493 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
494 | * @pdn pci device node | |
495 | */ | |
496 | ||
497 | int | |
498 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
499 | { | |
500 | int config_addr; | |
501 | int rc; | |
502 | ||
503 | /* Use PE configuration address, if present */ | |
504 | config_addr = pdn->eeh_config_addr; | |
505 | if (pdn->eeh_pe_config_addr) | |
506 | config_addr = pdn->eeh_pe_config_addr; | |
507 | ||
508 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
509 | config_addr, | |
510 | BUID_HI(pdn->phb->buid), | |
511 | BUID_LO(pdn->phb->buid), | |
512 | function); | |
513 | ||
514 | if (rc) | |
515 | printk(KERN_WARNING "EEH: Cannot enable function %d, err=%d dn=%s\n", | |
516 | function, rc, pdn->node->full_name); | |
517 | ||
518 | return rc; | |
519 | } | |
520 | ||
cb5b5624 LV |
521 | /** |
522 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
523 | * @pdn pci device node | |
524 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
525 | * |
526 | * Clear the EEH-frozen condition on a slot. This routine | |
527 | * asserts the PCI #RST line if the 'state' argument is '1', | |
528 | * and drops the #RST line if 'state is '0'. This routine is | |
529 | * safe to call in an interrupt context. | |
530 | * | |
531 | */ | |
532 | ||
533 | static void | |
534 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
535 | { | |
25e591f6 | 536 | int config_addr; |
6dee3fb9 LV |
537 | int rc; |
538 | ||
539 | BUG_ON (pdn==NULL); | |
540 | ||
541 | if (!pdn->phb) { | |
542 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
543 | pdn->node->full_name); | |
544 | return; | |
545 | } | |
546 | ||
25e591f6 LV |
547 | /* Use PE configuration address, if present */ |
548 | config_addr = pdn->eeh_config_addr; | |
549 | if (pdn->eeh_pe_config_addr) | |
550 | config_addr = pdn->eeh_pe_config_addr; | |
551 | ||
6dee3fb9 | 552 | rc = rtas_call(ibm_set_slot_reset,4,1, NULL, |
25e591f6 | 553 | config_addr, |
6dee3fb9 LV |
554 | BUID_HI(pdn->phb->buid), |
555 | BUID_LO(pdn->phb->buid), | |
556 | state); | |
e1029263 LV |
557 | if (rc) |
558 | printk (KERN_WARNING "EEH: Unable to reset the failed slot," | |
559 | " (%d) #RST=%d dn=%s\n", | |
6dee3fb9 | 560 | rc, state, pdn->node->full_name); |
6dee3fb9 LV |
561 | } |
562 | ||
cb5b5624 LV |
563 | /** |
564 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
565 | * @pdn: pci device node to be reset. | |
b6495c0c LV |
566 | * |
567 | * Return 0 if success, else a non-zero value. | |
6dee3fb9 LV |
568 | */ |
569 | ||
e1029263 | 570 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 571 | { |
6dee3fb9 LV |
572 | rtas_pci_slot_reset (pdn, 1); |
573 | ||
574 | /* The PCI bus requires that the reset be held high for at least | |
575 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
576 | ||
577 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
578 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
579 | |
580 | /* We might get hit with another EEH freeze as soon as the | |
581 | * pci slot reset line is dropped. Make sure we don't miss | |
582 | * these, and clear the flag now. */ | |
583 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
584 | ||
6dee3fb9 LV |
585 | rtas_pci_slot_reset (pdn, 0); |
586 | ||
587 | /* After a PCI slot has been reset, the PCI Express spec requires | |
588 | * a 1.5 second idle time for the bus to stabilize, before starting | |
589 | * up traffic. */ | |
590 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
591 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
592 | } |
593 | ||
594 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
595 | { | |
596 | int i, rc; | |
597 | ||
598 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 LV |
599 | |
600 | /* Now double check with the firmware to make sure the device is | |
601 | * ready to be used; if not, wait for recovery. */ | |
602 | for (i=0; i<10; i++) { | |
603 | rc = eeh_slot_availability (pdn); | |
b6495c0c LV |
604 | if (rc == 0) |
605 | return 0; | |
e1029263 LV |
606 | |
607 | if (rc == -2) { | |
608 | printk (KERN_ERR "EEH: failed (%d) to reset slot %s\n", | |
609 | i, pdn->node->full_name); | |
610 | __rtas_set_slot_reset(pdn); | |
611 | continue; | |
612 | } | |
613 | ||
614 | if (rc < 0) { | |
615 | printk (KERN_ERR "EEH: unrecoverable slot failure %s\n", | |
616 | pdn->node->full_name); | |
b6495c0c | 617 | return -1; |
e1029263 | 618 | } |
6dee3fb9 LV |
619 | |
620 | msleep (rc+100); | |
621 | } | |
b6495c0c LV |
622 | |
623 | rc = eeh_slot_availability (pdn); | |
624 | if (rc) | |
625 | printk (KERN_ERR "EEH: timeout resetting slot %s\n", pdn->node->full_name); | |
626 | ||
627 | return rc; | |
6dee3fb9 LV |
628 | } |
629 | ||
8b553f32 LV |
630 | /* ------------------------------------------------------- */ |
631 | /** Save and restore of PCI BARs | |
632 | * | |
633 | * Although firmware will set up BARs during boot, it doesn't | |
634 | * set up device BAR's after a device reset, although it will, | |
635 | * if requested, set up bridge configuration. Thus, we need to | |
636 | * configure the PCI devices ourselves. | |
637 | */ | |
638 | ||
639 | /** | |
640 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
641 | * @pdn: pci device node |
642 | * | |
8b553f32 LV |
643 | * Loads the PCI configuration space base address registers, |
644 | * the expansion ROM base address, the latency timer, and etc. | |
645 | * from the saved values in the device node. | |
646 | */ | |
647 | static inline void __restore_bars (struct pci_dn *pdn) | |
648 | { | |
649 | int i; | |
650 | ||
651 | if (NULL==pdn->phb) return; | |
652 | for (i=4; i<10; i++) { | |
653 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
654 | } | |
655 | ||
656 | /* 12 == Expansion ROM Address */ | |
657 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
658 | ||
659 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
660 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
661 | ||
662 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
663 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
664 | ||
665 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
666 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
667 | ||
668 | /* max latency, min grant, interrupt pin and line */ | |
669 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
670 | } | |
671 | ||
672 | /** | |
673 | * eeh_restore_bars - restore the PCI config space info | |
674 | * | |
675 | * This routine performs a recursive walk to the children | |
676 | * of this device as well. | |
677 | */ | |
678 | void eeh_restore_bars(struct pci_dn *pdn) | |
679 | { | |
680 | struct device_node *dn; | |
681 | if (!pdn) | |
682 | return; | |
683 | ||
7684b40c | 684 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
685 | __restore_bars (pdn); |
686 | ||
687 | dn = pdn->node->child; | |
688 | while (dn) { | |
689 | eeh_restore_bars (PCI_DN(dn)); | |
690 | dn = dn->sibling; | |
691 | } | |
692 | } | |
693 | ||
694 | /** | |
695 | * eeh_save_bars - save device bars | |
696 | * | |
697 | * Save the values of the device bars. Unlike the restore | |
698 | * routine, this routine is *not* recursive. This is because | |
699 | * PCI devices are added individuallly; but, for the restore, | |
700 | * an entire slot is reset at a time. | |
701 | */ | |
7684b40c | 702 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
703 | { |
704 | int i; | |
705 | ||
7684b40c | 706 | if (!pdn ) |
8b553f32 LV |
707 | return; |
708 | ||
709 | for (i = 0; i < 16; i++) | |
7684b40c | 710 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
711 | } |
712 | ||
713 | void | |
714 | rtas_configure_bridge(struct pci_dn *pdn) | |
715 | { | |
fcb7543e | 716 | int config_addr; |
8b553f32 LV |
717 | int rc; |
718 | ||
fcb7543e LV |
719 | /* Use PE configuration address, if present */ |
720 | config_addr = pdn->eeh_config_addr; | |
721 | if (pdn->eeh_pe_config_addr) | |
722 | config_addr = pdn->eeh_pe_config_addr; | |
723 | ||
21e464dd | 724 | rc = rtas_call(ibm_configure_bridge,3,1, NULL, |
fcb7543e | 725 | config_addr, |
8b553f32 LV |
726 | BUID_HI(pdn->phb->buid), |
727 | BUID_LO(pdn->phb->buid)); | |
728 | if (rc) { | |
729 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
730 | rc, pdn->node->full_name); | |
731 | } | |
732 | } | |
733 | ||
172ca926 LV |
734 | /* ------------------------------------------------------------- */ |
735 | /* The code below deals with enabling EEH for devices during the | |
736 | * early boot sequence. EEH must be enabled before any PCI probing | |
737 | * can be done. | |
738 | */ | |
739 | ||
740 | #define EEH_ENABLE 1 | |
741 | ||
1da177e4 LT |
742 | struct eeh_early_enable_info { |
743 | unsigned int buid_hi; | |
744 | unsigned int buid_lo; | |
745 | }; | |
746 | ||
747 | /* Enable eeh for the given device node. */ | |
748 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
749 | { | |
25c4a46f | 750 | unsigned int rets[3]; |
1da177e4 LT |
751 | struct eeh_early_enable_info *info = data; |
752 | int ret; | |
954a46e2 JK |
753 | const char *status = get_property(dn, "status", NULL); |
754 | const u32 *class_code = get_property(dn, "class-code", NULL); | |
755 | const u32 *vendor_id = get_property(dn, "vendor-id", NULL); | |
756 | const u32 *device_id = get_property(dn, "device-id", NULL); | |
757 | const u32 *regs; | |
1da177e4 | 758 | int enable; |
69376502 | 759 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 760 | |
0f17574a | 761 | pdn->class_code = 0; |
1635317f | 762 | pdn->eeh_mode = 0; |
5c1344e9 LV |
763 | pdn->eeh_check_count = 0; |
764 | pdn->eeh_freeze_count = 0; | |
1da177e4 LT |
765 | |
766 | if (status && strcmp(status, "ok") != 0) | |
767 | return NULL; /* ignore devices with bad status */ | |
768 | ||
769 | /* Ignore bad nodes. */ | |
770 | if (!class_code || !vendor_id || !device_id) | |
771 | return NULL; | |
772 | ||
773 | /* There is nothing to check on PCI to ISA bridges */ | |
774 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 775 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
776 | return NULL; |
777 | } | |
0f17574a | 778 | pdn->class_code = *class_code; |
1da177e4 LT |
779 | |
780 | /* | |
781 | * Now decide if we are going to "Disable" EEH checking | |
782 | * for this device. We still run with the EEH hardware active, | |
783 | * but we won't be checking for ff's. This means a driver | |
784 | * could return bad data (very bad!), an interrupt handler could | |
785 | * hang waiting on status bits that won't change, etc. | |
786 | * But there are a few cases like display devices that make sense. | |
787 | */ | |
788 | enable = 1; /* i.e. we will do checking */ | |
77bd7415 | 789 | #if 0 |
1da177e4 LT |
790 | if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) |
791 | enable = 0; | |
77bd7415 | 792 | #endif |
1da177e4 LT |
793 | |
794 | if (!enable) | |
1635317f | 795 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
796 | |
797 | /* Ok... see if this device supports EEH. Some do, some don't, | |
798 | * and the only way to find out is to check each and every one. */ | |
954a46e2 | 799 | regs = get_property(dn, "reg", NULL); |
1da177e4 LT |
800 | if (regs) { |
801 | /* First register entry is addr (00BBSS00) */ | |
802 | /* Try to enable eeh */ | |
803 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
804 | regs[0], info->buid_hi, info->buid_lo, |
805 | EEH_ENABLE); | |
806 | ||
25c4a46f | 807 | enable = 0; |
1da177e4 | 808 | if (ret == 0) { |
1635317f | 809 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
810 | |
811 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
812 | * then use that instead. */ | |
813 | pdn->eeh_pe_config_addr = 0; | |
814 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
25e591f6 LV |
815 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, |
816 | pdn->eeh_config_addr, | |
817 | info->buid_hi, info->buid_lo, | |
818 | 0); | |
819 | if (ret == 0) | |
820 | pdn->eeh_pe_config_addr = rets[0]; | |
821 | } | |
25c4a46f LV |
822 | |
823 | /* Some older systems (Power4) allow the | |
824 | * ibm,set-eeh-option call to succeed even on nodes | |
825 | * where EEH is not supported. Verify support | |
826 | * explicitly. */ | |
827 | ret = read_slot_reset_state(pdn, rets); | |
828 | if ((ret == 0) && (rets[1] == 1)) | |
829 | enable = 1; | |
830 | } | |
831 | ||
832 | if (enable) { | |
833 | eeh_subsystem_enabled = 1; | |
834 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
835 | ||
1da177e4 | 836 | #ifdef DEBUG |
25e591f6 LV |
837 | printk(KERN_DEBUG "EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
838 | dn->full_name, pdn->eeh_config_addr, pdn->eeh_pe_config_addr); | |
1da177e4 LT |
839 | #endif |
840 | } else { | |
841 | ||
842 | /* This device doesn't support EEH, but it may have an | |
843 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 844 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 845 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 846 | /* Parent supports EEH. */ |
1635317f PM |
847 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
848 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
849 | return NULL; |
850 | } | |
851 | } | |
852 | } else { | |
853 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
854 | dn->full_name); | |
855 | } | |
856 | ||
7684b40c | 857 | eeh_save_bars(pdn); |
69376502 | 858 | return NULL; |
1da177e4 LT |
859 | } |
860 | ||
861 | /* | |
862 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
863 | * As a side effect we can determine here if eeh is supported at all. | |
864 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
865 | * check. If a user turns off EEH for a particular adapter they are really | |
866 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
867 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
868 | * EEH for all slots/all devices. | |
869 | * | |
870 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
871 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
872 | * newer systems can boot. | |
873 | */ | |
874 | void __init eeh_init(void) | |
875 | { | |
876 | struct device_node *phb, *np; | |
877 | struct eeh_early_enable_info info; | |
878 | ||
fd761fd8 | 879 | spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
880 | spin_lock_init(&slot_errbuf_lock); |
881 | ||
1da177e4 LT |
882 | np = of_find_node_by_path("/rtas"); |
883 | if (np == NULL) | |
884 | return; | |
885 | ||
886 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
887 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
888 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
889 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
890 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 891 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
21e464dd | 892 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
1da177e4 LT |
893 | |
894 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
895 | return; | |
896 | ||
897 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
898 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
899 | eeh_error_buf_size = 1024; | |
900 | } | |
901 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
902 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
903 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
904 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
905 | } | |
906 | ||
907 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
908 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
909 | phb = of_find_node_by_name(phb, "pci")) { | |
910 | unsigned long buid; | |
911 | ||
912 | buid = get_phb_buid(phb); | |
69376502 | 913 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
914 | continue; |
915 | ||
916 | info.buid_lo = BUID_LO(buid); | |
917 | info.buid_hi = BUID_HI(buid); | |
918 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
919 | } | |
920 | ||
921 | if (eeh_subsystem_enabled) | |
922 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
923 | else | |
924 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
925 | } | |
926 | ||
927 | /** | |
928 | * eeh_add_device_early - enable EEH for the indicated device_node | |
929 | * @dn: device node for which to set up EEH | |
930 | * | |
931 | * This routine must be used to perform EEH initialization for PCI | |
932 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
933 | * This routine must be called before any i/o is performed to the | |
934 | * adapter (inluding any config-space i/o). | |
935 | * Whether this actually enables EEH or not for this device depends | |
936 | * on the CEC architecture, type of the device, on earlier boot | |
937 | * command-line arguments & etc. | |
938 | */ | |
794e085e | 939 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
940 | { |
941 | struct pci_controller *phb; | |
942 | struct eeh_early_enable_info info; | |
943 | ||
69376502 | 944 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 945 | return; |
1635317f | 946 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
947 | |
948 | /* USB Bus children of PCI devices will not have BUID's */ | |
949 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 950 | return; |
1da177e4 LT |
951 | |
952 | info.buid_hi = BUID_HI(phb->buid); | |
953 | info.buid_lo = BUID_LO(phb->buid); | |
954 | early_enable_eeh(dn, &info); | |
955 | } | |
1da177e4 | 956 | |
e2a296ee LV |
957 | void eeh_add_device_tree_early(struct device_node *dn) |
958 | { | |
959 | struct device_node *sib; | |
960 | for (sib = dn->child; sib; sib = sib->sibling) | |
961 | eeh_add_device_tree_early(sib); | |
962 | eeh_add_device_early(dn); | |
963 | } | |
964 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
965 | ||
1da177e4 LT |
966 | /** |
967 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
968 | * @dev: pci device for which to set up EEH | |
969 | * | |
970 | * This routine must be used to complete EEH initialization for PCI | |
971 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
972 | */ | |
794e085e | 973 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 974 | { |
56b0fca3 | 975 | struct device_node *dn; |
8b553f32 | 976 | struct pci_dn *pdn; |
56b0fca3 | 977 | |
1da177e4 LT |
978 | if (!dev || !eeh_subsystem_enabled) |
979 | return; | |
980 | ||
981 | #ifdef DEBUG | |
982245f0 | 982 | printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev)); |
1da177e4 LT |
983 | #endif |
984 | ||
56b0fca3 LV |
985 | pci_dev_get (dev); |
986 | dn = pci_device_to_OF_node(dev); | |
8b553f32 LV |
987 | pdn = PCI_DN(dn); |
988 | pdn->pcidev = dev; | |
56b0fca3 | 989 | |
1da177e4 LT |
990 | pci_addr_cache_insert_device (dev); |
991 | } | |
794e085e NF |
992 | |
993 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
994 | { | |
995 | struct pci_dev *dev; | |
996 | ||
997 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
998 | eeh_add_device_late(dev); | |
999 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1000 | struct pci_bus *subbus = dev->subordinate; | |
1001 | if (subbus) | |
1002 | eeh_add_device_tree_late(subbus); | |
1003 | } | |
1004 | } | |
1005 | } | |
1006 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1007 | |
1008 | /** | |
1009 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1010 | * @dev: pci device to be removed | |
1011 | * | |
794e085e NF |
1012 | * This routine should be called when a device is removed from |
1013 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1014 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1015 | * this device will no longer be detected after this call; thus, | |
1016 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1017 | */ |
794e085e | 1018 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1019 | { |
56b0fca3 | 1020 | struct device_node *dn; |
1da177e4 LT |
1021 | if (!dev || !eeh_subsystem_enabled) |
1022 | return; | |
1023 | ||
1024 | /* Unregister the device with the EEH/PCI address search system */ | |
1025 | #ifdef DEBUG | |
982245f0 | 1026 | printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev)); |
1da177e4 LT |
1027 | #endif |
1028 | pci_addr_cache_remove_device(dev); | |
56b0fca3 LV |
1029 | |
1030 | dn = pci_device_to_OF_node(dev); | |
b055a9e1 LV |
1031 | if (PCI_DN(dn)->pcidev) { |
1032 | PCI_DN(dn)->pcidev = NULL; | |
1033 | pci_dev_put (dev); | |
1034 | } | |
1da177e4 | 1035 | } |
1da177e4 | 1036 | |
e2a296ee LV |
1037 | void eeh_remove_bus_device(struct pci_dev *dev) |
1038 | { | |
794e085e NF |
1039 | struct pci_bus *bus = dev->subordinate; |
1040 | struct pci_dev *child, *tmp; | |
1041 | ||
e2a296ee | 1042 | eeh_remove_device(dev); |
794e085e NF |
1043 | |
1044 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1045 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1046 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1047 | } |
1048 | } | |
1049 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1050 | ||
1da177e4 LT |
1051 | static int proc_eeh_show(struct seq_file *m, void *v) |
1052 | { | |
1da177e4 LT |
1053 | if (0 == eeh_subsystem_enabled) { |
1054 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1055 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1056 | } else { |
1057 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1058 | seq_printf(m, |
1059 | "no device=%ld\n" | |
1060 | "no device node=%ld\n" | |
1061 | "no config address=%ld\n" | |
1062 | "check not wanted=%ld\n" | |
1063 | "eeh_total_mmio_ffs=%ld\n" | |
1064 | "eeh_false_positives=%ld\n" | |
1065 | "eeh_ignored_failures=%ld\n" | |
1066 | "eeh_slot_resets=%ld\n", | |
257ffc64 LV |
1067 | no_device, no_dn, no_cfg_addr, |
1068 | ignored_check, total_mmio_ffs, | |
1069 | false_positives, ignored_failures, | |
1070 | slot_resets); | |
1da177e4 LT |
1071 | } |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1077 | { | |
1078 | return single_open(file, proc_eeh_show, NULL); | |
1079 | } | |
1080 | ||
5dfe4c96 | 1081 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1082 | .open = proc_eeh_open, |
1083 | .read = seq_read, | |
1084 | .llseek = seq_lseek, | |
1085 | .release = single_release, | |
1086 | }; | |
1087 | ||
1088 | static int __init eeh_init_proc(void) | |
1089 | { | |
1090 | struct proc_dir_entry *e; | |
1091 | ||
e8222502 | 1092 | if (machine_is(pseries)) { |
1da177e4 LT |
1093 | e = create_proc_entry("ppc64/eeh", 0, NULL); |
1094 | if (e) | |
1095 | e->proc_fops = &proc_eeh_operations; | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | __initcall(eeh_init_proc); |