Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation | |
69376502 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
69376502 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
69376502 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
6dee3fb9 | 20 | #include <linux/delay.h> |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/list.h> | |
1da177e4 LT |
23 | #include <linux/pci.h> |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/rbtree.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/spinlock.h> | |
69376502 | 28 | #include <asm/atomic.h> |
1da177e4 | 29 | #include <asm/eeh.h> |
172ca926 | 30 | #include <asm/eeh_event.h> |
1da177e4 LT |
31 | #include <asm/io.h> |
32 | #include <asm/machdep.h> | |
172ca926 | 33 | #include <asm/ppc-pci.h> |
1da177e4 | 34 | #include <asm/rtas.h> |
1da177e4 LT |
35 | |
36 | #undef DEBUG | |
37 | ||
38 | /** Overview: | |
39 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
40 | * dealing with PCI bus errors that can't be dealt with within the | |
41 | * usual PCI framework, except by check-stopping the CPU. Systems | |
42 | * that are designed for high-availability/reliability cannot afford | |
43 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
44 | * An EEH-capable bridge operates by converting a detected error | |
45 | * into a "slot freeze", taking the PCI adapter off-line, making | |
46 | * the slot behave, from the OS'es point of view, as if the slot | |
47 | * were "empty": all reads return 0xff's and all writes are silently | |
48 | * ignored. EEH slot isolation events can be triggered by parity | |
49 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
50 | * which in turn might be caused by low voltage on the bus, dust, |
51 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
52 | * |
53 | * Note, however, that one of the leading causes of EEH slot | |
54 | * freeze events are buggy device drivers, buggy device microcode, | |
55 | * or buggy device hardware. This is because any attempt by the | |
56 | * device to bus-master data to a memory address that is not | |
57 | * assigned to the device will trigger a slot freeze. (The idea | |
58 | * is to prevent devices-gone-wild from corrupting system memory). | |
59 | * Buggy hardware/drivers will have a miserable time co-existing | |
60 | * with EEH. | |
61 | * | |
62 | * Ideally, a PCI device driver, when suspecting that an isolation | |
63 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
64 | * whether this is the case, and then take appropriate steps to | |
65 | * reset the PCI slot, the PCI device, and then resume operations. | |
66 | * However, until that day, the checking is done here, with the | |
67 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
68 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
69 | * and sent out for processing. | |
70 | */ | |
71 | ||
5c1344e9 | 72 | /* If a device driver keeps reading an MMIO register in an interrupt |
1da177e4 LT |
73 | * handler after a slot isolation event has occurred, we assume it |
74 | * is broken and panic. This sets the threshold for how many read | |
75 | * attempts we allow before panicking. | |
76 | */ | |
2fd30be8 | 77 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 78 | |
17213c3b | 79 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
80 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
81 | ||
1da177e4 LT |
82 | /* RTAS tokens */ |
83 | static int ibm_set_eeh_option; | |
84 | static int ibm_set_slot_reset; | |
85 | static int ibm_read_slot_reset_state; | |
86 | static int ibm_read_slot_reset_state2; | |
87 | static int ibm_slot_error_detail; | |
25e591f6 | 88 | static int ibm_get_config_addr_info; |
147d6a37 | 89 | static int ibm_get_config_addr_info2; |
21e464dd | 90 | static int ibm_configure_bridge; |
1da177e4 | 91 | |
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
fd761fd8 LV |
95 | /* Lock to avoid races due to multiple reports of an error */ |
96 | static DEFINE_SPINLOCK(confirm_error_lock); | |
97 | ||
17213c3b LV |
98 | /* Buffer for reporting slot-error-detail rtas calls. Its here |
99 | * in BSS, and not dynamically alloced, so that it ends up in | |
100 | * RMO where RTAS can access it. | |
101 | */ | |
1da177e4 LT |
102 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; |
103 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
104 | static int eeh_error_buf_size; | |
105 | ||
17213c3b LV |
106 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
107 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
108 | * can access it. | |
109 | */ | |
d99bb1db LV |
110 | #define EEH_PCI_REGS_LOG_LEN 4096 |
111 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
112 | ||
1da177e4 | 113 | /* System monitoring statistics */ |
257ffc64 LV |
114 | static unsigned long no_device; |
115 | static unsigned long no_dn; | |
116 | static unsigned long no_cfg_addr; | |
117 | static unsigned long ignored_check; | |
118 | static unsigned long total_mmio_ffs; | |
119 | static unsigned long false_positives; | |
120 | static unsigned long ignored_failures; | |
121 | static unsigned long slot_resets; | |
1da177e4 | 122 | |
7684b40c LV |
123 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
124 | ||
1da177e4 | 125 | /* --------------------------------------------------------------- */ |
5d5a0936 | 126 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 127 | |
d99bb1db LV |
128 | static void rtas_slot_error_detail(struct pci_dn *pdn, int severity, |
129 | char *driver_log, size_t loglen) | |
df7242b1 | 130 | { |
fcb7543e | 131 | int config_addr; |
df7242b1 LV |
132 | unsigned long flags; |
133 | int rc; | |
134 | ||
135 | /* Log the error with the rtas logger */ | |
136 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
137 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
138 | ||
fcb7543e LV |
139 | /* Use PE configuration address, if present */ |
140 | config_addr = pdn->eeh_config_addr; | |
141 | if (pdn->eeh_pe_config_addr) | |
142 | config_addr = pdn->eeh_pe_config_addr; | |
143 | ||
df7242b1 | 144 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 145 | 8, 1, NULL, config_addr, |
df7242b1 | 146 | BUID_HI(pdn->phb->buid), |
d99bb1db LV |
147 | BUID_LO(pdn->phb->buid), |
148 | virt_to_phys(driver_log), loglen, | |
df7242b1 LV |
149 | virt_to_phys(slot_errbuf), |
150 | eeh_error_buf_size, | |
151 | severity); | |
152 | ||
153 | if (rc == 0) | |
154 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
155 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
156 | } | |
157 | ||
d99bb1db LV |
158 | /** |
159 | * gather_pci_data - copy assorted PCI config space registers to buff | |
160 | * @pdn: device to report data for | |
161 | * @buf: point to buffer in which to log | |
162 | * @len: amount of room in buffer | |
163 | * | |
164 | * This routine captures assorted PCI configuration space data, | |
165 | * and puts them into a buffer for RTAS error logging. | |
166 | */ | |
167 | static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) | |
168 | { | |
169 | u32 cfg; | |
fcf9892b | 170 | int cap, i; |
d99bb1db LV |
171 | int n = 0; |
172 | ||
fcf9892b LV |
173 | n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name); |
174 | printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name); | |
175 | ||
d99bb1db | 176 | rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
177 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
178 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
179 | ||
d99bb1db LV |
180 | rtas_read_config(pdn, PCI_COMMAND, 4, &cfg); |
181 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); | |
fcf9892b LV |
182 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
183 | ||
184 | /* Dump out the PCI-X command and status regs */ | |
185 | cap = pci_find_capability(pdn->pcidev, PCI_CAP_ID_PCIX); | |
186 | if (cap) { | |
187 | rtas_read_config(pdn, cap, 4, &cfg); | |
188 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); | |
189 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
190 | ||
191 | rtas_read_config(pdn, cap+4, 4, &cfg); | |
192 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); | |
193 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
194 | } | |
195 | ||
196 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
197 | cap = pci_find_capability(pdn->pcidev, PCI_CAP_ID_EXP); | |
198 | if (cap) { | |
199 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
200 | printk(KERN_WARNING | |
201 | "EEH: PCI-E capabilities and status follow:\n"); | |
202 | ||
203 | for (i=0; i<=8; i++) { | |
204 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
205 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
206 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
207 | } | |
208 | ||
209 | cap = pci_find_ext_capability(pdn->pcidev,PCI_EXT_CAP_ID_ERR); | |
210 | if (cap) { | |
211 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
212 | printk(KERN_WARNING | |
213 | "EEH: PCI-E AER capability register set follows:\n"); | |
214 | ||
215 | for (i=0; i<14; i++) { | |
216 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
217 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
218 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
219 | } | |
220 | } | |
221 | } | |
d99bb1db LV |
222 | return n; |
223 | } | |
224 | ||
225 | void eeh_slot_error_detail(struct pci_dn *pdn, int severity) | |
226 | { | |
227 | size_t loglen = 0; | |
17213c3b | 228 | pci_regs_buf[0] = 0; |
d99bb1db LV |
229 | |
230 | rtas_pci_enable(pdn, EEH_THAW_MMIO); | |
231 | loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
232 | ||
233 | rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen); | |
234 | } | |
235 | ||
1da177e4 LT |
236 | /** |
237 | * read_slot_reset_state - Read the reset state of a device node's slot | |
238 | * @dn: device node to read | |
239 | * @rets: array to return results in | |
240 | */ | |
69376502 | 241 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
242 | { |
243 | int token, outputs; | |
fcb7543e | 244 | int config_addr; |
1da177e4 LT |
245 | |
246 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
247 | token = ibm_read_slot_reset_state2; | |
248 | outputs = 4; | |
249 | } else { | |
250 | token = ibm_read_slot_reset_state; | |
69376502 | 251 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
252 | outputs = 3; |
253 | } | |
254 | ||
fcb7543e LV |
255 | /* Use PE configuration address, if present */ |
256 | config_addr = pdn->eeh_config_addr; | |
257 | if (pdn->eeh_pe_config_addr) | |
258 | config_addr = pdn->eeh_pe_config_addr; | |
259 | ||
260 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 261 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
262 | } |
263 | ||
9c547768 LV |
264 | /** |
265 | * eeh_wait_for_slot_status - returns error status of slot | |
266 | * @pdn pci device node | |
267 | * @max_wait_msecs maximum number to millisecs to wait | |
268 | * | |
269 | * Return negative value if a permanent error, else return | |
270 | * Partition Endpoint (PE) status value. | |
271 | * | |
272 | * If @max_wait_msecs is positive, then this routine will | |
273 | * sleep until a valid status can be obtained, or until | |
274 | * the max allowed wait time is exceeded, in which case | |
275 | * a -2 is returned. | |
276 | */ | |
277 | int | |
278 | eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs) | |
279 | { | |
280 | int rc; | |
281 | int rets[3]; | |
282 | int mwait; | |
283 | ||
284 | while (1) { | |
285 | rc = read_slot_reset_state(pdn, rets); | |
286 | if (rc) return rc; | |
287 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
288 | ||
289 | if (rets[0] != 5) return rets[0]; /* return actual status */ | |
290 | ||
291 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
292 | ||
293 | if (max_wait_msecs <= 0) return -1; | |
294 | ||
295 | mwait = rets[2]; | |
296 | if (mwait <= 0) { | |
297 | printk (KERN_WARNING | |
298 | "EEH: Firmware returned bad wait value=%d\n", mwait); | |
299 | mwait = 1000; | |
300 | } else if (mwait > 300*1000) { | |
301 | printk (KERN_WARNING | |
302 | "EEH: Firmware is taking too long, time=%d\n", mwait); | |
303 | mwait = 300*1000; | |
304 | } | |
305 | max_wait_msecs -= mwait; | |
306 | msleep (mwait); | |
307 | } | |
308 | ||
309 | printk(KERN_WARNING "EEH: Timed out waiting for slot status\n"); | |
310 | return -2; | |
311 | } | |
312 | ||
1da177e4 LT |
313 | /** |
314 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 315 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
316 | */ |
317 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
318 | { | |
319 | pte_t *ptep; | |
320 | unsigned long pa; | |
321 | ||
20cee16c | 322 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
323 | if (!ptep) |
324 | return token; | |
325 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
326 | ||
327 | return pa | (token & (PAGE_SIZE-1)); | |
328 | } | |
329 | ||
fd761fd8 LV |
330 | /** |
331 | * Return the "partitionable endpoint" (pe) under which this device lies | |
332 | */ | |
9fb40eb8 | 333 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
334 | { |
335 | while ((dn->parent) && PCI_DN(dn->parent) && | |
336 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
337 | dn = dn->parent; | |
338 | } | |
339 | return dn; | |
340 | } | |
341 | ||
342 | /** Mark all devices that are peers of this device as failed. | |
343 | * Mark the device driver too, so that it can see the failure | |
344 | * immediately; this is critical, since some drivers poll | |
345 | * status registers in interrupts ... If a driver is polling, | |
346 | * and the slot is frozen, then the driver can deadlock in | |
347 | * an interrupt context, which is bad. | |
348 | */ | |
349 | ||
d9564ad1 | 350 | static void __eeh_mark_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
351 | { |
352 | while (dn) { | |
d9564ad1 | 353 | if (PCI_DN(dn)) { |
77bd7415 LV |
354 | /* Mark the pci device driver too */ |
355 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
356 | |
357 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
358 | ||
77bd7415 LV |
359 | if (dev && dev->driver) |
360 | dev->error_state = pci_channel_io_frozen; | |
361 | ||
d9564ad1 LV |
362 | if (dn->child) |
363 | __eeh_mark_slot (dn->child, mode_flag); | |
364 | } | |
fd761fd8 LV |
365 | dn = dn->sibling; |
366 | } | |
367 | } | |
368 | ||
d9564ad1 LV |
369 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
370 | { | |
022d51b1 | 371 | struct pci_dev *dev; |
d9564ad1 | 372 | dn = find_device_pe (dn); |
3914ac7b LV |
373 | |
374 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 375 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
376 | dn = dn->parent; |
377 | ||
d9564ad1 | 378 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
379 | |
380 | /* Mark the pci device too */ | |
381 | dev = PCI_DN(dn)->pcidev; | |
382 | if (dev) | |
383 | dev->error_state = pci_channel_io_frozen; | |
384 | ||
d9564ad1 LV |
385 | __eeh_mark_slot (dn->child, mode_flag); |
386 | } | |
387 | ||
388 | static void __eeh_clear_slot (struct device_node *dn, int mode_flag) | |
fd761fd8 LV |
389 | { |
390 | while (dn) { | |
d9564ad1 LV |
391 | if (PCI_DN(dn)) { |
392 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
393 | PCI_DN(dn)->eeh_check_count = 0; | |
394 | if (dn->child) | |
395 | __eeh_clear_slot (dn->child, mode_flag); | |
396 | } | |
fd761fd8 LV |
397 | dn = dn->sibling; |
398 | } | |
399 | } | |
400 | ||
d9564ad1 | 401 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
402 | { |
403 | unsigned long flags; | |
404 | spin_lock_irqsave(&confirm_error_lock, flags); | |
3914ac7b | 405 | |
d9564ad1 | 406 | dn = find_device_pe (dn); |
3914ac7b LV |
407 | |
408 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 409 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
410 | dn = dn->parent; |
411 | ||
d9564ad1 LV |
412 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
413 | PCI_DN(dn)->eeh_check_count = 0; | |
414 | __eeh_clear_slot (dn->child, mode_flag); | |
fd761fd8 LV |
415 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
416 | } | |
417 | ||
1da177e4 LT |
418 | /** |
419 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
420 | * @dn device node | |
421 | * @dev pci device, if known | |
422 | * | |
423 | * Check for an EEH failure for the given device node. Call this | |
424 | * routine if the result of a read was all 0xff's and you want to | |
425 | * find out if this is due to an EEH slot freeze. This routine | |
426 | * will query firmware for the EEH status. | |
427 | * | |
428 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 429 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
430 | * |
431 | * It is safe to call this routine in an interrupt context. | |
432 | */ | |
433 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
434 | { | |
435 | int ret; | |
436 | int rets[3]; | |
437 | unsigned long flags; | |
1635317f | 438 | struct pci_dn *pdn; |
fd761fd8 | 439 | int rc = 0; |
1da177e4 | 440 | |
257ffc64 | 441 | total_mmio_ffs++; |
1da177e4 LT |
442 | |
443 | if (!eeh_subsystem_enabled) | |
444 | return 0; | |
445 | ||
177bc936 | 446 | if (!dn) { |
257ffc64 | 447 | no_dn++; |
1da177e4 | 448 | return 0; |
177bc936 | 449 | } |
69376502 | 450 | pdn = PCI_DN(dn); |
1da177e4 LT |
451 | |
452 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 453 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 454 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 455 | ignored_check++; |
177bc936 | 456 | #ifdef DEBUG |
f8632c82 LV |
457 | printk ("EEH:ignored check (%x) for %s %s\n", |
458 | pdn->eeh_mode, pci_name (dev), dn->full_name); | |
177bc936 | 459 | #endif |
1da177e4 LT |
460 | return 0; |
461 | } | |
462 | ||
fcb7543e | 463 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 464 | no_cfg_addr++; |
1da177e4 LT |
465 | return 0; |
466 | } | |
467 | ||
fd761fd8 LV |
468 | /* If we already have a pending isolation event for this |
469 | * slot, we know it's bad already, we don't need to check. | |
470 | * Do this checking under a lock; as multiple PCI devices | |
471 | * in one slot might report errors simultaneously, and we | |
472 | * only want one error recovery routine running. | |
1da177e4 | 473 | */ |
fd761fd8 LV |
474 | spin_lock_irqsave(&confirm_error_lock, flags); |
475 | rc = 1; | |
1635317f | 476 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 LV |
477 | pdn->eeh_check_count ++; |
478 | if (pdn->eeh_check_count >= EEH_MAX_FAILS) { | |
479 | printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n", | |
480 | pdn->eeh_check_count); | |
481 | dump_stack(); | |
d0e70341 | 482 | msleep(5000); |
5c1344e9 | 483 | |
1da177e4 | 484 | /* re-read the slot reset state */ |
69376502 | 485 | if (read_slot_reset_state(pdn, rets) != 0) |
1da177e4 | 486 | rets[0] = -1; /* reset state unknown */ |
5c1344e9 LV |
487 | |
488 | /* If we are here, then we hit an infinite loop. Stop. */ | |
489 | panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev)); | |
1da177e4 | 490 | } |
fd761fd8 | 491 | goto dn_unlock; |
1da177e4 LT |
492 | } |
493 | ||
494 | /* | |
495 | * Now test for an EEH failure. This is VERY expensive. | |
496 | * Note that the eeh_config_addr may be a parent device | |
497 | * in the case of a device behind a bridge, or it may be | |
498 | * function zero of a multi-function device. | |
499 | * In any case they must share a common PHB. | |
500 | */ | |
69376502 | 501 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
502 | |
503 | /* If the call to firmware failed, punt */ | |
504 | if (ret != 0) { | |
505 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
506 | ret, dn->full_name); | |
257ffc64 | 507 | false_positives++; |
fd761fd8 LV |
508 | rc = 0; |
509 | goto dn_unlock; | |
76e6faf7 LV |
510 | } |
511 | ||
39d16e29 LV |
512 | /* Note that config-io to empty slots may fail; |
513 | * they are empty when they don't have children. */ | |
514 | if ((rets[0] == 5) && (dn->child == NULL)) { | |
515 | false_positives++; | |
516 | rc = 0; | |
517 | goto dn_unlock; | |
518 | } | |
519 | ||
76e6faf7 LV |
520 | /* If EEH is not supported on this device, punt. */ |
521 | if (rets[1] != 1) { | |
522 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
523 | ret, dn->full_name); | |
257ffc64 | 524 | false_positives++; |
fd761fd8 LV |
525 | rc = 0; |
526 | goto dn_unlock; | |
76e6faf7 LV |
527 | } |
528 | ||
529 | /* If not the kind of error we know about, punt. */ | |
90375f53 | 530 | if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { |
257ffc64 | 531 | false_positives++; |
fd761fd8 LV |
532 | rc = 0; |
533 | goto dn_unlock; | |
76e6faf7 LV |
534 | } |
535 | ||
257ffc64 | 536 | slot_resets++; |
fd761fd8 LV |
537 | |
538 | /* Avoid repeated reports of this failure, including problems | |
539 | * with other functions on this device, and functions under | |
540 | * bridges. */ | |
d9564ad1 | 541 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
fd761fd8 | 542 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 543 | |
d0ab95ca | 544 | eeh_send_failure_event (dn, dev); |
77bd7415 | 545 | |
1da177e4 LT |
546 | /* Most EEH events are due to device driver bugs. Having |
547 | * a stack trace will help the device-driver authors figure | |
548 | * out what happened. So print that out. */ | |
90375f53 | 549 | dump_stack(); |
fd761fd8 LV |
550 | return 1; |
551 | ||
552 | dn_unlock: | |
553 | spin_unlock_irqrestore(&confirm_error_lock, flags); | |
554 | return rc; | |
1da177e4 LT |
555 | } |
556 | ||
fd761fd8 | 557 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
558 | |
559 | /** | |
560 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
561 | * @token i/o token, should be address in the form 0xA.... | |
562 | * @val value, should be all 1's (XXX why do we need this arg??) | |
563 | * | |
1da177e4 LT |
564 | * Check for an EEH failure at the given token address. Call this |
565 | * routine if the result of a read was all 0xff's and you want to | |
566 | * find out if this is due to an EEH slot freeze event. This routine | |
567 | * will query firmware for the EEH status. | |
568 | * | |
569 | * Note this routine is safe to call in an interrupt context. | |
570 | */ | |
571 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
572 | { | |
573 | unsigned long addr; | |
574 | struct pci_dev *dev; | |
575 | struct device_node *dn; | |
576 | ||
577 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
578 | addr = eeh_token_to_phys((unsigned long __force) token); | |
579 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 580 | if (!dev) { |
257ffc64 | 581 | no_device++; |
1da177e4 | 582 | return val; |
177bc936 | 583 | } |
1da177e4 LT |
584 | |
585 | dn = pci_device_to_OF_node(dev); | |
586 | eeh_dn_check_failure (dn, dev); | |
587 | ||
588 | pci_dev_put(dev); | |
589 | return val; | |
590 | } | |
591 | ||
592 | EXPORT_SYMBOL(eeh_check_failure); | |
593 | ||
6dee3fb9 LV |
594 | /* ------------------------------------------------------------- */ |
595 | /* The code below deals with error recovery */ | |
596 | ||
47b5c838 LV |
597 | /** |
598 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
599 | * @pdn pci device node | |
600 | */ | |
601 | ||
602 | int | |
603 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
604 | { | |
605 | int config_addr; | |
606 | int rc; | |
607 | ||
608 | /* Use PE configuration address, if present */ | |
609 | config_addr = pdn->eeh_config_addr; | |
610 | if (pdn->eeh_pe_config_addr) | |
611 | config_addr = pdn->eeh_pe_config_addr; | |
612 | ||
613 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
614 | config_addr, | |
615 | BUID_HI(pdn->phb->buid), | |
616 | BUID_LO(pdn->phb->buid), | |
617 | function); | |
618 | ||
619 | if (rc) | |
fa1be476 | 620 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
47b5c838 LV |
621 | function, rc, pdn->node->full_name); |
622 | ||
fa1be476 LV |
623 | rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC); |
624 | if ((rc == 4) && (function == EEH_THAW_MMIO)) | |
625 | return 0; | |
626 | ||
47b5c838 LV |
627 | return rc; |
628 | } | |
629 | ||
cb5b5624 LV |
630 | /** |
631 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
632 | * @pdn pci device node | |
633 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
634 | * |
635 | * Clear the EEH-frozen condition on a slot. This routine | |
636 | * asserts the PCI #RST line if the 'state' argument is '1', | |
637 | * and drops the #RST line if 'state is '0'. This routine is | |
638 | * safe to call in an interrupt context. | |
639 | * | |
640 | */ | |
641 | ||
642 | static void | |
643 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
644 | { | |
25e591f6 | 645 | int config_addr; |
6dee3fb9 LV |
646 | int rc; |
647 | ||
648 | BUG_ON (pdn==NULL); | |
649 | ||
650 | if (!pdn->phb) { | |
651 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
652 | pdn->node->full_name); | |
653 | return; | |
654 | } | |
655 | ||
25e591f6 LV |
656 | /* Use PE configuration address, if present */ |
657 | config_addr = pdn->eeh_config_addr; | |
658 | if (pdn->eeh_pe_config_addr) | |
659 | config_addr = pdn->eeh_pe_config_addr; | |
660 | ||
6dee3fb9 | 661 | rc = rtas_call(ibm_set_slot_reset,4,1, NULL, |
25e591f6 | 662 | config_addr, |
6dee3fb9 LV |
663 | BUID_HI(pdn->phb->buid), |
664 | BUID_LO(pdn->phb->buid), | |
665 | state); | |
e1029263 LV |
666 | if (rc) |
667 | printk (KERN_WARNING "EEH: Unable to reset the failed slot," | |
668 | " (%d) #RST=%d dn=%s\n", | |
6dee3fb9 | 669 | rc, state, pdn->node->full_name); |
6dee3fb9 LV |
670 | } |
671 | ||
00c2ae35 BK |
672 | /** |
673 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
674 | * @dev: pci device struct | |
675 | * @state: reset state to enter | |
676 | * | |
677 | * Return value: | |
678 | * 0 if success | |
679 | **/ | |
680 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
681 | { | |
682 | struct device_node *dn = pci_device_to_OF_node(dev); | |
683 | struct pci_dn *pdn = PCI_DN(dn); | |
684 | ||
685 | switch (state) { | |
686 | case pcie_deassert_reset: | |
687 | rtas_pci_slot_reset(pdn, 0); | |
688 | break; | |
689 | case pcie_hot_reset: | |
690 | rtas_pci_slot_reset(pdn, 1); | |
691 | break; | |
692 | case pcie_warm_reset: | |
693 | rtas_pci_slot_reset(pdn, 3); | |
694 | break; | |
695 | default: | |
696 | return -EINVAL; | |
697 | }; | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
cb5b5624 LV |
702 | /** |
703 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
704 | * @pdn: pci device node to be reset. | |
b6495c0c LV |
705 | * |
706 | * Return 0 if success, else a non-zero value. | |
6dee3fb9 LV |
707 | */ |
708 | ||
e1029263 | 709 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 710 | { |
6dee3fb9 LV |
711 | rtas_pci_slot_reset (pdn, 1); |
712 | ||
713 | /* The PCI bus requires that the reset be held high for at least | |
714 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
715 | ||
716 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
717 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
718 | |
719 | /* We might get hit with another EEH freeze as soon as the | |
720 | * pci slot reset line is dropped. Make sure we don't miss | |
721 | * these, and clear the flag now. */ | |
722 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
723 | ||
6dee3fb9 LV |
724 | rtas_pci_slot_reset (pdn, 0); |
725 | ||
726 | /* After a PCI slot has been reset, the PCI Express spec requires | |
727 | * a 1.5 second idle time for the bus to stabilize, before starting | |
728 | * up traffic. */ | |
729 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
730 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
731 | } |
732 | ||
733 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
734 | { | |
735 | int i, rc; | |
736 | ||
9c547768 LV |
737 | /* Take three shots at resetting the bus */ |
738 | for (i=0; i<3; i++) { | |
739 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 | 740 | |
9c547768 | 741 | rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC); |
b6495c0c LV |
742 | if (rc == 0) |
743 | return 0; | |
e1029263 | 744 | |
e1029263 LV |
745 | if (rc < 0) { |
746 | printk (KERN_ERR "EEH: unrecoverable slot failure %s\n", | |
747 | pdn->node->full_name); | |
b6495c0c | 748 | return -1; |
e1029263 | 749 | } |
9c547768 LV |
750 | printk (KERN_ERR "EEH: bus reset %d failed on slot %s\n", |
751 | i+1, pdn->node->full_name); | |
6dee3fb9 | 752 | } |
b6495c0c | 753 | |
9c547768 | 754 | return -1; |
6dee3fb9 LV |
755 | } |
756 | ||
8b553f32 LV |
757 | /* ------------------------------------------------------- */ |
758 | /** Save and restore of PCI BARs | |
759 | * | |
760 | * Although firmware will set up BARs during boot, it doesn't | |
761 | * set up device BAR's after a device reset, although it will, | |
762 | * if requested, set up bridge configuration. Thus, we need to | |
763 | * configure the PCI devices ourselves. | |
764 | */ | |
765 | ||
766 | /** | |
767 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
768 | * @pdn: pci device node |
769 | * | |
8b553f32 LV |
770 | * Loads the PCI configuration space base address registers, |
771 | * the expansion ROM base address, the latency timer, and etc. | |
772 | * from the saved values in the device node. | |
773 | */ | |
774 | static inline void __restore_bars (struct pci_dn *pdn) | |
775 | { | |
776 | int i; | |
777 | ||
778 | if (NULL==pdn->phb) return; | |
779 | for (i=4; i<10; i++) { | |
780 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
781 | } | |
782 | ||
783 | /* 12 == Expansion ROM Address */ | |
784 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
785 | ||
786 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
787 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
788 | ||
789 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
790 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
791 | ||
792 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
793 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
794 | ||
795 | /* max latency, min grant, interrupt pin and line */ | |
796 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
797 | } | |
798 | ||
799 | /** | |
800 | * eeh_restore_bars - restore the PCI config space info | |
801 | * | |
802 | * This routine performs a recursive walk to the children | |
803 | * of this device as well. | |
804 | */ | |
805 | void eeh_restore_bars(struct pci_dn *pdn) | |
806 | { | |
807 | struct device_node *dn; | |
808 | if (!pdn) | |
809 | return; | |
810 | ||
7684b40c | 811 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
812 | __restore_bars (pdn); |
813 | ||
814 | dn = pdn->node->child; | |
815 | while (dn) { | |
816 | eeh_restore_bars (PCI_DN(dn)); | |
817 | dn = dn->sibling; | |
818 | } | |
819 | } | |
820 | ||
821 | /** | |
822 | * eeh_save_bars - save device bars | |
823 | * | |
824 | * Save the values of the device bars. Unlike the restore | |
825 | * routine, this routine is *not* recursive. This is because | |
826 | * PCI devices are added individuallly; but, for the restore, | |
827 | * an entire slot is reset at a time. | |
828 | */ | |
7684b40c | 829 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
830 | { |
831 | int i; | |
832 | ||
7684b40c | 833 | if (!pdn ) |
8b553f32 LV |
834 | return; |
835 | ||
836 | for (i = 0; i < 16; i++) | |
7684b40c | 837 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
838 | } |
839 | ||
840 | void | |
841 | rtas_configure_bridge(struct pci_dn *pdn) | |
842 | { | |
fcb7543e | 843 | int config_addr; |
8b553f32 LV |
844 | int rc; |
845 | ||
fcb7543e LV |
846 | /* Use PE configuration address, if present */ |
847 | config_addr = pdn->eeh_config_addr; | |
848 | if (pdn->eeh_pe_config_addr) | |
849 | config_addr = pdn->eeh_pe_config_addr; | |
850 | ||
21e464dd | 851 | rc = rtas_call(ibm_configure_bridge,3,1, NULL, |
fcb7543e | 852 | config_addr, |
8b553f32 LV |
853 | BUID_HI(pdn->phb->buid), |
854 | BUID_LO(pdn->phb->buid)); | |
855 | if (rc) { | |
856 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
857 | rc, pdn->node->full_name); | |
858 | } | |
859 | } | |
860 | ||
172ca926 LV |
861 | /* ------------------------------------------------------------- */ |
862 | /* The code below deals with enabling EEH for devices during the | |
863 | * early boot sequence. EEH must be enabled before any PCI probing | |
864 | * can be done. | |
865 | */ | |
866 | ||
867 | #define EEH_ENABLE 1 | |
868 | ||
1da177e4 LT |
869 | struct eeh_early_enable_info { |
870 | unsigned int buid_hi; | |
871 | unsigned int buid_lo; | |
872 | }; | |
873 | ||
147d6a37 LV |
874 | static int get_pe_addr (int config_addr, |
875 | struct eeh_early_enable_info *info) | |
876 | { | |
877 | unsigned int rets[3]; | |
878 | int ret; | |
879 | ||
880 | /* Use latest config-addr token on power6 */ | |
881 | if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) { | |
882 | /* Make sure we have a PE in hand */ | |
883 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
884 | config_addr, info->buid_hi, info->buid_lo, 1); | |
885 | if (ret || (rets[0]==0)) | |
886 | return 0; | |
887 | ||
888 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
889 | config_addr, info->buid_hi, info->buid_lo, 0); | |
890 | if (ret) | |
891 | return 0; | |
892 | return rets[0]; | |
893 | } | |
894 | ||
895 | /* Use older config-addr token on power5 */ | |
896 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
897 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, | |
898 | config_addr, info->buid_hi, info->buid_lo, 0); | |
899 | if (ret) | |
900 | return 0; | |
901 | return rets[0]; | |
902 | } | |
903 | return 0; | |
904 | } | |
905 | ||
1da177e4 LT |
906 | /* Enable eeh for the given device node. */ |
907 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
908 | { | |
25c4a46f | 909 | unsigned int rets[3]; |
1da177e4 LT |
910 | struct eeh_early_enable_info *info = data; |
911 | int ret; | |
e2eb6392 SR |
912 | const char *status = of_get_property(dn, "status", NULL); |
913 | const u32 *class_code = of_get_property(dn, "class-code", NULL); | |
914 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
915 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 916 | const u32 *regs; |
1da177e4 | 917 | int enable; |
69376502 | 918 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 919 | |
0f17574a | 920 | pdn->class_code = 0; |
1635317f | 921 | pdn->eeh_mode = 0; |
5c1344e9 LV |
922 | pdn->eeh_check_count = 0; |
923 | pdn->eeh_freeze_count = 0; | |
1da177e4 LT |
924 | |
925 | if (status && strcmp(status, "ok") != 0) | |
926 | return NULL; /* ignore devices with bad status */ | |
927 | ||
928 | /* Ignore bad nodes. */ | |
929 | if (!class_code || !vendor_id || !device_id) | |
930 | return NULL; | |
931 | ||
932 | /* There is nothing to check on PCI to ISA bridges */ | |
933 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 934 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
935 | return NULL; |
936 | } | |
0f17574a | 937 | pdn->class_code = *class_code; |
1da177e4 LT |
938 | |
939 | /* | |
940 | * Now decide if we are going to "Disable" EEH checking | |
941 | * for this device. We still run with the EEH hardware active, | |
942 | * but we won't be checking for ff's. This means a driver | |
943 | * could return bad data (very bad!), an interrupt handler could | |
944 | * hang waiting on status bits that won't change, etc. | |
945 | * But there are a few cases like display devices that make sense. | |
946 | */ | |
947 | enable = 1; /* i.e. we will do checking */ | |
77bd7415 | 948 | #if 0 |
1da177e4 LT |
949 | if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) |
950 | enable = 0; | |
77bd7415 | 951 | #endif |
1da177e4 LT |
952 | |
953 | if (!enable) | |
1635317f | 954 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
955 | |
956 | /* Ok... see if this device supports EEH. Some do, some don't, | |
957 | * and the only way to find out is to check each and every one. */ | |
e2eb6392 | 958 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
959 | if (regs) { |
960 | /* First register entry is addr (00BBSS00) */ | |
961 | /* Try to enable eeh */ | |
962 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
963 | regs[0], info->buid_hi, info->buid_lo, |
964 | EEH_ENABLE); | |
965 | ||
25c4a46f | 966 | enable = 0; |
1da177e4 | 967 | if (ret == 0) { |
1635317f | 968 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
969 | |
970 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
971 | * then use that instead. */ | |
147d6a37 | 972 | pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info); |
25c4a46f LV |
973 | |
974 | /* Some older systems (Power4) allow the | |
975 | * ibm,set-eeh-option call to succeed even on nodes | |
976 | * where EEH is not supported. Verify support | |
977 | * explicitly. */ | |
978 | ret = read_slot_reset_state(pdn, rets); | |
979 | if ((ret == 0) && (rets[1] == 1)) | |
980 | enable = 1; | |
981 | } | |
982 | ||
983 | if (enable) { | |
984 | eeh_subsystem_enabled = 1; | |
985 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
986 | ||
1da177e4 | 987 | #ifdef DEBUG |
25e591f6 LV |
988 | printk(KERN_DEBUG "EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
989 | dn->full_name, pdn->eeh_config_addr, pdn->eeh_pe_config_addr); | |
1da177e4 LT |
990 | #endif |
991 | } else { | |
992 | ||
993 | /* This device doesn't support EEH, but it may have an | |
994 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 995 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 996 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 997 | /* Parent supports EEH. */ |
1635317f PM |
998 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
999 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
1000 | return NULL; |
1001 | } | |
1002 | } | |
1003 | } else { | |
1004 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
1005 | dn->full_name); | |
1006 | } | |
1007 | ||
7684b40c | 1008 | eeh_save_bars(pdn); |
69376502 | 1009 | return NULL; |
1da177e4 LT |
1010 | } |
1011 | ||
1012 | /* | |
1013 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
1014 | * As a side effect we can determine here if eeh is supported at all. | |
1015 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
1016 | * check. If a user turns off EEH for a particular adapter they are really | |
1017 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
1018 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
1019 | * EEH for all slots/all devices. | |
1020 | * | |
1021 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
1022 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
1023 | * newer systems can boot. | |
1024 | */ | |
1025 | void __init eeh_init(void) | |
1026 | { | |
1027 | struct device_node *phb, *np; | |
1028 | struct eeh_early_enable_info info; | |
1029 | ||
fd761fd8 | 1030 | spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
1031 | spin_lock_init(&slot_errbuf_lock); |
1032 | ||
1da177e4 LT |
1033 | np = of_find_node_by_path("/rtas"); |
1034 | if (np == NULL) | |
1035 | return; | |
1036 | ||
1037 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
1038 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
1039 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
1040 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
1041 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 1042 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
147d6a37 | 1043 | ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2"); |
21e464dd | 1044 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
1da177e4 LT |
1045 | |
1046 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
1047 | return; | |
1048 | ||
1049 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
1050 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
1051 | eeh_error_buf_size = 1024; | |
1052 | } | |
1053 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
1054 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
1055 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
1056 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
1057 | } | |
1058 | ||
1059 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
1060 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1061 | phb = of_find_node_by_name(phb, "pci")) { | |
1062 | unsigned long buid; | |
1063 | ||
1064 | buid = get_phb_buid(phb); | |
69376502 | 1065 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
1066 | continue; |
1067 | ||
1068 | info.buid_lo = BUID_LO(buid); | |
1069 | info.buid_hi = BUID_HI(buid); | |
1070 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
1071 | } | |
1072 | ||
1073 | if (eeh_subsystem_enabled) | |
1074 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1075 | else | |
1076 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1077 | } | |
1078 | ||
1079 | /** | |
1080 | * eeh_add_device_early - enable EEH for the indicated device_node | |
1081 | * @dn: device node for which to set up EEH | |
1082 | * | |
1083 | * This routine must be used to perform EEH initialization for PCI | |
1084 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1085 | * This routine must be called before any i/o is performed to the | |
1086 | * adapter (inluding any config-space i/o). | |
1087 | * Whether this actually enables EEH or not for this device depends | |
1088 | * on the CEC architecture, type of the device, on earlier boot | |
1089 | * command-line arguments & etc. | |
1090 | */ | |
794e085e | 1091 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1092 | { |
1093 | struct pci_controller *phb; | |
1094 | struct eeh_early_enable_info info; | |
1095 | ||
69376502 | 1096 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 1097 | return; |
1635317f | 1098 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
1099 | |
1100 | /* USB Bus children of PCI devices will not have BUID's */ | |
1101 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1102 | return; |
1da177e4 LT |
1103 | |
1104 | info.buid_hi = BUID_HI(phb->buid); | |
1105 | info.buid_lo = BUID_LO(phb->buid); | |
1106 | early_enable_eeh(dn, &info); | |
1107 | } | |
1da177e4 | 1108 | |
e2a296ee LV |
1109 | void eeh_add_device_tree_early(struct device_node *dn) |
1110 | { | |
1111 | struct device_node *sib; | |
1112 | for (sib = dn->child; sib; sib = sib->sibling) | |
1113 | eeh_add_device_tree_early(sib); | |
1114 | eeh_add_device_early(dn); | |
1115 | } | |
1116 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1117 | ||
1da177e4 LT |
1118 | /** |
1119 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
1120 | * @dev: pci device for which to set up EEH | |
1121 | * | |
1122 | * This routine must be used to complete EEH initialization for PCI | |
1123 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1124 | */ | |
794e085e | 1125 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1126 | { |
56b0fca3 | 1127 | struct device_node *dn; |
8b553f32 | 1128 | struct pci_dn *pdn; |
56b0fca3 | 1129 | |
1da177e4 LT |
1130 | if (!dev || !eeh_subsystem_enabled) |
1131 | return; | |
1132 | ||
1133 | #ifdef DEBUG | |
982245f0 | 1134 | printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev)); |
1da177e4 LT |
1135 | #endif |
1136 | ||
56b0fca3 LV |
1137 | pci_dev_get (dev); |
1138 | dn = pci_device_to_OF_node(dev); | |
8b553f32 LV |
1139 | pdn = PCI_DN(dn); |
1140 | pdn->pcidev = dev; | |
56b0fca3 | 1141 | |
1da177e4 LT |
1142 | pci_addr_cache_insert_device (dev); |
1143 | } | |
794e085e NF |
1144 | |
1145 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
1146 | { | |
1147 | struct pci_dev *dev; | |
1148 | ||
1149 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1150 | eeh_add_device_late(dev); | |
1151 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1152 | struct pci_bus *subbus = dev->subordinate; | |
1153 | if (subbus) | |
1154 | eeh_add_device_tree_late(subbus); | |
1155 | } | |
1156 | } | |
1157 | } | |
1158 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1159 | |
1160 | /** | |
1161 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1162 | * @dev: pci device to be removed | |
1163 | * | |
794e085e NF |
1164 | * This routine should be called when a device is removed from |
1165 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1166 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1167 | * this device will no longer be detected after this call; thus, | |
1168 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1169 | */ |
794e085e | 1170 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1171 | { |
56b0fca3 | 1172 | struct device_node *dn; |
1da177e4 LT |
1173 | if (!dev || !eeh_subsystem_enabled) |
1174 | return; | |
1175 | ||
1176 | /* Unregister the device with the EEH/PCI address search system */ | |
1177 | #ifdef DEBUG | |
982245f0 | 1178 | printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev)); |
1da177e4 LT |
1179 | #endif |
1180 | pci_addr_cache_remove_device(dev); | |
56b0fca3 LV |
1181 | |
1182 | dn = pci_device_to_OF_node(dev); | |
b055a9e1 LV |
1183 | if (PCI_DN(dn)->pcidev) { |
1184 | PCI_DN(dn)->pcidev = NULL; | |
1185 | pci_dev_put (dev); | |
1186 | } | |
1da177e4 | 1187 | } |
1da177e4 | 1188 | |
e2a296ee LV |
1189 | void eeh_remove_bus_device(struct pci_dev *dev) |
1190 | { | |
794e085e NF |
1191 | struct pci_bus *bus = dev->subordinate; |
1192 | struct pci_dev *child, *tmp; | |
1193 | ||
e2a296ee | 1194 | eeh_remove_device(dev); |
794e085e NF |
1195 | |
1196 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1197 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1198 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1199 | } |
1200 | } | |
1201 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1202 | ||
1da177e4 LT |
1203 | static int proc_eeh_show(struct seq_file *m, void *v) |
1204 | { | |
1da177e4 LT |
1205 | if (0 == eeh_subsystem_enabled) { |
1206 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1207 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1208 | } else { |
1209 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1210 | seq_printf(m, |
1211 | "no device=%ld\n" | |
1212 | "no device node=%ld\n" | |
1213 | "no config address=%ld\n" | |
1214 | "check not wanted=%ld\n" | |
1215 | "eeh_total_mmio_ffs=%ld\n" | |
1216 | "eeh_false_positives=%ld\n" | |
1217 | "eeh_ignored_failures=%ld\n" | |
1218 | "eeh_slot_resets=%ld\n", | |
257ffc64 LV |
1219 | no_device, no_dn, no_cfg_addr, |
1220 | ignored_check, total_mmio_ffs, | |
1221 | false_positives, ignored_failures, | |
1222 | slot_resets); | |
1da177e4 LT |
1223 | } |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1229 | { | |
1230 | return single_open(file, proc_eeh_show, NULL); | |
1231 | } | |
1232 | ||
5dfe4c96 | 1233 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1234 | .open = proc_eeh_open, |
1235 | .read = seq_read, | |
1236 | .llseek = seq_lseek, | |
1237 | .release = single_release, | |
1238 | }; | |
1239 | ||
1240 | static int __init eeh_init_proc(void) | |
1241 | { | |
1242 | struct proc_dir_entry *e; | |
1243 | ||
e8222502 | 1244 | if (machine_is(pseries)) { |
1da177e4 LT |
1245 | e = create_proc_entry("ppc64/eeh", 0, NULL); |
1246 | if (e) | |
1247 | e->proc_fops = &proc_eeh_operations; | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | __initcall(eeh_init_proc); |