Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Support for the interrupt controllers found on Power Macintosh, | |
3 | * currently Apple's "Grand Central" interrupt controller in all | |
4 | * it's incarnations. OpenPIC support used on newer machines is | |
5 | * in a separate file | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
8 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
9 | * IBM, Corp. | |
14cf11af PM |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/stddef.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/signal.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
f5a592f7 | 24 | #include <linux/syscore_ops.h> |
14cf11af PM |
25 | #include <linux/adb.h> |
26 | #include <linux/pmu.h> | |
27 | ||
28 | #include <asm/sections.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/prom.h> | |
32 | #include <asm/pci-bridge.h> | |
33 | #include <asm/time.h> | |
14cf11af PM |
34 | #include <asm/pmac_feature.h> |
35 | #include <asm/mpic.h> | |
af3b74df | 36 | #include <asm/xmon.h> |
14cf11af | 37 | |
3c3f42d6 | 38 | #include "pmac.h" |
14cf11af | 39 | |
3c3f42d6 | 40 | #ifdef CONFIG_PPC32 |
14cf11af PM |
41 | struct pmac_irq_hw { |
42 | unsigned int event; | |
43 | unsigned int enable; | |
44 | unsigned int ack; | |
45 | unsigned int level; | |
46 | }; | |
47 | ||
b83da291 GL |
48 | /* Workaround flags for 32bit powermac machines */ |
49 | unsigned int of_irq_workarounds; | |
50 | struct device_node *of_irq_dflt_pic; | |
51 | ||
14cf11af | 52 | /* Default addresses */ |
cc5d0189 | 53 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af PM |
54 | |
55 | #define GC_LEVEL_MASK 0x3ff00000 | |
56 | #define OHARE_LEVEL_MASK 0x1ff00000 | |
57 | #define HEATHROW_LEVEL_MASK 0x1ff00000 | |
58 | ||
59 | static int max_irqs; | |
60 | static int max_real_irqs; | |
61 | static u32 level_mask[4]; | |
62 | ||
d0eab3eb | 63 | static DEFINE_RAW_SPINLOCK(pmac_pic_lock); |
14cf11af | 64 | |
756e7104 SR |
65 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) |
66 | static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | |
b9e5b4e6 BH |
67 | static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; |
68 | static int pmac_irq_cascade = -1; | |
0ebfff14 | 69 | static struct irq_host *pmac_pic_host; |
756e7104 | 70 | |
b9e5b4e6 | 71 | static void __pmac_retrigger(unsigned int irq_nr) |
14cf11af | 72 | { |
b9e5b4e6 BH |
73 | if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { |
74 | __set_bit(irq_nr, ppc_lost_interrupts); | |
75 | irq_nr = pmac_irq_cascade; | |
76 | mb(); | |
77 | } | |
78 | if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
14cf11af | 79 | atomic_inc(&ppc_n_lost_interrupts); |
b9e5b4e6 | 80 | set_dec(1); |
14cf11af PM |
81 | } |
82 | } | |
83 | ||
d8c94aca | 84 | static void pmac_mask_and_ack_irq(struct irq_data *d) |
14cf11af | 85 | { |
476eb491 | 86 | unsigned int src = irqd_to_hwirq(d); |
ca72945d BH |
87 | unsigned long bit = 1UL << (src & 0x1f); |
88 | int i = src >> 5; | |
14cf11af PM |
89 | unsigned long flags; |
90 | ||
d0eab3eb | 91 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
92 | __clear_bit(src, ppc_cached_irq_mask); |
93 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) | |
b9e5b4e6 | 94 | atomic_dec(&ppc_n_lost_interrupts); |
14cf11af PM |
95 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); |
96 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
97 | do { | |
98 | /* make sure ack gets to controller before we enable | |
99 | interrupts */ | |
100 | mb(); | |
101 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
102 | != (ppc_cached_irq_mask[i] & bit)); | |
d0eab3eb | 103 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
104 | } |
105 | ||
d8c94aca | 106 | static void pmac_ack_irq(struct irq_data *d) |
14cf11af | 107 | { |
476eb491 | 108 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
109 | unsigned long bit = 1UL << (src & 0x1f); |
110 | int i = src >> 5; | |
14cf11af PM |
111 | unsigned long flags; |
112 | ||
d0eab3eb | 113 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 114 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) |
b9e5b4e6 BH |
115 | atomic_dec(&ppc_n_lost_interrupts); |
116 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
117 | (void)in_le32(&pmac_irq_hw[i]->ack); | |
d0eab3eb | 118 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
119 | } |
120 | ||
121 | static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
122 | { | |
123 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
124 | int i = irq_nr >> 5; | |
125 | ||
126 | if ((unsigned)irq_nr >= max_irqs) | |
127 | return; | |
128 | ||
14cf11af PM |
129 | /* enable unmasked interrupts */ |
130 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
131 | ||
132 | do { | |
133 | /* make sure mask gets to controller before we | |
134 | return to user */ | |
135 | mb(); | |
136 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
137 | != (ppc_cached_irq_mask[i] & bit)); | |
138 | ||
139 | /* | |
140 | * Unfortunately, setting the bit in the enable register | |
141 | * when the device interrupt is already on *doesn't* set | |
142 | * the bit in the flag register or request another interrupt. | |
143 | */ | |
144 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
b9e5b4e6 | 145 | __pmac_retrigger(irq_nr); |
14cf11af PM |
146 | } |
147 | ||
148 | /* When an irq gets requested for the first client, if it's an | |
149 | * edge interrupt, we clear any previous one on the controller | |
150 | */ | |
d8c94aca | 151 | static unsigned int pmac_startup_irq(struct irq_data *d) |
14cf11af | 152 | { |
b9e5b4e6 | 153 | unsigned long flags; |
476eb491 | 154 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
155 | unsigned long bit = 1UL << (src & 0x1f); |
156 | int i = src >> 5; | |
14cf11af | 157 | |
d0eab3eb | 158 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
8c99f561 | 159 | if (!irqd_is_level_type(d)) |
14cf11af | 160 | out_le32(&pmac_irq_hw[i]->ack, bit); |
0ebfff14 BH |
161 | __set_bit(src, ppc_cached_irq_mask); |
162 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 163 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
164 | |
165 | return 0; | |
166 | } | |
167 | ||
d8c94aca | 168 | static void pmac_mask_irq(struct irq_data *d) |
14cf11af | 169 | { |
b9e5b4e6 | 170 | unsigned long flags; |
476eb491 | 171 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 172 | |
d0eab3eb | 173 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 174 | __clear_bit(src, ppc_cached_irq_mask); |
ca72945d | 175 | __pmac_set_irq_mask(src, 1); |
d0eab3eb | 176 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
177 | } |
178 | ||
d8c94aca | 179 | static void pmac_unmask_irq(struct irq_data *d) |
14cf11af | 180 | { |
b9e5b4e6 | 181 | unsigned long flags; |
476eb491 | 182 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 183 | |
d0eab3eb | 184 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
185 | __set_bit(src, ppc_cached_irq_mask); |
186 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 187 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
188 | } |
189 | ||
d8c94aca | 190 | static int pmac_retrigger(struct irq_data *d) |
14cf11af | 191 | { |
b9e5b4e6 | 192 | unsigned long flags; |
14cf11af | 193 | |
d0eab3eb | 194 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
476eb491 | 195 | __pmac_retrigger(irqd_to_hwirq(d)); |
d0eab3eb | 196 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
197 | return 1; |
198 | } | |
14cf11af | 199 | |
b9e5b4e6 | 200 | static struct irq_chip pmac_pic = { |
fc380c0c | 201 | .name = "PMAC-PIC", |
d8c94aca LB |
202 | .irq_startup = pmac_startup_irq, |
203 | .irq_mask = pmac_mask_irq, | |
204 | .irq_ack = pmac_ack_irq, | |
205 | .irq_mask_ack = pmac_mask_and_ack_irq, | |
206 | .irq_unmask = pmac_unmask_irq, | |
207 | .irq_retrigger = pmac_retrigger, | |
14cf11af PM |
208 | }; |
209 | ||
35a84c2f | 210 | static irqreturn_t gatwick_action(int cpl, void *dev_id) |
14cf11af | 211 | { |
b9e5b4e6 | 212 | unsigned long flags; |
14cf11af | 213 | int irq, bits; |
b9e5b4e6 | 214 | int rc = IRQ_NONE; |
14cf11af | 215 | |
d0eab3eb | 216 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
217 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { |
218 | int i = irq >> 5; | |
219 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
220 | /* We must read level interrupts from the level register */ | |
221 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
222 | bits &= ppc_cached_irq_mask[i]; | |
223 | if (bits == 0) | |
224 | continue; | |
225 | irq += __ilog2(bits); | |
d0eab3eb | 226 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
f11f76d4 | 227 | generic_handle_irq(irq); |
d0eab3eb | 228 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
b9e5b4e6 | 229 | rc = IRQ_HANDLED; |
14cf11af | 230 | } |
d0eab3eb | 231 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 | 232 | return rc; |
14cf11af PM |
233 | } |
234 | ||
35a84c2f | 235 | static unsigned int pmac_pic_get_irq(void) |
14cf11af PM |
236 | { |
237 | int irq; | |
238 | unsigned long bits = 0; | |
b9e5b4e6 | 239 | unsigned long flags; |
14cf11af | 240 | |
1ece355b | 241 | #ifdef CONFIG_PPC_PMAC32_PSURGE |
23f73a5f MM |
242 | /* IPI's are a hack on the powersurge -- Cort */ |
243 | if (smp_processor_id() != 0) { | |
244 | return psurge_secondary_virq; | |
14cf11af | 245 | } |
1ece355b | 246 | #endif /* CONFIG_PPC_PMAC32_PSURGE */ |
d0eab3eb | 247 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
248 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { |
249 | int i = irq >> 5; | |
250 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
251 | /* We must read level interrupts from the level register */ | |
252 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
253 | bits &= ppc_cached_irq_mask[i]; | |
254 | if (bits == 0) | |
255 | continue; | |
256 | irq += __ilog2(bits); | |
257 | break; | |
258 | } | |
d0eab3eb | 259 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
0ebfff14 BH |
260 | if (unlikely(irq < 0)) |
261 | return NO_IRQ; | |
262 | return irq_linear_revmap(pmac_pic_host, irq); | |
14cf11af PM |
263 | } |
264 | ||
14cf11af PM |
265 | #ifdef CONFIG_XMON |
266 | static struct irqaction xmon_action = { | |
267 | .handler = xmon_irq, | |
268 | .flags = 0, | |
14cf11af PM |
269 | .name = "NMI - XMON" |
270 | }; | |
271 | #endif | |
272 | ||
273 | static struct irqaction gatwick_cascade_action = { | |
274 | .handler = gatwick_action, | |
14cf11af PM |
275 | .name = "cascade", |
276 | }; | |
3c3f42d6 | 277 | |
0ebfff14 BH |
278 | static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) |
279 | { | |
280 | /* We match all, we don't always have a node anyway */ | |
281 | return 1; | |
282 | } | |
283 | ||
284 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 285 | irq_hw_number_t hw) |
0ebfff14 | 286 | { |
0ebfff14 BH |
287 | int level; |
288 | ||
289 | if (hw >= max_irqs) | |
290 | return -EINVAL; | |
291 | ||
292 | /* Mark level interrupts, set delayed disable for edge ones and set | |
293 | * handlers | |
294 | */ | |
295 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); | |
296 | if (level) | |
98488db9 | 297 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e TG |
298 | irq_set_chip_and_handler(virq, &pmac_pic, |
299 | level ? handle_level_irq : handle_edge_irq); | |
0ebfff14 BH |
300 | return 0; |
301 | } | |
302 | ||
303 | static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 304 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
305 | irq_hw_number_t *out_hwirq, |
306 | unsigned int *out_flags) | |
307 | ||
308 | { | |
6e99e458 | 309 | *out_flags = IRQ_TYPE_NONE; |
0ebfff14 BH |
310 | *out_hwirq = *intspec; |
311 | return 0; | |
312 | } | |
313 | ||
314 | static struct irq_host_ops pmac_pic_host_ops = { | |
315 | .match = pmac_pic_host_match, | |
316 | .map = pmac_pic_host_map, | |
317 | .xlate = pmac_pic_host_xlate, | |
318 | }; | |
319 | ||
cc5d0189 | 320 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 321 | { |
3c3f42d6 | 322 | int i; |
cc5d0189 BH |
323 | struct device_node *master = NULL; |
324 | struct device_node *slave = NULL; | |
325 | u8 __iomem *addr; | |
326 | struct resource r; | |
14cf11af | 327 | |
cc5d0189 | 328 | /* Set our get_irq function */ |
0ebfff14 | 329 | ppc_md.get_irq = pmac_pic_get_irq; |
14cf11af | 330 | |
cc5d0189 BH |
331 | /* |
332 | * Find the interrupt controller type & node | |
14cf11af | 333 | */ |
cc5d0189 BH |
334 | |
335 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
336 | max_irqs = max_real_irqs = 32; | |
14cf11af | 337 | level_mask[0] = GC_LEVEL_MASK; |
cc5d0189 BH |
338 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
339 | max_irqs = max_real_irqs = 32; | |
14cf11af | 340 | level_mask[0] = OHARE_LEVEL_MASK; |
cc5d0189 | 341 | |
14cf11af | 342 | /* We might have a second cascaded ohare */ |
cc5d0189 BH |
343 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
344 | if (slave) { | |
345 | max_irqs = 64; | |
346 | level_mask[1] = OHARE_LEVEL_MASK; | |
cc5d0189 BH |
347 | } |
348 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { | |
349 | max_irqs = max_real_irqs = 64; | |
14cf11af PM |
350 | level_mask[0] = HEATHROW_LEVEL_MASK; |
351 | level_mask[1] = 0; | |
cc5d0189 | 352 | |
14cf11af | 353 | /* We might have a second cascaded heathrow */ |
cc5d0189 BH |
354 | slave = of_find_node_by_name(master, "mac-io"); |
355 | ||
356 | /* Check ordering of master & slave */ | |
55b61fec | 357 | if (of_device_is_compatible(master, "gatwick")) { |
cc5d0189 BH |
358 | struct device_node *tmp; |
359 | BUG_ON(slave == NULL); | |
360 | tmp = master; | |
361 | master = slave; | |
362 | slave = tmp; | |
363 | } | |
14cf11af | 364 | |
cc5d0189 BH |
365 | /* We found a slave */ |
366 | if (slave) { | |
14cf11af | 367 | max_irqs = 128; |
cc5d0189 BH |
368 | level_mask[2] = HEATHROW_LEVEL_MASK; |
369 | level_mask[3] = 0; | |
cc5d0189 | 370 | } |
14cf11af | 371 | } |
cc5d0189 BH |
372 | BUG_ON(master == NULL); |
373 | ||
0ebfff14 BH |
374 | /* |
375 | * Allocate an irq host | |
376 | */ | |
52964f87 | 377 | pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs, |
0ebfff14 BH |
378 | &pmac_pic_host_ops, |
379 | max_irqs); | |
380 | BUG_ON(pmac_pic_host == NULL); | |
381 | irq_set_default_host(pmac_pic_host); | |
14cf11af | 382 | |
cc5d0189 BH |
383 | /* Get addresses of first controller if we have a node for it */ |
384 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
385 | ||
386 | /* Map interrupts of primary controller */ | |
387 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
388 | i = 0; | |
389 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
390 | (addr + 0x20); | |
391 | if (max_real_irqs > 32) | |
392 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
393 | (addr + 0x10); | |
394 | of_node_put(master); | |
395 | ||
396 | printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", | |
397 | master->full_name, max_real_irqs); | |
398 | ||
399 | /* Map interrupts of cascaded controller */ | |
400 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
401 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
402 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
403 | (addr + 0x20); | |
404 | if (max_irqs > 64) | |
405 | pmac_irq_hw[i++] = | |
406 | (volatile struct pmac_irq_hw __iomem *) | |
407 | (addr + 0x10); | |
0ebfff14 | 408 | pmac_irq_cascade = irq_of_parse_and_map(slave, 0); |
cc5d0189 BH |
409 | |
410 | printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" | |
411 | " cascade: %d\n", slave->full_name, | |
b9e5b4e6 | 412 | max_irqs - max_real_irqs, pmac_irq_cascade); |
14cf11af | 413 | } |
cc5d0189 | 414 | of_node_put(slave); |
14cf11af | 415 | |
b9e5b4e6 | 416 | /* Disable all interrupts in all controllers */ |
14cf11af PM |
417 | for (i = 0; i * 32 < max_irqs; ++i) |
418 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 419 | |
b9e5b4e6 | 420 | /* Hookup cascade irq */ |
0ebfff14 | 421 | if (slave && pmac_irq_cascade != NO_IRQ) |
b9e5b4e6 | 422 | setup_irq(pmac_irq_cascade, &gatwick_cascade_action); |
14cf11af | 423 | |
cc5d0189 | 424 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af | 425 | #ifdef CONFIG_XMON |
6e99e458 | 426 | setup_irq(irq_create_mapping(NULL, 20), &xmon_action); |
cc5d0189 BH |
427 | #endif |
428 | } | |
b83da291 GL |
429 | |
430 | int of_irq_map_oldworld(struct device_node *device, int index, | |
431 | struct of_irq *out_irq) | |
432 | { | |
433 | const u32 *ints = NULL; | |
434 | int intlen; | |
435 | ||
436 | /* | |
437 | * Old machines just have a list of interrupt numbers | |
438 | * and no interrupt-controller nodes. We also have dodgy | |
439 | * cases where the APPL,interrupts property is completely | |
440 | * missing behind pci-pci bridges and we have to get it | |
441 | * from the parent (the bridge itself, as apple just wired | |
442 | * everything together on these) | |
443 | */ | |
444 | while (device) { | |
445 | ints = of_get_property(device, "AAPL,interrupts", &intlen); | |
446 | if (ints != NULL) | |
447 | break; | |
448 | device = device->parent; | |
449 | if (device && strcmp(device->type, "pci") != 0) | |
450 | break; | |
451 | } | |
452 | if (ints == NULL) | |
453 | return -EINVAL; | |
454 | intlen /= sizeof(u32); | |
455 | ||
456 | if (index >= intlen) | |
457 | return -EINVAL; | |
458 | ||
459 | out_irq->controller = NULL; | |
460 | out_irq->specifier[0] = ints[index]; | |
461 | out_irq->size = 1; | |
462 | ||
463 | return 0; | |
464 | } | |
cc5d0189 BH |
465 | #endif /* CONFIG_PPC32 */ |
466 | ||
7d12e780 | 467 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) |
cc5d0189 | 468 | { |
ec775d0e TG |
469 | struct irq_chip *chip = irq_desc_get_chip(desc); |
470 | struct mpic *mpic = irq_desc_get_handler_data(desc); | |
35a84c2f | 471 | unsigned int cascade_irq = mpic_get_one_irq(mpic); |
d8c94aca | 472 | |
0ebfff14 | 473 | if (cascade_irq != NO_IRQ) |
7d12e780 | 474 | generic_handle_irq(cascade_irq); |
d8c94aca LB |
475 | |
476 | chip->irq_eoi(&desc->irq_data); | |
cc5d0189 BH |
477 | } |
478 | ||
479 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) | |
480 | { | |
481 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
482 | struct device_node* pswitch; | |
483 | int nmi_irq; | |
484 | ||
485 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
0ebfff14 BH |
486 | if (pswitch) { |
487 | nmi_irq = irq_of_parse_and_map(pswitch, 0); | |
488 | if (nmi_irq != NO_IRQ) { | |
489 | mpic_irq_set_priority(nmi_irq, 9); | |
490 | setup_irq(nmi_irq, &xmon_action); | |
491 | } | |
492 | of_node_put(pswitch); | |
cc5d0189 | 493 | } |
cc5d0189 BH |
494 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ |
495 | } | |
496 | ||
1beb6a7d BH |
497 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
498 | int master) | |
499 | { | |
1beb6a7d BH |
500 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; |
501 | struct resource r; | |
502 | struct mpic *mpic; | |
503 | unsigned int flags = master ? MPIC_PRIMARY : 0; | |
504 | int rc; | |
505 | ||
506 | rc = of_address_to_resource(np, 0, &r); | |
507 | if (rc) | |
508 | return NULL; | |
509 | ||
510 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
511 | ||
1beb6a7d | 512 | flags |= MPIC_WANTS_RESET; |
e2eb6392 | 513 | if (of_get_property(np, "big-endian", NULL)) |
1beb6a7d BH |
514 | flags |= MPIC_BIG_ENDIAN; |
515 | ||
516 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
517 | * but works until I find a better way | |
518 | */ | |
519 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
6cfef5b2 | 520 | flags |= MPIC_U3_HT_IRQS; |
1beb6a7d | 521 | |
0ebfff14 | 522 | mpic = mpic_alloc(np, r.start, flags, 0, 0, name); |
1beb6a7d BH |
523 | if (mpic == NULL) |
524 | return NULL; | |
525 | ||
526 | mpic_init(mpic); | |
527 | ||
528 | return mpic; | |
529 | } | |
530 | ||
cc5d0189 BH |
531 | static int __init pmac_pic_probe_mpic(void) |
532 | { | |
533 | struct mpic *mpic1, *mpic2; | |
534 | struct device_node *np, *master = NULL, *slave = NULL; | |
0ebfff14 | 535 | unsigned int cascade; |
cc5d0189 BH |
536 | |
537 | /* We can have up to 2 MPICs cascaded */ | |
538 | for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) | |
539 | != NULL;) { | |
540 | if (master == NULL && | |
e2eb6392 | 541 | of_get_property(np, "interrupts", NULL) == NULL) |
cc5d0189 BH |
542 | master = of_node_get(np); |
543 | else if (slave == NULL) | |
544 | slave = of_node_get(np); | |
545 | if (master && slave) | |
546 | break; | |
547 | } | |
548 | ||
549 | /* Check for bogus setups */ | |
550 | if (master == NULL && slave != NULL) { | |
551 | master = slave; | |
552 | slave = NULL; | |
553 | } | |
554 | ||
555 | /* Not found, default to good old pmac pic */ | |
556 | if (master == NULL) | |
557 | return -ENODEV; | |
558 | ||
559 | /* Set master handler */ | |
560 | ppc_md.get_irq = mpic_get_irq; | |
561 | ||
562 | /* Setup master */ | |
1beb6a7d | 563 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 564 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
565 | |
566 | /* Install NMI if any */ | |
567 | pmac_pic_setup_mpic_nmi(mpic1); | |
568 | ||
569 | of_node_put(master); | |
570 | ||
571 | /* No slave, let's go out */ | |
0ebfff14 BH |
572 | if (slave == NULL) |
573 | return 0; | |
574 | ||
575 | /* Get/Map slave interrupt */ | |
576 | cascade = irq_of_parse_and_map(slave, 0); | |
577 | if (cascade == NO_IRQ) { | |
578 | printk(KERN_ERR "Failed to map cascade IRQ\n"); | |
cc5d0189 | 579 | return 0; |
0ebfff14 | 580 | } |
cc5d0189 | 581 | |
1beb6a7d | 582 | mpic2 = pmac_setup_one_mpic(slave, 0); |
cc5d0189 | 583 | if (mpic2 == NULL) { |
1beb6a7d BH |
584 | printk(KERN_ERR "Failed to setup slave MPIC\n"); |
585 | of_node_put(slave); | |
cc5d0189 BH |
586 | return 0; |
587 | } | |
ec775d0e TG |
588 | irq_set_handler_data(cascade, mpic2); |
589 | irq_set_chained_handler(cascade, pmac_u3_cascade); | |
cc5d0189 BH |
590 | |
591 | of_node_put(slave); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | ||
596 | void __init pmac_pic_init(void) | |
597 | { | |
0ebfff14 BH |
598 | /* We configure the OF parsing based on our oldworld vs. newworld |
599 | * platform type and wether we were booted by BootX. | |
600 | */ | |
601 | #ifdef CONFIG_PPC32 | |
602 | if (!pmac_newworld) | |
b83da291 | 603 | of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC; |
e2eb6392 | 604 | if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL) |
b83da291 | 605 | of_irq_workarounds |= OF_IMAP_NO_PHANDLE; |
0ebfff14 | 606 | |
b83da291 GL |
607 | /* If we don't have phandles on a newworld, then try to locate a |
608 | * default interrupt controller (happens when booting with BootX). | |
609 | * We do a first match here, hopefully, that only ever happens on | |
610 | * machines with one controller. | |
611 | */ | |
612 | if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) { | |
613 | struct device_node *np; | |
614 | ||
615 | for_each_node_with_property(np, "interrupt-controller") { | |
616 | /* Skip /chosen/interrupt-controller */ | |
617 | if (strcmp(np->name, "chosen") == 0) | |
618 | continue; | |
619 | /* It seems like at least one person wants | |
620 | * to use BootX on a machine with an AppleKiwi | |
621 | * controller which happens to pretend to be an | |
622 | * interrupt controller too. */ | |
623 | if (strcmp(np->name, "AppleKiwi") == 0) | |
624 | continue; | |
625 | /* I think we found one ! */ | |
626 | of_irq_dflt_pic = np; | |
627 | break; | |
628 | } | |
629 | } | |
630 | #endif /* CONFIG_PPC32 */ | |
6e99e458 | 631 | |
cc5d0189 BH |
632 | /* We first try to detect Apple's new Core99 chipset, since mac-io |
633 | * is quite different on those machines and contains an IBM MPIC2. | |
634 | */ | |
635 | if (pmac_pic_probe_mpic() == 0) | |
636 | return; | |
637 | ||
638 | #ifdef CONFIG_PPC32 | |
639 | pmac_pic_probe_oldstyle(); | |
640 | #endif | |
14cf11af PM |
641 | } |
642 | ||
a0005034 | 643 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
644 | /* |
645 | * These procedures are used in implementing sleep on the powerbooks. | |
646 | * sleep_save_intrs() saves the states of all interrupt enables | |
647 | * and disables all interrupts except for the nominated one. | |
648 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
649 | */ | |
650 | unsigned long sleep_save_mask[2]; | |
651 | ||
652 | /* This used to be passed by the PMU driver but that link got | |
653 | * broken with the new driver model. We use this tweak for now... | |
0ebfff14 | 654 | * We really want to do things differently though... |
14cf11af PM |
655 | */ |
656 | static int pmacpic_find_viaint(void) | |
657 | { | |
658 | int viaint = -1; | |
659 | ||
660 | #ifdef CONFIG_ADB_PMU | |
661 | struct device_node *np; | |
662 | ||
663 | if (pmu_get_model() != PMU_OHARE_BASED) | |
664 | goto not_found; | |
665 | np = of_find_node_by_name(NULL, "via-pmu"); | |
666 | if (np == NULL) | |
667 | goto not_found; | |
d258e64e | 668 | viaint = irq_of_parse_and_map(np, 0); |
14cf11af PM |
669 | |
670 | not_found: | |
98cddbfb | 671 | #endif /* CONFIG_ADB_PMU */ |
14cf11af PM |
672 | return viaint; |
673 | } | |
674 | ||
f5a592f7 | 675 | static int pmacpic_suspend(void) |
14cf11af PM |
676 | { |
677 | int viaint = pmacpic_find_viaint(); | |
678 | ||
679 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
680 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
681 | ppc_cached_irq_mask[0] = 0; | |
682 | ppc_cached_irq_mask[1] = 0; | |
683 | if (viaint > 0) | |
684 | set_bit(viaint, ppc_cached_irq_mask); | |
685 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
686 | if (max_real_irqs > 32) | |
687 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
688 | (void)in_le32(&pmac_irq_hw[0]->event); | |
689 | /* make sure mask gets to controller before we return to caller */ | |
690 | mb(); | |
691 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
f5a592f7 | 696 | static void pmacpic_resume(void) |
14cf11af PM |
697 | { |
698 | int i; | |
699 | ||
700 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
701 | if (max_real_irqs > 32) | |
702 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
703 | mb(); | |
704 | for (i = 0; i < max_real_irqs; ++i) | |
705 | if (test_bit(i, sleep_save_mask)) | |
d8c94aca | 706 | pmac_unmask_irq(irq_get_irq_data(i)); |
14cf11af PM |
707 | } |
708 | ||
f5a592f7 RW |
709 | static struct syscore_ops pmacpic_syscore_ops = { |
710 | .suspend = pmacpic_suspend, | |
711 | .resume = pmacpic_resume, | |
14cf11af PM |
712 | }; |
713 | ||
f5a592f7 | 714 | static int __init init_pmacpic_syscore(void) |
14cf11af | 715 | { |
339dedf7 BH |
716 | if (pmac_irq_hw[0]) |
717 | register_syscore_ops(&pmacpic_syscore_ops); | |
14cf11af PM |
718 | return 0; |
719 | } | |
14cf11af | 720 | |
f5a592f7 RW |
721 | machine_subsys_initcall(powermac, init_pmacpic_syscore); |
722 | ||
723 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |