[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / platforms / pasemi / setup.c

/*
 * Copyright (C) 2006-2007 PA Semi, Inc
 *
 * Authors: Kip Walker, PA Semi
 *	    Olof Johansson, PA Semi
 *
 * Maintained by: Olof Johansson <olof@lixom.net>
 *
 * Based on arch/powerpc/platforms/maple/setup.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/of_platform.h>
#include <linux/gfp.h>

#include <asm/prom.h>
#include <asm/iommu.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mmu.h>
#include <asm/debug.h>

#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ds.h>

#include "pasemi.h"

/* SDC reset register, must be pre-mapped at reset time */
static void __iomem *reset_reg;

/* Various error status registers, must be pre-mapped at MCE time */

#define MAX_MCE_REGS	32
struct mce_regs {
	char *name;
	void __iomem *addr;
};

static struct mce_regs mce_regs[MAX_MCE_REGS];
static int num_mce_regs;
static int nmi_virq = NO_IRQ;


static void pas_restart(char *cmd)
{
	/* Need to put others cpu in hold loop so they're not sleeping */
	smp_send_stop();
	udelay(10000);
	printk("Restarting...\n");
	while (1)
		out_le32(reset_reg, 0x6000000);
}

#ifdef CONFIG_SMP
static arch_spinlock_t timebase_lock;
static unsigned long timebase;

static void pas_give_timebase(void)
{
	unsigned long flags;

	local_irq_save(flags);
	hard_irq_disable();
	arch_spin_lock(&timebase_lock);
	mtspr(SPRN_TBCTL, TBCTL_FREEZE);
	isync();
	timebase = get_tb();
	arch_spin_unlock(&timebase_lock);

	while (timebase)
		barrier();
	mtspr(SPRN_TBCTL, TBCTL_RESTART);
	local_irq_restore(flags);
}

static void pas_take_timebase(void)
{
	while (!timebase)
		smp_rmb();

	arch_spin_lock(&timebase_lock);
	set_tb(timebase >> 32, timebase & 0xffffffff);
	timebase = 0;
	arch_spin_unlock(&timebase_lock);
}

struct smp_ops_t pas_smp_ops = {
	.probe		= smp_mpic_probe,
	.message_pass	= smp_mpic_message_pass,
	.kick_cpu	= smp_generic_kick_cpu,
	.setup_cpu	= smp_mpic_setup_cpu,
	.give_timebase	= pas_give_timebase,
	.take_timebase	= pas_take_timebase,
};
#endif /* CONFIG_SMP */

void __init pas_setup_arch(void)
{
#ifdef CONFIG_SMP
	/* Setup SMP callback */
	smp_ops = &pas_smp_ops;
#endif
	/* Lookup PCI hosts */
	pas_pci_init();

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	/* Remap SDC register for doing reset */
	/* XXXOJN This should maybe come out of the device tree */
	reset_reg = ioremap(0xfc101100, 4);
}

static int __init pas_setup_mce_regs(void)
{
	struct pci_dev *dev;
	int reg;

	/* Remap various SoC status registers for use by the MCE handler */

	reg = 0;

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
	while (dev && reg < MAX_MCE_REGS) {
		mce_regs[reg].name = kasprintf(GFP_KERNEL,
						"mc%d_mcdebug_errsta", reg);
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
		dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
		reg++;
	}

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
	if (dev && reg+4 < MAX_MCE_REGS) {
		mce_regs[reg].name = "iobdbg_IntStatus1";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
		reg++;
		mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
		reg++;
		mce_regs[reg].name = "iobiom_IntStatus";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
		reg++;
		mce_regs[reg].name = "iobiom_IntDbgReg";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
		reg++;
	}

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
	if (dev && reg+2 < MAX_MCE_REGS) {
		mce_regs[reg].name = "l2csts_IntStatus";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
		reg++;
		mce_regs[reg].name = "l2csts_Cnt";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
		reg++;
	}

	num_mce_regs = reg;

	return 0;
}
machine_device_initcall(pasemi, pas_setup_mce_regs);

static __init void pas_init_IRQ(void)
{
	struct device_node *np;
	struct device_node *root, *mpic_node;
	unsigned long openpic_addr;
	const unsigned int *opprop;
	int naddr, opplen;
	int mpic_flags;
	const unsigned int *nmiprop;
	struct mpic *mpic;

	mpic_node = NULL;

	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "open-pic")) {
			mpic_node = np;
			break;
		}
	if (!mpic_node)
		for_each_node_by_type(np, "open-pic") {
			mpic_node = np;
			break;
		}
	if (!mpic_node) {
		printk(KERN_ERR
			"Failed to locate the MPIC interrupt controller\n");
		return;
	}

	/* Find address list in /platform-open-pic */
	root = of_find_node_by_path("/");
	naddr = of_n_addr_cells(root);
	opprop = of_get_property(root, "platform-open-pic", &opplen);
	if (!opprop) {
		printk(KERN_ERR "No platform-open-pic property.\n");
		of_node_put(root);
		return;
	}
	openpic_addr = of_read_number(opprop, naddr);
	printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);

	mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;

	nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
	if (nmiprop)
		mpic_flags |= MPIC_ENABLE_MCK;

	mpic = mpic_alloc(mpic_node, openpic_addr,
			  mpic_flags, 0, 0, "PASEMI-OPIC");
	BUG_ON(!mpic);

	mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
	mpic_init(mpic);
	/* The NMI/MCK source needs to be prio 15 */
	if (nmiprop) {
		nmi_virq = irq_create_mapping(NULL, *nmiprop);
		mpic_irq_set_priority(nmi_virq, 15);
		irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
		mpic_unmask_irq(irq_get_irq_data(nmi_virq));
	}

	of_node_put(mpic_node);
	of_node_put(root);
}

static void __init pas_progress(char *s, unsigned short hex)
{
	printk("[%04x] : %s\n", hex, s ? s : "");
}


static int pas_machine_check_handler(struct pt_regs *regs)
{
	int cpu = smp_processor_id();
	unsigned long srr0, srr1, dsisr;
	int dump_slb = 0;
	int i;

	srr0 = regs->nip;
	srr1 = regs->msr;

	if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
		printk(KERN_ERR "NMI delivered\n");
		debugger(regs);
		mpic_end_irq(irq_get_irq_data(nmi_virq));
		goto out;
	}

	dsisr = mfspr(SPRN_DSISR);
	printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
	printk(KERN_ERR "SRR0  0x%016lx SRR1 0x%016lx\n", srr0, srr1);
	printk(KERN_ERR "DSISR 0x%016lx DAR  0x%016lx\n", dsisr, regs->dar);
	printk(KERN_ERR "BER   0x%016lx MER  0x%016lx\n", mfspr(SPRN_PA6T_BER),
		mfspr(SPRN_PA6T_MER));
	printk(KERN_ERR "IER   0x%016lx DER  0x%016lx\n", mfspr(SPRN_PA6T_IER),
		mfspr(SPRN_PA6T_DER));
	printk(KERN_ERR "Cause:\n");

	if (srr1 & 0x200000)
		printk(KERN_ERR "Signalled by SDC\n");

	if (srr1 & 0x100000) {
		printk(KERN_ERR "Load/Store detected error:\n");
		if (dsisr & 0x8000)
			printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
		if (dsisr & 0x4000)
			printk(KERN_ERR "LSU snoop response error\n");
		if (dsisr & 0x2000) {
			printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
			dump_slb = 1;
		}
		if (dsisr & 0x1000)
			printk(KERN_ERR "Recoverable Duptags\n");
		if (dsisr & 0x800)
			printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
		if (dsisr & 0x400)
			printk(KERN_ERR "TLB parity error count overflow\n");
	}

	if (srr1 & 0x80000)
		printk(KERN_ERR "Bus Error\n");

	if (srr1 & 0x40000) {
		printk(KERN_ERR "I-side SLB multiple hit\n");
		dump_slb = 1;
	}

	if (srr1 & 0x20000)
		printk(KERN_ERR "I-cache parity error hit\n");

	if (num_mce_regs == 0)
		printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
	else
		printk(KERN_ERR "SoC debug registers:\n");

	for (i = 0; i < num_mce_regs; i++)
		printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
			in_le32(mce_regs[i].addr));

	if (dump_slb) {
		unsigned long e, v;
		int i;

		printk(KERN_ERR "slb contents:\n");
		for (i = 0; i < mmu_slb_size; i++) {
			asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
			asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
			printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
		}
	}

out:
	/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
	return !!(srr1 & 0x2);
}

static void __init pas_init_early(void)
{
	iommu_init_early_pasemi();
}

#ifdef CONFIG_PCMCIA
static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
			 void *data)
{
	struct device *dev = data;
	struct device *parent;
	struct pcmcia_device *pdev = to_pcmcia_dev(dev);

	/* We are only intereted in device addition */
	if (action != BUS_NOTIFY_ADD_DEVICE)
		return 0;

	parent = pdev->socket->dev.parent;

	/* We know electra_cf devices will always have of_node set, since
	 * electra_cf is an of_platform driver.
	 */
	if (!parent->of_node)
		return 0;

	if (!of_device_is_compatible(parent->of_node, "electra-cf"))
		return 0;

	/* We use the direct ops for localbus */
	dev->archdata.dma_ops = &dma_direct_ops;

	return 0;
}

static struct notifier_block pcmcia_notifier = {
	.notifier_call = pcmcia_notify,
};

static inline void pasemi_pcmcia_init(void)
{
	extern struct bus_type pcmcia_bus_type;

	bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
}

#else

static inline void pasemi_pcmcia_init(void)
{
}

#endif


static struct of_device_id pasemi_bus_ids[] = {
	/* Unfortunately needed for legacy firmwares */
	{ .type = "localbus", },
	{ .type = "sdc", },
	/* These are the proper entries, which newer firmware uses */
	{ .compatible = "pasemi,localbus", },
	{ .compatible = "pasemi,sdc", },
	{},
};

static int __init pasemi_publish_devices(void)
{
	pasemi_pcmcia_init();

	/* Publish OF platform devices for SDC and other non-PCI devices */
	of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);

	return 0;
}
machine_device_initcall(pasemi, pasemi_publish_devices);


/*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
static int __init pas_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
	    !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
		return 0;

	hpte_init_native();

	alloc_iobmap_l2();

	return 1;
}

define_machine(pasemi) {
	.name			= "PA Semi PWRficient",
	.probe			= pas_probe,
	.setup_arch		= pas_setup_arch,
	.init_early		= pas_init_early,
	.init_IRQ		= pas_init_IRQ,
	.get_irq		= mpic_get_irq,
	.restart		= pas_restart,
	.get_boot_time		= pas_get_boot_time,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= pas_progress,
	.machine_check_exception = pas_machine_check_handler,
};
Commit	Line	Data
1e76875e	1	/*
31c56d82	2	* Copyright (C) 2006-2007 PA Semi, Inc
1e76875e OJ	3	*
	4	* Authors: Kip Walker, PA Semi
	5	* Olof Johansson, PA Semi
	6	*
	7	* Maintained by: Olof Johansson <olof@lixom.net>
	8	*
	9	* Based on arch/powerpc/platforms/maple/setup.c
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*/
	24
1e76875e OJ	25	#include <linux/errno.h>
	26	#include <linux/kernel.h>
	27	#include <linux/delay.h>
	28	#include <linux/console.h>
66b15db6	29	#include <linux/export.h>
12d04eef	30	#include <linux/pci.h>
5f867dc7	31	#include <linux/of_platform.h>
5a0e3ad6	32	#include <linux/gfp.h>
1e76875e OJ	33
1e76875e OJ	34	#include <asm/prom.h>
1e76875e OJ	35	#include <asm/iommu.h>
	36	#include <asm/machdep.h>
	37	#include <asm/mpic.h>
	38	#include <asm/smp.h>
	39	#include <asm/time.h>
584f8b71	40	#include <asm/mmu.h>
ae3a197e	41	#include <asm/debug.h>
1e76875e	42
2b571a06 OJ	43	#include <pcmcia/ss.h>
	44	#include <pcmcia/cistpl.h>
	45	#include <pcmcia/ds.h>
	46
1e76875e OJ	47	#include "pasemi.h"
1e76875e OJ	48
cd783416	49	/* SDC reset register, must be pre-mapped at reset time */
f620be99	50	static void __iomem *reset_reg;
1e76875e	51
cd783416 OJ	52	/* Various error status registers, must be pre-mapped at MCE time */
	53
	54	#define MAX_MCE_REGS 32
	55	struct mce_regs {
	56	char *name;
	57	void __iomem *addr;
	58	};
	59
	60	static struct mce_regs mce_regs[MAX_MCE_REGS];
	61	static int num_mce_regs;
f365355e	62	static int nmi_virq = NO_IRQ;
cd783416 OJ	63
cd783416 OJ	64
f620be99	65	static void pas_restart(char *cmd)
1e76875e	66	{
32e2b55e OJ	67	/* Need to put others cpu in hold loop so they're not sleeping */
	68	smp_send_stop();
	69	udelay(10000);
f620be99 OJ	70	printk("Restarting...\n");
	71	while (1)
	72	out_le32(reset_reg, 0x6000000);
1e76875e OJ	73	}
	74
	75	#ifdef CONFIG_SMP
445c8951	76	static arch_spinlock_t timebase_lock;
dc559f7c	77	static unsigned long timebase;
c388cfeb	78
cad5cef6	79	static void pas_give_timebase(void)
c388cfeb	80	{
6893ce6c BH	81	unsigned long flags;
	82
	83	local_irq_save(flags);
	84	hard_irq_disable();
0199c4e6	85	arch_spin_lock(&timebase_lock);
c388cfeb	86	mtspr(SPRN_TBCTL, TBCTL_FREEZE);
dc559f7c OJ	87	isync();
dc559f7c OJ	88	timebase = get_tb();
0199c4e6	89	arch_spin_unlock(&timebase_lock);
dc559f7c OJ	90
	91	while (timebase)
	92	barrier();
	93	mtspr(SPRN_TBCTL, TBCTL_RESTART);
6893ce6c	94	local_irq_restore(flags);
c388cfeb OJ	95	}
c388cfeb OJ	96
cad5cef6	97	static void pas_take_timebase(void)
c388cfeb	98	{
dc559f7c OJ	99	while (!timebase)
	100	smp_rmb();
	101
0199c4e6	102	arch_spin_lock(&timebase_lock);
dc559f7c OJ	103	set_tb(timebase >> 32, timebase & 0xffffffff);
dc559f7c OJ	104	timebase = 0;
0199c4e6	105	arch_spin_unlock(&timebase_lock);
c388cfeb OJ	106	}
c388cfeb OJ	107
1e76875e OJ	108	struct smp_ops_t pas_smp_ops = {
	109	.probe = smp_mpic_probe,
	110	.message_pass = smp_mpic_message_pass,
	111	.kick_cpu = smp_generic_kick_cpu,
	112	.setup_cpu = smp_mpic_setup_cpu,
c388cfeb OJ	113	.give_timebase = pas_give_timebase,
c388cfeb OJ	114	.take_timebase = pas_take_timebase,
1e76875e OJ	115	};
	116	#endif /* CONFIG_SMP */
	117
	118	void __init pas_setup_arch(void)
	119	{
	120	#ifdef CONFIG_SMP
	121	/* Setup SMP callback */
	122	smp_ops = &pas_smp_ops;
	123	#endif
	124	/* Lookup PCI hosts */
	125	pas_pci_init();
	126
	127	#ifdef CONFIG_DUMMY_CONSOLE
	128	conswitchp = &dummy_con;
	129	#endif
	130
f620be99 OJ	131	/* Remap SDC register for doing reset */
	132	/* XXXOJN This should maybe come out of the device tree */
	133	reset_reg = ioremap(0xfc101100, 4);
1e76875e OJ	134	}
1e76875e OJ	135
cd783416 OJ	136	static int __init pas_setup_mce_regs(void)
	137	{
	138	struct pci_dev *dev;
	139	int reg;
	140
cd783416 OJ	141	/* Remap various SoC status registers for use by the MCE handler */
	142
	143	reg = 0;
	144
	145	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
	146	while (dev && reg < MAX_MCE_REGS) {
	147	mce_regs[reg].name = kasprintf(GFP_KERNEL,
	148	"mc%d_mcdebug_errsta", reg);
	149	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
	150	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
	151	reg++;
	152	}
	153
	154	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
	155	if (dev && reg+4 < MAX_MCE_REGS) {
	156	mce_regs[reg].name = "iobdbg_IntStatus1";
	157	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
	158	reg++;
	159	mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
	160	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
	161	reg++;
	162	mce_regs[reg].name = "iobiom_IntStatus";
	163	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
	164	reg++;
	165	mce_regs[reg].name = "iobiom_IntDbgReg";
	166	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
	167	reg++;
	168	}
	169
	170	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
	171	if (dev && reg+2 < MAX_MCE_REGS) {
	172	mce_regs[reg].name = "l2csts_IntStatus";
	173	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
	174	reg++;
	175	mce_regs[reg].name = "l2csts_Cnt";
	176	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
	177	reg++;
	178	}
	179
	180	num_mce_regs = reg;
	181
	182	return 0;
	183	}
bdddec45	184	machine_device_initcall(pasemi, pas_setup_mce_regs);
cd783416	185
1e76875e OJ	186	static __init void pas_init_IRQ(void)
	187	{
	188	struct device_node *np;
	189	struct device_node root, mpic_node;
	190	unsigned long openpic_addr;
	191	const unsigned int *opprop;
	192	int naddr, opplen;
f365355e OJ	193	int mpic_flags;
f365355e OJ	194	const unsigned int *nmiprop;
1e76875e OJ	195	struct mpic *mpic;
	196
	197	mpic_node = NULL;
	198
	199	for_each_node_by_type(np, "interrupt-controller")
55b61fec	200	if (of_device_is_compatible(np, "open-pic")) {
1e76875e OJ	201	mpic_node = np;
	202	break;
	203	}
	204	if (!mpic_node)
	205	for_each_node_by_type(np, "open-pic") {
	206	mpic_node = np;
	207	break;
	208	}
	209	if (!mpic_node) {
	210	printk(KERN_ERR
	211	"Failed to locate the MPIC interrupt controller\n");
	212	return;
	213	}
	214
	215	/* Find address list in /platform-open-pic */
	216	root = of_find_node_by_path("/");
a8bda5dd	217	naddr = of_n_addr_cells(root);
e2eb6392	218	opprop = of_get_property(root, "platform-open-pic", &opplen);
1e76875e OJ	219	if (!opprop) {
	220	printk(KERN_ERR "No platform-open-pic property.\n");
	221	of_node_put(root);
	222	return;
	223	}
	224	openpic_addr = of_read_number(opprop, naddr);
	225	printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
1e76875e	226
e55d7f73	227	mpic_flags = MPIC_LARGE_VECTORS \| MPIC_NO_BIAS \| MPIC_NO_RESET;
f365355e OJ	228
	229	nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
	230	if (nmiprop)
	231	mpic_flags \|= MPIC_ENABLE_MCK;
	232
7df2457d	233	mpic = mpic_alloc(mpic_node, openpic_addr,
f365355e	234	mpic_flags, 0, 0, "PASEMI-OPIC");
1e76875e OJ	235	BUG_ON(!mpic);
1e76875e OJ	236
e7a98675	237	mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
1e76875e	238	mpic_init(mpic);
f365355e OJ	239	/* The NMI/MCK source needs to be prio 15 */
	240	if (nmiprop) {
	241	nmi_virq = irq_create_mapping(NULL, *nmiprop);
	242	mpic_irq_set_priority(nmi_virq, 15);
ec775d0e	243	irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
835c0553	244	mpic_unmask_irq(irq_get_irq_data(nmi_virq));
f365355e OJ	245	}
f365355e OJ	246
1e76875e OJ	247	of_node_put(mpic_node);
	248	of_node_put(root);
	249	}
	250
	251	static void __init pas_progress(char *s, unsigned short hex)
	252	{
	253	printk("[%04x] : %s\n", hex, s ? s : "");
	254	}
	255
	256
bfed9d32 OJ	257	static int pas_machine_check_handler(struct pt_regs *regs)
	258	{
	259	int cpu = smp_processor_id();
	260	unsigned long srr0, srr1, dsisr;
cd783416 OJ	261	int dump_slb = 0;
cd783416 OJ	262	int i;
bfed9d32 OJ	263
	264	srr0 = regs->nip;
	265	srr1 = regs->msr;
f365355e	266
f0d4577c	267	if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
f365355e OJ	268	printk(KERN_ERR "NMI delivered\n");
f365355e OJ	269	debugger(regs);
835c0553	270	mpic_end_irq(irq_get_irq_data(nmi_virq));
f365355e OJ	271	goto out;
	272	}
	273
bfed9d32 OJ	274	dsisr = mfspr(SPRN_DSISR);
bfed9d32 OJ	275	printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
cd783416 OJ	276	printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
	277	printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
	278	printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
	279	mfspr(SPRN_PA6T_MER));
	280	printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
	281	mfspr(SPRN_PA6T_DER));
bfed9d32 OJ	282	printk(KERN_ERR "Cause:\n");
	283
	284	if (srr1 & 0x200000)
	285	printk(KERN_ERR "Signalled by SDC\n");
cd783416	286
bfed9d32 OJ	287	if (srr1 & 0x100000) {
	288	printk(KERN_ERR "Load/Store detected error:\n");
	289	if (dsisr & 0x8000)
	290	printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
	291	if (dsisr & 0x4000)
	292	printk(KERN_ERR "LSU snoop response error\n");
cd783416	293	if (dsisr & 0x2000) {
bfed9d32	294	printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
cd783416 OJ	295	dump_slb = 1;
cd783416 OJ	296	}
bfed9d32 OJ	297	if (dsisr & 0x1000)
	298	printk(KERN_ERR "Recoverable Duptags\n");
	299	if (dsisr & 0x800)
	300	printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
	301	if (dsisr & 0x400)
	302	printk(KERN_ERR "TLB parity error count overflow\n");
	303	}
cd783416	304
bfed9d32 OJ	305	if (srr1 & 0x80000)
bfed9d32 OJ	306	printk(KERN_ERR "Bus Error\n");
cd783416 OJ	307
cd783416 OJ	308	if (srr1 & 0x40000) {
bfed9d32	309	printk(KERN_ERR "I-side SLB multiple hit\n");
cd783416 OJ	310	dump_slb = 1;
	311	}
	312
bfed9d32 OJ	313	if (srr1 & 0x20000)
	314	printk(KERN_ERR "I-cache parity error hit\n");
	315
cd783416 OJ	316	if (num_mce_regs == 0)
	317	printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
	318	else
	319	printk(KERN_ERR "SoC debug registers:\n");
	320
	321	for (i = 0; i < num_mce_regs; i++)
	322	printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
	323	in_le32(mce_regs[i].addr));
	324
	325	if (dump_slb) {
	326	unsigned long e, v;
	327	int i;
	328
	329	printk(KERN_ERR "slb contents:\n");
584f8b71	330	for (i = 0; i < mmu_slb_size; i++) {
cd783416 OJ	331	asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
	332	asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
	333	printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
	334	}
	335	}
	336
f365355e	337	out:
bfed9d32 OJ	338	/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
	339	return !!(srr1 & 0x2);
	340	}
	341
31c56d82 OJ	342	static void __init pas_init_early(void)
	343	{
	344	iommu_init_early_pasemi();
	345	}
	346
2b571a06 OJ	347	#ifdef CONFIG_PCMCIA
	348	static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
	349	void *data)
	350	{
	351	struct device *dev = data;
	352	struct device *parent;
	353	struct pcmcia_device *pdev = to_pcmcia_dev(dev);
	354
	355	/* We are only intereted in device addition */
	356	if (action != BUS_NOTIFY_ADD_DEVICE)
	357	return 0;
	358
	359	parent = pdev->socket->dev.parent;
	360
	361	/* We know electra_cf devices will always have of_node set, since
	362	* electra_cf is an of_platform driver.
	363	*/
58f9b0b0	364	if (!parent->of_node)
2b571a06 OJ	365	return 0;
2b571a06 OJ	366
58f9b0b0	367	if (!of_device_is_compatible(parent->of_node, "electra-cf"))
2b571a06 OJ	368	return 0;
	369
	370	/* We use the direct ops for localbus */
	371	dev->archdata.dma_ops = &dma_direct_ops;
	372
	373	return 0;
	374	}
	375
	376	static struct notifier_block pcmcia_notifier = {
	377	.notifier_call = pcmcia_notify,
	378	};
	379
	380	static inline void pasemi_pcmcia_init(void)
	381	{
	382	extern struct bus_type pcmcia_bus_type;
	383
	384	bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
	385	}
	386
	387	#else
	388
	389	static inline void pasemi_pcmcia_init(void)
	390	{
	391	}
	392
	393	#endif
	394
	395
b97d2791	396	static struct of_device_id pasemi_bus_ids[] = {
0d08a847	397	/* Unfortunately needed for legacy firmwares */
2b571a06	398	{ .type = "localbus", },
b97d2791	399	{ .type = "sdc", },
0d08a847 OJ	400	/* These are the proper entries, which newer firmware uses */
	401	{ .compatible = "pasemi,localbus", },
	402	{ .compatible = "pasemi,sdc", },
b97d2791 OJ	403	{},
	404	};
	405
	406	static int __init pasemi_publish_devices(void)
	407	{
2b571a06 OJ	408	pasemi_pcmcia_init();
2b571a06 OJ	409
90f7afef	410	/* Publish OF platform devices for SDC and other non-PCI devices */
b97d2791 OJ	411	of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
	412
	413	return 0;
	414	}
bdddec45	415	machine_device_initcall(pasemi, pasemi_publish_devices);
b97d2791	416
bfed9d32	417
1e76875e OJ	418	/*
	419	* Called very early, MMU is off, device-tree isn't unflattened
	420	*/
	421	static int __init pas_probe(void)
	422	{
	423	unsigned long root = of_get_flat_dt_root();
	424
0d08a847 OJ	425	if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
0d08a847 OJ	426	!of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
1e76875e OJ	427	return 0;
	428
	429	hpte_init_native();
	430
31c56d82 OJ	431	alloc_iobmap_l2();
31c56d82 OJ	432
1e76875e OJ	433	return 1;
	434	}
	435
d4875a21	436	define_machine(pasemi) {
0d08a847	437	.name = "PA Semi PWRficient",
1e76875e OJ	438	.probe = pas_probe,
1e76875e OJ	439	.setup_arch = pas_setup_arch,
31c56d82	440	.init_early = pas_init_early,
1e76875e OJ	441	.init_IRQ = pas_init_IRQ,
1e76875e OJ	442	.get_irq = mpic_get_irq,
1e76875e	443	.restart = pas_restart,
1e76875e OJ	444	.get_boot_time = pas_get_boot_time,
1e76875e OJ	445	.calibrate_decr = generic_calibrate_decr,
1e76875e	446	.progress = pas_progress,
bfed9d32	447	.machine_check_exception = pas_machine_check_handler,
1e76875e	448	};