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ppc64 iSeries: use device_node instead of iSeries_Device_node
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / platforms / iseries / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
3 *
4 * iSeries specific routines for PCI.
d387899f 5 *
1da177e4
LT		 6 * Based on code from pci.c and iSeries_pci.c 32bit
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
d387899f 12 *
1da177e4
LT		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
d387899f 17 *
1da177e4
LT		 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/kernel.h>
d387899f 23#include <linux/list.h>
1da177e4
LT		 24#include <linux/string.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/ide.h>
28#include <linux/pci.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/prom.h>
33#include <asm/machdep.h>
34#include <asm/pci-bridge.h>
35#include <asm/ppcdebug.h>
36#include <asm/iommu.h>
37
38#include <asm/iSeries/HvCallPci.h>
1da177e4 39#include <asm/iSeries/HvCallXm.h>
1da177e4
LT		 40#include <asm/iSeries/iSeries_irq.h>
41#include <asm/iSeries/iSeries_pci.h>
42#include <asm/iSeries/mf.h>
43
d387899f 44#include <asm/ppc-pci.h>
1da177e4
LT		 45
46extern unsigned long io_page_mask;
47
48/*
d387899f 49 * Forward declares of prototypes.
1da177e4 50 */
252e75a5 51static struct device_node *find_Device_Node(int bus, int devfn);
1da177e4
LT		 52static void scan_PHB_slots(struct pci_controller *Phb);
53static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
54static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
55
56LIST_HEAD(iSeries_Global_Device_List);
57
58static int DeviceCount;
59
60/* Counters and control flags. */
61static long Pci_Io_Read_Count;
62static long Pci_Io_Write_Count;
63#if 0
64static long Pci_Cfg_Read_Count;
65static long Pci_Cfg_Write_Count;
66#endif
67static long Pci_Error_Count;
68
d387899f 69static int Pci_Retry_Max = 3; /* Only retry 3 times */
1da177e4
LT		 70static int Pci_Error_Flag = 1; /* Set Retry Error on. */
71
72static struct pci_ops iSeries_pci_ops;
73
74/*
75 * Table defines
76 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
77 */
78#define IOMM_TABLE_MAX_ENTRIES 1024
79#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
80#define BASE_IO_MEMORY 0xE000000000000000UL
81
82static unsigned long max_io_memory = 0xE000000000000000UL;
83static long current_iomm_table_entry;
84
85/*
86 * Lookup Tables.
87 */
252e75a5 88static struct device_node **iomm_table;
1da177e4
LT		 89static u8 *iobar_table;
90
91/*
92 * Static and Global variables
93 */
94static char *pci_io_text = "iSeries PCI I/O";
95static DEFINE_SPINLOCK(iomm_table_lock);
96
97/*
98 * iomm_table_initialize
99 *
100 * Allocates and initalizes the Address Translation Table and Bar
101 * Tables to get them ready for use. Must be called before any
102 * I/O space is handed out to the device BARs.
103 */
104static void iomm_table_initialize(void)
105{
106 spin_lock(&iomm_table_lock);
107 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
108 GFP_KERNEL);
109 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
110 GFP_KERNEL);
111 spin_unlock(&iomm_table_lock);
112 if ((iomm_table == NULL) || (iobar_table == NULL))
113 panic("PCI: I/O tables allocation failed.\n");
114}
115
116/*
117 * iomm_table_allocate_entry
118 *
119 * Adds pci_dev entry in address translation table
120 *
121 * - Allocates the number of entries required in table base on BAR
122 * size.
123 * - Allocates starting at BASE_IO_MEMORY and increases.
124 * - The size is round up to be a multiple of entry size.
125 * - CurrentIndex is incremented to keep track of the last entry.
126 * - Builds the resource entry for allocated BARs.
127 */
128static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
129{
130 struct resource *bar_res = &dev->resource[bar_num];
131 long bar_size = pci_resource_len(dev, bar_num);
132
133 /*
134 * No space to allocate, quick exit, skip Allocation.
135 */
136 if (bar_size == 0)
137 return;
138 /*
139 * Set Resource values.
140 */
141 spin_lock(&iomm_table_lock);
142 bar_res->name = pci_io_text;
143 bar_res->start =
144 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
145 bar_res->start += BASE_IO_MEMORY;
146 bar_res->end = bar_res->start + bar_size - 1;
147 /*
148 * Allocate the number of table entries needed for BAR.
149 */
150 while (bar_size > 0 ) {
151 iomm_table[current_iomm_table_entry] = dev->sysdata;
152 iobar_table[current_iomm_table_entry] = bar_num;
153 bar_size -= IOMM_TABLE_ENTRY_SIZE;
154 ++current_iomm_table_entry;
155 }
156 max_io_memory = BASE_IO_MEMORY +
157 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
158 spin_unlock(&iomm_table_lock);
159}
160
161/*
162 * allocate_device_bars
163 *
164 * - Allocates ALL pci_dev BAR's and updates the resources with the
165 * BAR value. BARS with zero length will have the resources
166 * The HvCallPci_getBarParms is used to get the size of the BAR
167 * space. It calls iomm_table_allocate_entry to allocate
168 * each entry.
169 * - Loops through The Bar resources(0 - 5) including the ROM
170 * is resource(6).
171 */
172static void allocate_device_bars(struct pci_dev *dev)
173{
174 struct resource *bar_res;
175 int bar_num;
176
177 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
178 bar_res = &dev->resource[bar_num];
179 iomm_table_allocate_entry(dev, bar_num);
d387899f 180 }
1da177e4
LT		 181}
182
183/*
184 * Log error information to system console.
185 * Filter out the device not there errors.
186 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
187 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
188 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
189 */
190static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
191 int AgentId, int HvRc)
192{
193 if (HvRc == 0x0302)
194 return;
195 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
196 Error_Text, Bus, SubBus, AgentId, HvRc);
197}
198
199/*
200 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
201 */
252e75a5 202static struct device_node *build_device_node(HvBusNumber Bus,
1da177e4
LT		 203 HvSubBusNumber SubBus, int AgentId, int Function)
204{
252e75a5
SR		 205 struct device_node *node;
206 struct pci_dn *pdn;
1da177e4
LT		 207
208 PPCDBG(PPCDBG_BUSWALK,
209 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
210 Bus, SubBus, AgentId, Function);
211
252e75a5 212 node = kmalloc(sizeof(struct device_node), GFP_KERNEL);
1da177e4
LT		 213 if (node == NULL)
214 return NULL;
252e75a5
SR		 215 memset(node, 0, sizeof(struct device_node));
216 pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
217 if (pdn == NULL) {
218 kfree(node);
219 return NULL;
220 }
221 node->data = pdn;
1da177e4
LT		 222 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
223#if 0
252e75a5 224 pdn->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
1da177e4 225#endif
252e75a5
SR		 226 pdn->DsaAddr.DsaAddr = 0;
227 pdn->DsaAddr.Dsa.busNumber = Bus;
228 pdn->DsaAddr.Dsa.subBusNumber = SubBus;
229 pdn->DsaAddr.Dsa.deviceId = 0x10;
230 pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
1da177e4
LT		 231 return node;
232}
233
234/*
235 * unsigned long __init find_and_init_phbs(void)
236 *
237 * Description:
238 * This function checks for all possible system PCI host bridges that connect
239 * PCI buses. The system hypervisor is queried as to the guest partition
240 * ownership status. A pci_controller is built for any bus which is partially
241 * owned or fully owned by this guest partition.
242 */
243unsigned long __init find_and_init_phbs(void)
244{
245 struct pci_controller *phb;
246 HvBusNumber bus;
247
248 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
249
250 /* Check all possible buses. */
251 for (bus = 0; bus < 256; bus++) {
252 int ret = HvCallXm_testBus(bus);
253 if (ret == 0) {
254 printk("bus %d appears to exist\n", bus);
255
256 phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
257 if (phb == NULL)
258 return -ENOMEM;
3238e9c9 259 pci_setup_pci_controller(phb);
1da177e4
LT		 260
261 phb->pci_mem_offset = phb->local_number = bus;
262 phb->first_busno = bus;
263 phb->last_busno = bus;
264 phb->ops = &iSeries_pci_ops;
265
266 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
267 phb, bus);
268
269 /* Find and connect the devices. */
270 scan_PHB_slots(phb);
271 }
272 /*
273 * Check for Unexpected Return code, a clue that something
274 * has gone wrong.
275 */
276 else if (ret != 0x0301)
277 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
278 bus, ret);
279 }
280 return 0;
281}
282
283/*
284 * iSeries_pcibios_init
d387899f 285 *
1da177e4
LT		 286 * Chance to initialize and structures or variable before PCI Bus walk.
287 */
288void iSeries_pcibios_init(void)
289{
d387899f 290 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
1da177e4
LT		 291 iomm_table_initialize();
292 find_and_init_phbs();
293 io_page_mask = -1;
d387899f 294 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
1da177e4
LT		 295}
296
297/*
d387899f 298 * iSeries_pci_final_fixup(void)
1da177e4
LT		 299 */
300void __init iSeries_pci_final_fixup(void)
301{
302 struct pci_dev *pdev = NULL;
252e75a5 303 struct device_node *node;
d387899f 304 int DeviceCount = 0;
1da177e4 305
d387899f 306 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
1da177e4
LT		 307
308 /* Fix up at the device node and pci_dev relationship */
309 mf_display_src(0xC9000100);
310
311 printk("pcibios_final_fixup\n");
312 for_each_pci_dev(pdev) {
313 node = find_Device_Node(pdev->bus->number, pdev->devfn);
314 printk("pci dev %p (%x.%x), node %p\n", pdev,
315 pdev->bus->number, pdev->devfn, node);
316
317 if (node != NULL) {
318 ++DeviceCount;
319 pdev->sysdata = (void *)node;
252e75a5 320 PCI_DN(node)->pcidev = pdev;
1da177e4
LT		 321 PPCDBG(PPCDBG_BUSWALK,
322 "pdev 0x%p <==> DevNode 0x%p\n",
323 pdev, node);
324 allocate_device_bars(pdev);
061c063e 325 iSeries_Device_Information(pdev, DeviceCount);
1da177e4
LT		 326 iommu_devnode_init_iSeries(node);
327 } else
328 printk("PCI: Device Tree not found for 0x%016lX\n",
329 (unsigned long)pdev);
252e75a5 330 pdev->irq = PCI_DN(node)->Irq;
1da177e4
LT		 331 }
332 iSeries_activate_IRQs();
333 mf_display_src(0xC9000200);
334}
335
336void pcibios_fixup_bus(struct pci_bus *PciBus)
337{
338 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
d387899f 339 PciBus->number);
1da177e4
LT		 340}
341
342void pcibios_fixup_resources(struct pci_dev *pdev)
343{
344 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
d387899f 345}
1da177e4
LT		 346
347/*
d387899f 348 * Loop through each node function to find usable EADs bridges.
1da177e4
LT		 349 */
350static void scan_PHB_slots(struct pci_controller *Phb)
351{
352 struct HvCallPci_DeviceInfo *DevInfo;
d387899f 353 HvBusNumber bus = Phb->local_number; /* System Bus */
1da177e4
LT		 354 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
355 int HvRc = 0;
d387899f 356 int IdSel;
1da177e4
LT		 357 const int MaxAgents = 8;
358
359 DevInfo = (struct HvCallPci_DeviceInfo*)
360 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
361 if (DevInfo == NULL)
362 return;
363
364 /*
d387899f 365 * Probe for EADs Bridges
1da177e4
LT		 366 */
367 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
d387899f 368 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
1da177e4
LT		 369 ISERIES_HV_ADDR(DevInfo),
370 sizeof(struct HvCallPci_DeviceInfo));
371 if (HvRc == 0) {
372 if (DevInfo->deviceType == HvCallPci_NodeDevice)
373 scan_EADS_bridge(bus, SubBus, IdSel);
374 else
375 printk("PCI: Invalid System Configuration(0x%02X)"
376 " for bus 0x%02x id 0x%02x.\n",
377 DevInfo->deviceType, bus, IdSel);
378 }
379 else
380 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
381 }
382 kfree(DevInfo);
383}
384
385static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
386 int IdSel)
387{
388 struct HvCallPci_BridgeInfo *BridgeInfo;
389 HvAgentId AgentId;
390 int Function;
391 int HvRc;
392
393 BridgeInfo = (struct HvCallPci_BridgeInfo *)
394 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
395 if (BridgeInfo == NULL)
396 return;
397
398 /* Note: hvSubBus and irq is always be 0 at this level! */
399 for (Function = 0; Function < 8; ++Function) {
d387899f 400 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
1da177e4 401 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
d387899f 402 if (HvRc == 0) {
1da177e4
LT		 403 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
404 bus, IdSel, Function, AgentId);
d387899f 405 /* Connect EADs: 0x18.00.12 = 0x00 */
1da177e4
LT		 406 PPCDBG(PPCDBG_BUSWALK,
407 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
408 bus, SubBus, AgentId);
d387899f 409 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
1da177e4
LT		 410 ISERIES_HV_ADDR(BridgeInfo),
411 sizeof(struct HvCallPci_BridgeInfo));
d387899f 412 if (HvRc == 0) {
1da177e4
LT		 413 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
414 BridgeInfo->busUnitInfo.deviceType,
415 BridgeInfo->subBusNumber,
416 BridgeInfo->maxAgents,
417 BridgeInfo->maxSubBusNumber,
418 BridgeInfo->logicalSlotNumber);
419 PPCDBG(PPCDBG_BUSWALK,
420 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
421 BridgeInfo->busUnitInfo.deviceType,
422 BridgeInfo->subBusNumber,
423 BridgeInfo->maxAgents,
424 BridgeInfo->maxSubBusNumber,
425 BridgeInfo->logicalSlotNumber);
426
427 if (BridgeInfo->busUnitInfo.deviceType ==
428 HvCallPci_BridgeDevice) {
429 /* Scan_Bridge_Slot...: 0x18.00.12 */
430 scan_bridge_slot(bus, BridgeInfo);
431 } else
432 printk("PCI: Invalid Bridge Configuration(0x%02X)",
433 BridgeInfo->busUnitInfo.deviceType);
434 }
d387899f 435 } else if (HvRc != 0x000B)
1da177e4
LT		 436 pci_Log_Error("EADs Connect",
437 bus, SubBus, AgentId, HvRc);
438 }
439 kfree(BridgeInfo);
440}
441
442/*
443 * This assumes that the node slot is always on the primary bus!
444 */
445static int scan_bridge_slot(HvBusNumber Bus,
446 struct HvCallPci_BridgeInfo *BridgeInfo)
447{
252e75a5 448 struct device_node *node;
1da177e4
LT		 449 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
450 u16 VendorId = 0;
451 int HvRc = 0;
452 u8 Irq = 0;
453 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
454 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
455 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
456
457 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
d387899f 458 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
1da177e4
LT		 459 PPCDBG(PPCDBG_BUSWALK,
460 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
461 Bus, 0, EADsIdSel, Irq);
462
463 /*
d387899f 464 * Connect all functions of any device found.
1da177e4 465 */
d387899f
SR		 466 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
467 for (Function = 0; Function < 8; ++Function) {
1da177e4
LT		 468 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
469 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
470 AgentId, Irq);
471 if (HvRc != 0) {
472 pci_Log_Error("Connect Bus Unit",
473 Bus, SubBus, AgentId, HvRc);
474 continue;
475 }
476
477 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
478 PCI_VENDOR_ID, &VendorId);
479 if (HvRc != 0) {
480 pci_Log_Error("Read Vendor",
481 Bus, SubBus, AgentId, HvRc);
482 continue;
483 }
484 printk("read vendor ID: %x\n", VendorId);
485
486 /* FoundDevice: 0x18.28.10 = 0x12AE */
487 PPCDBG(PPCDBG_BUSWALK,
488 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
489 Bus, SubBus, AgentId, VendorId, Irq);
490 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
d387899f 491 PCI_INTERRUPT_LINE, Irq);
1da177e4
LT		 492 if (HvRc != 0)
493 pci_Log_Error("PciCfgStore Irq Failed!",
494 Bus, SubBus, AgentId, HvRc);
495
496 ++DeviceCount;
497 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
252e75a5
SR		 498 PCI_DN(node)->Irq = Irq;
499 PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber;
1da177e4
LT		 500
501 } /* for (Function = 0; Function < 8; ++Function) */
502 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
503 return HvRc;
504}
505
506/*
507 * I/0 Memory copy MUST use mmio commands on iSeries
508 * To do; For performance, include the hv call directly
509 */
510void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
511{
512 u8 ByteValue = c;
513 long NumberOfBytes = Count;
514
515 while (NumberOfBytes > 0) {
516 iSeries_Write_Byte(ByteValue, dest++);
517 -- NumberOfBytes;
518 }
519}
520EXPORT_SYMBOL(iSeries_memset_io);
521
522void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
523{
524 char *src = source;
525 long NumberOfBytes = count;
526
527 while (NumberOfBytes > 0) {
528 iSeries_Write_Byte(*src++, dest++);
529 -- NumberOfBytes;
530 }
531}
532EXPORT_SYMBOL(iSeries_memcpy_toio);
533
534void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
535{
536 char *dst = dest;
537 long NumberOfBytes = count;
538
539 while (NumberOfBytes > 0) {
540 *dst++ = iSeries_Read_Byte(src++);
541 -- NumberOfBytes;
542 }
543}
544EXPORT_SYMBOL(iSeries_memcpy_fromio);
545
546/*
547 * Look down the chain to find the matching Device Device
548 */
252e75a5 549static struct device_node *find_Device_Node(int bus, int devfn)
1da177e4
LT		 550{
551 struct list_head *pos;
552
553 list_for_each(pos, &iSeries_Global_Device_List) {
252e75a5
SR		 554 struct device_node *node =
555 list_entry(pos, struct device_node, Device_List);
1da177e4 556
252e75a5
SR		 557 if ((bus == ISERIES_BUS(node)) &&
558 (devfn == PCI_DN(node)->devfn))
1da177e4
LT		 559 return node;
560 }
561 return NULL;
562}
563
564#if 0
565/*
566 * Returns the device node for the passed pci_dev
567 * Sanity Check Node PciDev to passed pci_dev
568 * If none is found, returns a NULL which the client must handle.
569 */
252e75a5 570static struct device_node *get_Device_Node(struct pci_dev *pdev)
1da177e4 571{
252e75a5 572 struct device_node *node;
1da177e4
LT		 573
574 node = pdev->sysdata;
252e75a5 575 if (node == NULL || PCI_DN(node)->pcidev != pdev)
1da177e4
LT		 576 node = find_Device_Node(pdev->bus->number, pdev->devfn);
577 return node;
578}
579#endif
580
581/*
582 * Config space read and write functions.
583 * For now at least, we look for the device node for the bus and devfn
584 * that we are asked to access. It may be possible to translate the devfn
585 * to a subbus and deviceid more directly.
586 */
587static u64 hv_cfg_read_func[4] = {
588 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
589 HvCallPciConfigLoad32, HvCallPciConfigLoad32
590};
591
592static u64 hv_cfg_write_func[4] = {
593 HvCallPciConfigStore8, HvCallPciConfigStore16,
594 HvCallPciConfigStore32, HvCallPciConfigStore32
595};
596
597/*
598 * Read PCI config space
599 */
600static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
601 int offset, int size, u32 *val)
602{
252e75a5 603 struct device_node *node = find_Device_Node(bus->number, devfn);
1da177e4
LT		 604 u64 fn;
605 struct HvCallPci_LoadReturn ret;
606
607 if (node == NULL)
608 return PCIBIOS_DEVICE_NOT_FOUND;
609 if (offset > 255) {
610 *val = ~0;
611 return PCIBIOS_BAD_REGISTER_NUMBER;
612 }
613
614 fn = hv_cfg_read_func[(size - 1) & 3];
252e75a5 615 HvCall3Ret16(fn, &ret, PCI_DN(node)->DsaAddr.DsaAddr, offset, 0);
1da177e4
LT		 616
617 if (ret.rc != 0) {
618 *val = ~0;
619 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
620 }
621
622 *val = ret.value;
623 return 0;
624}
625
626/*
627 * Write PCI config space
628 */
629
630static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
631 int offset, int size, u32 val)
632{
252e75a5 633 struct device_node *node = find_Device_Node(bus->number, devfn);
1da177e4
LT		 634 u64 fn;
635 u64 ret;
636
637 if (node == NULL)
638 return PCIBIOS_DEVICE_NOT_FOUND;
639 if (offset > 255)
640 return PCIBIOS_BAD_REGISTER_NUMBER;
641
642 fn = hv_cfg_write_func[(size - 1) & 3];
252e75a5 643 ret = HvCall4(fn, PCI_DN(node)->DsaAddr.DsaAddr, offset, val, 0);
1da177e4
LT		 644
645 if (ret != 0)
646 return PCIBIOS_DEVICE_NOT_FOUND;
647
648 return 0;
649}
650
651static struct pci_ops iSeries_pci_ops = {
652 .read = iSeries_pci_read_config,
653 .write = iSeries_pci_write_config
654};
655
656/*
657 * Check Return Code
658 * -> On Failure, print and log information.
659 * Increment Retry Count, if exceeds max, panic partition.
1da177e4
LT		 660 *
661 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
662 * PCI: Device 23.90 ReadL Retry( 1)
663 * PCI: Device 23.90 ReadL Retry Successful(1)
664 */
252e75a5 665static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
a2ebaf25 666 int *retry, u64 ret)
1da177e4
LT		 667{
668 if (ret != 0) {
252e75a5
SR		 669 struct pci_dn *pdn = PCI_DN(DevNode);
670
1da177e4 671 ++Pci_Error_Count;
a2ebaf25 672 (*retry)++;
1da177e4 673 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
252e75a5 674 TextHdr, pdn->DsaAddr.Dsa.busNumber, pdn->devfn,
a2ebaf25 675 *retry, (int)ret);
1da177e4
LT		 676 /*
677 * Bump the retry and check for retry count exceeded.
678 * If, Exceeded, panic the system.
679 */
a2ebaf25 680 if (((*retry) > Pci_Retry_Max) &&
1da177e4
LT		 681 (Pci_Error_Flag > 0)) {
682 mf_display_src(0xB6000103);
a2ebaf25 683 panic_timeout = 0;
1da177e4
LT		 684 panic("PCI: Hardware I/O Error, SRC B6000103, "
685 "Automatic Reboot Disabled.\n");
686 }
687 return -1; /* Retry Try */
688 }
a2ebaf25 689 return 0;
1da177e4
LT		 690}
691
692/*
693 * Translate the I/O Address into a device node, bar, and bar offset.
694 * Note: Make sure the passed variable end up on the stack to avoid
695 * the exposure of being device global.
696 */
252e75a5 697static inline struct device_node *xlate_iomm_address(
1da177e4
LT		 698 const volatile void __iomem *IoAddress,
699 u64 *dsaptr, u64 *BarOffsetPtr)
700{
701 unsigned long OrigIoAddr;
702 unsigned long BaseIoAddr;
703 unsigned long TableIndex;
252e75a5 704 struct device_node *DevNode;
1da177e4
LT		 705
706 OrigIoAddr = (unsigned long __force)IoAddress;
707 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
708 return NULL;
709 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
710 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
711 DevNode = iomm_table[TableIndex];
712
713 if (DevNode != NULL) {
714 int barnum = iobar_table[TableIndex];
252e75a5 715 *dsaptr = PCI_DN(DevNode)->DsaAddr.DsaAddr | (barnum << 24);
1da177e4
LT		 716 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
717 } else
718 panic("PCI: Invalid PCI IoAddress detected!\n");
719 return DevNode;
720}
721
722/*
723 * Read MM I/O Instructions for the iSeries
724 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
725 * else, data is returned in big Endian format.
726 *
727 * iSeries_Read_Byte = Read Byte ( 8 bit)
728 * iSeries_Read_Word = Read Word (16 bit)
729 * iSeries_Read_Long = Read Long (32 bit)
730 */
731u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
732{
733 u64 BarOffset;
734 u64 dsa;
a2ebaf25 735 int retry = 0;
1da177e4 736 struct HvCallPci_LoadReturn ret;
252e75a5 737 struct device_node *DevNode =
1da177e4
LT		 738 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
739
740 if (DevNode == NULL) {
741 static unsigned long last_jiffies;
742 static int num_printed;
743
744 if ((jiffies - last_jiffies) > 60 * HZ) {
745 last_jiffies = jiffies;
746 num_printed = 0;
747 }
748 if (num_printed++ < 10)
749 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
750 return 0xff;
751 }
752 do {
753 ++Pci_Io_Read_Count;
754 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
a2ebaf25 755 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
1da177e4
LT		 756
757 return (u8)ret.value;
758}
759EXPORT_SYMBOL(iSeries_Read_Byte);
760
761u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
762{
763 u64 BarOffset;
764 u64 dsa;
a2ebaf25 765 int retry = 0;
1da177e4 766 struct HvCallPci_LoadReturn ret;
252e75a5 767 struct device_node *DevNode =
1da177e4
LT		 768 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
769
770 if (DevNode == NULL) {
771 static unsigned long last_jiffies;
772 static int num_printed;
773
774 if ((jiffies - last_jiffies) > 60 * HZ) {
775 last_jiffies = jiffies;
776 num_printed = 0;
777 }
778 if (num_printed++ < 10)
779 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
780 return 0xffff;
781 }
782 do {
783 ++Pci_Io_Read_Count;
784 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
785 BarOffset, 0);
a2ebaf25 786 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
1da177e4
LT		 787
788 return swab16((u16)ret.value);
789}
790EXPORT_SYMBOL(iSeries_Read_Word);
791
792u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
793{
794 u64 BarOffset;
795 u64 dsa;
a2ebaf25 796 int retry = 0;
1da177e4 797 struct HvCallPci_LoadReturn ret;
252e75a5 798 struct device_node *DevNode =
1da177e4
LT		 799 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
800
801 if (DevNode == NULL) {
802 static unsigned long last_jiffies;
803 static int num_printed;
804
805 if ((jiffies - last_jiffies) > 60 * HZ) {
806 last_jiffies = jiffies;
807 num_printed = 0;
808 }
809 if (num_printed++ < 10)
810 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
811 return 0xffffffff;
812 }
813 do {
814 ++Pci_Io_Read_Count;
815 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
816 BarOffset, 0);
a2ebaf25 817 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
1da177e4
LT		 818
819 return swab32((u32)ret.value);
820}
821EXPORT_SYMBOL(iSeries_Read_Long);
822
823/*
824 * Write MM I/O Instructions for the iSeries
825 *
826 * iSeries_Write_Byte = Write Byte (8 bit)
827 * iSeries_Write_Word = Write Word(16 bit)
828 * iSeries_Write_Long = Write Long(32 bit)
829 */
830void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
831{
832 u64 BarOffset;
833 u64 dsa;
a2ebaf25 834 int retry = 0;
1da177e4 835 u64 rc;
252e75a5 836 struct device_node *DevNode =
1da177e4
LT		 837 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
838
839 if (DevNode == NULL) {
840 static unsigned long last_jiffies;
841 static int num_printed;
842
843 if ((jiffies - last_jiffies) > 60 * HZ) {
844 last_jiffies = jiffies;
845 num_printed = 0;
846 }
847 if (num_printed++ < 10)
848 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
849 return;
850 }
851 do {
852 ++Pci_Io_Write_Count;
853 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
a2ebaf25 854 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
1da177e4
LT		 855}
856EXPORT_SYMBOL(iSeries_Write_Byte);
857
858void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
859{
860 u64 BarOffset;
861 u64 dsa;
a2ebaf25 862 int retry = 0;
1da177e4 863 u64 rc;
252e75a5 864 struct device_node *DevNode =
1da177e4
LT		 865 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
866
867 if (DevNode == NULL) {
868 static unsigned long last_jiffies;
869 static int num_printed;
870
871 if ((jiffies - last_jiffies) > 60 * HZ) {
872 last_jiffies = jiffies;
873 num_printed = 0;
874 }
875 if (num_printed++ < 10)
876 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
877 return;
878 }
879 do {
880 ++Pci_Io_Write_Count;
881 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
a2ebaf25 882 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
1da177e4
LT		 883}
884EXPORT_SYMBOL(iSeries_Write_Word);
885
886void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
887{
888 u64 BarOffset;
889 u64 dsa;
a2ebaf25 890 int retry = 0;
1da177e4 891 u64 rc;
252e75a5 892 struct device_node *DevNode =
1da177e4
LT		 893 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
894
895 if (DevNode == NULL) {
896 static unsigned long last_jiffies;
897 static int num_printed;
898
899 if ((jiffies - last_jiffies) > 60 * HZ) {
900 last_jiffies = jiffies;
901 num_printed = 0;
902 }
903 if (num_printed++ < 10)
904 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
905 return;
906 }
907 do {
908 ++Pci_Io_Write_Count;
909 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
a2ebaf25 910 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
1da177e4
LT		 911}
912EXPORT_SYMBOL(iSeries_Write_Long);
kernel source for telekom puls (alcatel/mediatek)