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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
28 | ||
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
78 | ||
79 | #define SPRN_MMCRA SPRN_MMCR2 | |
80 | #define MMCRA_SAMPLE_ENABLE 0 | |
81 | ||
82 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
83 | { | |
84 | return 0; | |
85 | } | |
98fb1807 PM |
86 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
87 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
88 | { | |
89 | return 0; | |
90 | } | |
75382aa7 AB |
91 | static inline void perf_read_regs(struct pt_regs *regs) |
92 | { | |
93 | regs->result = 0; | |
94 | } | |
98fb1807 PM |
95 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
96 | { | |
97 | return 0; | |
98 | } | |
99 | ||
e6878835 | 100 | static inline int siar_valid(struct pt_regs *regs) |
101 | { | |
102 | return 1; | |
103 | } | |
104 | ||
d52f2dc4 MN |
105 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
106 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
107 | void power_pmu_flush_branch_stack(void) {} | |
108 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
98fb1807 PM |
109 | #endif /* CONFIG_PPC32 */ |
110 | ||
33904054 ME |
111 | static bool regs_use_siar(struct pt_regs *regs) |
112 | { | |
113 | return !!(regs->result & 1); | |
114 | } | |
115 | ||
98fb1807 PM |
116 | /* |
117 | * Things that are specific to 64-bit implementations. | |
118 | */ | |
119 | #ifdef CONFIG_PPC64 | |
120 | ||
121 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
122 | { | |
123 | unsigned long mmcra = regs->dsisr; | |
124 | ||
7a786832 | 125 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
126 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
127 | if (slot > 1) | |
128 | return 4 * (slot - 1); | |
129 | } | |
7a786832 | 130 | |
98fb1807 PM |
131 | return 0; |
132 | } | |
133 | ||
98fb1807 PM |
134 | /* |
135 | * The user wants a data address recorded. | |
136 | * If we're not doing instruction sampling, give them the SDAR | |
137 | * (sampled data address). If we are doing instruction sampling, then | |
138 | * only give them the SDAR if it corresponds to the instruction | |
e6878835 | 139 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or |
140 | * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. | |
98fb1807 PM |
141 | */ |
142 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
143 | { | |
144 | unsigned long mmcra = regs->dsisr; | |
e6878835 | 145 | unsigned long sdsync; |
146 | ||
147 | if (ppmu->flags & PPMU_SIAR_VALID) | |
148 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
149 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
150 | sdsync = POWER6_MMCRA_SDSYNC; | |
151 | else | |
152 | sdsync = MMCRA_SDSYNC; | |
98fb1807 PM |
153 | |
154 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
155 | *addrp = mfspr(SPRN_SDAR); | |
156 | } | |
157 | ||
5682c460 | 158 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
159 | { |
160 | unsigned long sihv = MMCRA_SIHV; | |
161 | ||
8f61aa32 ME |
162 | if (ppmu->flags & PPMU_HAS_SIER) |
163 | return !!(regs->dar & SIER_SIHV); | |
164 | ||
68b30bb9 AB |
165 | if (ppmu->flags & PPMU_ALT_SIPR) |
166 | sihv = POWER6_MMCRA_SIHV; | |
167 | ||
5682c460 | 168 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
169 | } |
170 | ||
5682c460 | 171 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
172 | { |
173 | unsigned long sipr = MMCRA_SIPR; | |
174 | ||
8f61aa32 ME |
175 | if (ppmu->flags & PPMU_HAS_SIER) |
176 | return !!(regs->dar & SIER_SIPR); | |
177 | ||
68b30bb9 AB |
178 | if (ppmu->flags & PPMU_ALT_SIPR) |
179 | sipr = POWER6_MMCRA_SIPR; | |
180 | ||
5682c460 | 181 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
182 | } |
183 | ||
860aad71 ME |
184 | static bool regs_no_sipr(struct pt_regs *regs) |
185 | { | |
186 | return !!(regs->result & 2); | |
187 | } | |
188 | ||
1ce447b9 BH |
189 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
190 | { | |
191 | if (regs->msr & MSR_PR) | |
192 | return PERF_RECORD_MISC_USER; | |
193 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
194 | return PERF_RECORD_MISC_HYPERVISOR; | |
195 | return PERF_RECORD_MISC_KERNEL; | |
196 | } | |
197 | ||
98fb1807 PM |
198 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
199 | { | |
33904054 | 200 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 201 | |
75382aa7 | 202 | if (!use_siar) |
1ce447b9 BH |
203 | return perf_flags_from_msr(regs); |
204 | ||
205 | /* | |
206 | * If we don't have flags in MMCRA, rather than using | |
207 | * the MSR, we intuit the flags from the address in | |
208 | * SIAR which should give slightly more reliable | |
209 | * results | |
210 | */ | |
860aad71 | 211 | if (regs_no_sipr(regs)) { |
1ce447b9 BH |
212 | unsigned long siar = mfspr(SPRN_SIAR); |
213 | if (siar >= PAGE_OFFSET) | |
214 | return PERF_RECORD_MISC_KERNEL; | |
215 | return PERF_RECORD_MISC_USER; | |
216 | } | |
98fb1807 | 217 | |
7abb840b | 218 | /* PR has priority over HV, so order below is important */ |
5682c460 | 219 | if (regs_sipr(regs)) |
7abb840b | 220 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
221 | |
222 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 223 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 224 | |
7abb840b | 225 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
226 | } |
227 | ||
228 | /* | |
229 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
230 | * on each interrupt. | |
8f61aa32 | 231 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
232 | * Overload regs->result to specify whether we should use the MSR (result |
233 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
234 | */ |
235 | static inline void perf_read_regs(struct pt_regs *regs) | |
236 | { | |
75382aa7 AB |
237 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
238 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
239 | int use_siar; | |
240 | ||
5682c460 | 241 | regs->dsisr = mmcra; |
860aad71 ME |
242 | regs->result = 0; |
243 | ||
244 | if (ppmu->flags & PPMU_NO_SIPR) | |
245 | regs->result |= 2; | |
5682c460 | 246 | |
8f61aa32 ME |
247 | /* |
248 | * On power8 if we're in random sampling mode, the SIER is updated. | |
249 | * If we're in continuous sampling mode, we don't have SIPR. | |
250 | */ | |
251 | if (ppmu->flags & PPMU_HAS_SIER) { | |
252 | if (marked) | |
253 | regs->dar = mfspr(SPRN_SIER); | |
254 | else | |
255 | regs->result |= 2; | |
256 | } | |
257 | ||
258 | ||
5c093efa AB |
259 | /* |
260 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
261 | * not valid. Use pt_regs. | |
262 | * | |
263 | * If it is a marked event use the SIAR. | |
264 | * | |
265 | * If the PMU doesn't update the SIAR for non marked events use | |
266 | * pt_regs. | |
267 | * | |
268 | * If the PMU has HV/PR flags then check to see if they | |
269 | * place the exception in userspace. If so, use pt_regs. In | |
270 | * continuous sampling mode the SIAR and the PMU exception are | |
271 | * not synchronised, so they may be many instructions apart. | |
272 | * This can result in confusing backtraces. We still want | |
273 | * hypervisor samples as well as samples in the kernel with | |
274 | * interrupts off hence the userspace check. | |
275 | */ | |
75382aa7 AB |
276 | if (TRAP(regs) != 0xf00) |
277 | use_siar = 0; | |
5c093efa AB |
278 | else if (marked) |
279 | use_siar = 1; | |
280 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
281 | use_siar = 0; | |
860aad71 | 282 | else if (!regs_no_sipr(regs) && regs_sipr(regs)) |
75382aa7 AB |
283 | use_siar = 0; |
284 | else | |
285 | use_siar = 1; | |
286 | ||
860aad71 | 287 | regs->result |= use_siar; |
98fb1807 PM |
288 | } |
289 | ||
290 | /* | |
291 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
292 | * it as an NMI. | |
293 | */ | |
294 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
295 | { | |
296 | return !regs->softe; | |
297 | } | |
298 | ||
e6878835 | 299 | /* |
300 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
301 | * must be sampled only if the SIAR-valid bit is set. | |
302 | * | |
303 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
304 | * bit, assume that SIAR is valid. | |
305 | */ | |
306 | static inline int siar_valid(struct pt_regs *regs) | |
307 | { | |
308 | unsigned long mmcra = regs->dsisr; | |
309 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
310 | ||
311 | if ((ppmu->flags & PPMU_SIAR_VALID) && marked) | |
312 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
313 | ||
314 | return 1; | |
315 | } | |
316 | ||
d52f2dc4 MN |
317 | |
318 | /* Reset all possible BHRB entries */ | |
319 | static void power_pmu_bhrb_reset(void) | |
320 | { | |
321 | asm volatile(PPC_CLRBHRB); | |
322 | } | |
323 | ||
324 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
325 | { | |
326 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
327 | ||
328 | if (!ppmu->bhrb_nr) | |
329 | return; | |
330 | ||
331 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
332 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
333 | power_pmu_bhrb_reset(); | |
334 | cpuhw->bhrb_context = event->ctx; | |
335 | } | |
336 | cpuhw->bhrb_users++; | |
337 | } | |
338 | ||
339 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
340 | { | |
341 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
342 | ||
343 | if (!ppmu->bhrb_nr) | |
344 | return; | |
345 | ||
346 | cpuhw->bhrb_users--; | |
347 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
348 | ||
349 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
350 | /* BHRB cannot be turned off when other | |
351 | * events are active on the PMU. | |
352 | */ | |
353 | ||
354 | /* avoid stale pointer */ | |
355 | cpuhw->bhrb_context = NULL; | |
356 | } | |
357 | } | |
358 | ||
359 | /* Called from ctxsw to prevent one process's branch entries to | |
360 | * mingle with the other process's entries during context switch. | |
361 | */ | |
362 | void power_pmu_flush_branch_stack(void) | |
363 | { | |
364 | if (ppmu->bhrb_nr) | |
365 | power_pmu_bhrb_reset(); | |
366 | } | |
69123184 MN |
367 | /* Calculate the to address for a branch */ |
368 | static __u64 power_pmu_bhrb_to(u64 addr) | |
369 | { | |
370 | unsigned int instr; | |
371 | int ret; | |
372 | __u64 target; | |
373 | ||
374 | if (is_kernel_addr(addr)) | |
375 | return branch_target((unsigned int *)addr); | |
376 | ||
377 | /* Userspace: need copy instruction here then translate it */ | |
378 | pagefault_disable(); | |
379 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
380 | if (ret) { | |
381 | pagefault_enable(); | |
382 | return 0; | |
383 | } | |
384 | pagefault_enable(); | |
385 | ||
386 | target = branch_target(&instr); | |
387 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
388 | return target; | |
389 | ||
390 | /* Translate relative branch target from kernel to user address */ | |
391 | return target - (unsigned long)&instr + addr; | |
392 | } | |
d52f2dc4 | 393 | |
d52f2dc4 | 394 | /* Processing BHRB entries */ |
506e70d1 | 395 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
396 | { |
397 | u64 val; | |
398 | u64 addr; | |
506e70d1 | 399 | int r_index, u_index, pred; |
d52f2dc4 MN |
400 | |
401 | r_index = 0; | |
402 | u_index = 0; | |
403 | while (r_index < ppmu->bhrb_nr) { | |
404 | /* Assembly read function */ | |
506e70d1 MN |
405 | val = read_bhrb(r_index++); |
406 | if (!val) | |
407 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 408 | break; |
506e70d1 | 409 | else { |
d52f2dc4 MN |
410 | addr = val & BHRB_EA; |
411 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 412 | |
506e70d1 MN |
413 | if (!addr) |
414 | /* invalid entry */ | |
d52f2dc4 | 415 | continue; |
d52f2dc4 | 416 | |
506e70d1 MN |
417 | /* Branches are read most recent first (ie. mfbhrb 0 is |
418 | * the most recent branch). | |
419 | * There are two types of valid entries: | |
420 | * 1) a target entry which is the to address of a | |
421 | * computed goto like a blr,bctr,btar. The next | |
422 | * entry read from the bhrb will be branch | |
423 | * corresponding to this target (ie. the actual | |
424 | * blr/bctr/btar instruction). | |
425 | * 2) a from address which is an actual branch. If a | |
426 | * target entry proceeds this, then this is the | |
427 | * matching branch for that target. If this is not | |
428 | * following a target entry, then this is a branch | |
429 | * where the target is given as an immediate field | |
430 | * in the instruction (ie. an i or b form branch). | |
431 | * In this case we need to read the instruction from | |
432 | * memory to determine the target/to address. | |
433 | */ | |
d52f2dc4 | 434 | |
d52f2dc4 | 435 | if (val & BHRB_TARGET) { |
506e70d1 MN |
436 | /* Target branches use two entries |
437 | * (ie. computed gotos/XL form) | |
438 | */ | |
439 | cpuhw->bhrb_entries[u_index].to = addr; | |
440 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
441 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 442 | |
506e70d1 MN |
443 | /* Get from address in next entry */ |
444 | val = read_bhrb(r_index++); | |
445 | addr = val & BHRB_EA; | |
446 | if (val & BHRB_TARGET) { | |
447 | /* Shouldn't have two targets in a | |
448 | row.. Reset index and try again */ | |
449 | r_index--; | |
450 | addr = 0; | |
451 | } | |
452 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 453 | } else { |
506e70d1 MN |
454 | /* Branches to immediate field |
455 | (ie I or B form) */ | |
d52f2dc4 | 456 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
457 | cpuhw->bhrb_entries[u_index].to = |
458 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
459 | cpuhw->bhrb_entries[u_index].mispred = pred; |
460 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 461 | } |
506e70d1 MN |
462 | u_index++; |
463 | ||
d52f2dc4 MN |
464 | } |
465 | } | |
466 | cpuhw->bhrb_stack.nr = u_index; | |
467 | return; | |
468 | } | |
469 | ||
98fb1807 PM |
470 | #endif /* CONFIG_PPC64 */ |
471 | ||
cdd6c482 | 472 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 473 | |
cdd6c482 | 474 | void perf_event_print_debug(void) |
4574910e PM |
475 | { |
476 | } | |
477 | ||
4574910e | 478 | /* |
57c0c15b | 479 | * Read one performance monitor counter (PMC). |
4574910e PM |
480 | */ |
481 | static unsigned long read_pmc(int idx) | |
482 | { | |
483 | unsigned long val; | |
484 | ||
485 | switch (idx) { | |
486 | case 1: | |
487 | val = mfspr(SPRN_PMC1); | |
488 | break; | |
489 | case 2: | |
490 | val = mfspr(SPRN_PMC2); | |
491 | break; | |
492 | case 3: | |
493 | val = mfspr(SPRN_PMC3); | |
494 | break; | |
495 | case 4: | |
496 | val = mfspr(SPRN_PMC4); | |
497 | break; | |
498 | case 5: | |
499 | val = mfspr(SPRN_PMC5); | |
500 | break; | |
501 | case 6: | |
502 | val = mfspr(SPRN_PMC6); | |
503 | break; | |
98fb1807 | 504 | #ifdef CONFIG_PPC64 |
4574910e PM |
505 | case 7: |
506 | val = mfspr(SPRN_PMC7); | |
507 | break; | |
508 | case 8: | |
509 | val = mfspr(SPRN_PMC8); | |
510 | break; | |
98fb1807 | 511 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
512 | default: |
513 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
514 | val = 0; | |
515 | } | |
516 | return val; | |
517 | } | |
518 | ||
519 | /* | |
520 | * Write one PMC. | |
521 | */ | |
522 | static void write_pmc(int idx, unsigned long val) | |
523 | { | |
524 | switch (idx) { | |
525 | case 1: | |
526 | mtspr(SPRN_PMC1, val); | |
527 | break; | |
528 | case 2: | |
529 | mtspr(SPRN_PMC2, val); | |
530 | break; | |
531 | case 3: | |
532 | mtspr(SPRN_PMC3, val); | |
533 | break; | |
534 | case 4: | |
535 | mtspr(SPRN_PMC4, val); | |
536 | break; | |
537 | case 5: | |
538 | mtspr(SPRN_PMC5, val); | |
539 | break; | |
540 | case 6: | |
541 | mtspr(SPRN_PMC6, val); | |
542 | break; | |
98fb1807 | 543 | #ifdef CONFIG_PPC64 |
4574910e PM |
544 | case 7: |
545 | mtspr(SPRN_PMC7, val); | |
546 | break; | |
547 | case 8: | |
548 | mtspr(SPRN_PMC8, val); | |
549 | break; | |
98fb1807 | 550 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
551 | default: |
552 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
553 | } | |
554 | } | |
555 | ||
556 | /* | |
557 | * Check if a set of events can all go on the PMU at once. | |
558 | * If they can't, this will look at alternative codes for the events | |
559 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 560 | * The feasible set is returned in event_id[]. |
4574910e | 561 | */ |
cdd6c482 IM |
562 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
563 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 564 | int n_ev) |
4574910e | 565 | { |
448d64f8 | 566 | unsigned long mask, value, nv; |
cdd6c482 IM |
567 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
568 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 569 | int i, j; |
448d64f8 PM |
570 | unsigned long addf = ppmu->add_fields; |
571 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 572 | |
a8f90e90 | 573 | if (n_ev > ppmu->n_counter) |
4574910e PM |
574 | return -1; |
575 | ||
576 | /* First see if the events will go on as-is */ | |
577 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 578 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
579 | && !ppmu->limited_pmc_event(event_id[i])) { |
580 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 581 | cpuhw->alternatives[i]); |
cdd6c482 | 582 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 583 | } |
cdd6c482 | 584 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 585 | &cpuhw->avalues[i][0])) |
4574910e | 586 | return -1; |
4574910e PM |
587 | } |
588 | value = mask = 0; | |
589 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
590 | nv = (value | cpuhw->avalues[i][0]) + |
591 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 592 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
593 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
594 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
595 | break; |
596 | value = nv; | |
e51ee31e | 597 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
598 | } |
599 | if (i == n_ev) | |
600 | return 0; /* all OK */ | |
601 | ||
602 | /* doesn't work, gather alternatives... */ | |
603 | if (!ppmu->get_alternatives) | |
604 | return -1; | |
605 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 606 | choice[i] = 0; |
cdd6c482 | 607 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 608 | cpuhw->alternatives[i]); |
4574910e | 609 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
610 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
611 | &cpuhw->amasks[i][j], | |
612 | &cpuhw->avalues[i][j]); | |
4574910e PM |
613 | } |
614 | ||
615 | /* enumerate all possibilities and see if any will work */ | |
616 | i = 0; | |
617 | j = -1; | |
618 | value = mask = nv = 0; | |
619 | while (i < n_ev) { | |
620 | if (j >= 0) { | |
621 | /* we're backtracking, restore context */ | |
622 | value = svalues[i]; | |
623 | mask = smasks[i]; | |
624 | j = choice[i]; | |
625 | } | |
626 | /* | |
cdd6c482 | 627 | * See if any alternative k for event_id i, |
4574910e PM |
628 | * where k > j, will satisfy the constraints. |
629 | */ | |
630 | while (++j < n_alt[i]) { | |
e51ee31e PM |
631 | nv = (value | cpuhw->avalues[i][j]) + |
632 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 633 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
634 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
635 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
636 | break; |
637 | } | |
638 | if (j >= n_alt[i]) { | |
639 | /* | |
640 | * No feasible alternative, backtrack | |
cdd6c482 | 641 | * to event_id i-1 and continue enumerating its |
4574910e PM |
642 | * alternatives from where we got up to. |
643 | */ | |
644 | if (--i < 0) | |
645 | return -1; | |
646 | } else { | |
647 | /* | |
cdd6c482 IM |
648 | * Found a feasible alternative for event_id i, |
649 | * remember where we got up to with this event_id, | |
650 | * go on to the next event_id, and start with | |
4574910e PM |
651 | * the first alternative for it. |
652 | */ | |
653 | choice[i] = j; | |
654 | svalues[i] = value; | |
655 | smasks[i] = mask; | |
656 | value = nv; | |
e51ee31e | 657 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
658 | ++i; |
659 | j = -1; | |
660 | } | |
661 | } | |
662 | ||
663 | /* OK, we have a feasible combination, tell the caller the solution */ | |
664 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 665 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
666 | return 0; |
667 | } | |
668 | ||
0475f9ea | 669 | /* |
cdd6c482 | 670 | * Check if newly-added events have consistent settings for |
0475f9ea | 671 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 672 | * added events. |
0475f9ea | 673 | */ |
cdd6c482 | 674 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 675 | int n_prev, int n_new) |
0475f9ea | 676 | { |
ab7ef2e5 PM |
677 | int eu = 0, ek = 0, eh = 0; |
678 | int i, n, first; | |
cdd6c482 | 679 | struct perf_event *event; |
0475f9ea PM |
680 | |
681 | n = n_prev + n_new; | |
682 | if (n <= 1) | |
683 | return 0; | |
684 | ||
ab7ef2e5 PM |
685 | first = 1; |
686 | for (i = 0; i < n; ++i) { | |
687 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
688 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
689 | continue; | |
690 | } | |
cdd6c482 | 691 | event = ctrs[i]; |
ab7ef2e5 | 692 | if (first) { |
cdd6c482 IM |
693 | eu = event->attr.exclude_user; |
694 | ek = event->attr.exclude_kernel; | |
695 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 696 | first = 0; |
cdd6c482 IM |
697 | } else if (event->attr.exclude_user != eu || |
698 | event->attr.exclude_kernel != ek || | |
699 | event->attr.exclude_hv != eh) { | |
0475f9ea | 700 | return -EAGAIN; |
ab7ef2e5 | 701 | } |
0475f9ea | 702 | } |
ab7ef2e5 PM |
703 | |
704 | if (eu || ek || eh) | |
705 | for (i = 0; i < n; ++i) | |
706 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
707 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
708 | ||
0475f9ea PM |
709 | return 0; |
710 | } | |
711 | ||
86c74ab3 EM |
712 | static u64 check_and_compute_delta(u64 prev, u64 val) |
713 | { | |
714 | u64 delta = (val - prev) & 0xfffffffful; | |
715 | ||
716 | /* | |
717 | * POWER7 can roll back counter values, if the new value is smaller | |
718 | * than the previous value it will cause the delta and the counter to | |
719 | * have bogus values unless we rolled a counter over. If a coutner is | |
720 | * rolled back, it will be smaller, but within 256, which is the maximum | |
721 | * number of events to rollback at once. If we dectect a rollback | |
722 | * return 0. This can lead to a small lack of precision in the | |
723 | * counters. | |
724 | */ | |
725 | if (prev > val && (prev - val) < 256) | |
726 | delta = 0; | |
727 | ||
728 | return delta; | |
729 | } | |
730 | ||
cdd6c482 | 731 | static void power_pmu_read(struct perf_event *event) |
4574910e | 732 | { |
98fb1807 | 733 | s64 val, delta, prev; |
4574910e | 734 | |
a4eaf7f1 PZ |
735 | if (event->hw.state & PERF_HES_STOPPED) |
736 | return; | |
737 | ||
cdd6c482 | 738 | if (!event->hw.idx) |
4574910e PM |
739 | return; |
740 | /* | |
741 | * Performance monitor interrupts come even when interrupts | |
742 | * are soft-disabled, as long as interrupts are hard-enabled. | |
743 | * Therefore we treat them like NMIs. | |
744 | */ | |
745 | do { | |
e7850595 | 746 | prev = local64_read(&event->hw.prev_count); |
4574910e | 747 | barrier(); |
cdd6c482 | 748 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
749 | delta = check_and_compute_delta(prev, val); |
750 | if (!delta) | |
751 | return; | |
e7850595 | 752 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 753 | |
e7850595 PZ |
754 | local64_add(delta, &event->count); |
755 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
756 | } |
757 | ||
ab7ef2e5 PM |
758 | /* |
759 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
760 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 761 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
762 | */ |
763 | static int is_limited_pmc(int pmcnum) | |
764 | { | |
0bbd0d4b PM |
765 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
766 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
767 | } |
768 | ||
a8f90e90 | 769 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
770 | unsigned long pmc5, unsigned long pmc6) |
771 | { | |
cdd6c482 | 772 | struct perf_event *event; |
ab7ef2e5 PM |
773 | u64 val, prev, delta; |
774 | int i; | |
775 | ||
776 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 777 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 778 | if (!event->hw.idx) |
ab7ef2e5 | 779 | continue; |
cdd6c482 | 780 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 781 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 782 | event->hw.idx = 0; |
86c74ab3 EM |
783 | delta = check_and_compute_delta(prev, val); |
784 | if (delta) | |
785 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
786 | } |
787 | } | |
788 | ||
a8f90e90 | 789 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
790 | unsigned long pmc5, unsigned long pmc6) |
791 | { | |
cdd6c482 | 792 | struct perf_event *event; |
86c74ab3 | 793 | u64 val, prev; |
ab7ef2e5 PM |
794 | int i; |
795 | ||
796 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 797 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
798 | event->hw.idx = cpuhw->limited_hwidx[i]; |
799 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
800 | prev = local64_read(&event->hw.prev_count); |
801 | if (check_and_compute_delta(prev, val)) | |
802 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 803 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
804 | } |
805 | } | |
806 | ||
807 | /* | |
cdd6c482 | 808 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 809 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
810 | * other events. We try to keep the values from the limited |
811 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 812 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
813 | * the limited events as small and consistent as possible. |
814 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
815 | * both, and always in the same order, to minimize variability, |
816 | * and do it inside the same asm that writes MMCR0. | |
817 | */ | |
cdd6c482 | 818 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
819 | { |
820 | unsigned long pmc5, pmc6; | |
821 | ||
822 | if (!cpuhw->n_limited) { | |
823 | mtspr(SPRN_MMCR0, mmcr0); | |
824 | return; | |
825 | } | |
826 | ||
827 | /* | |
828 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
829 | * To ensure we don't get a performance monitor interrupt |
830 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 831 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 832 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
833 | */ |
834 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
835 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
836 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
837 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
838 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
839 | ||
840 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 841 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 842 | else |
a8f90e90 | 843 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
844 | |
845 | /* | |
cdd6c482 | 846 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
847 | * enable bits, if necessary. |
848 | */ | |
849 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
850 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
851 | } |
852 | ||
4574910e | 853 | /* |
cdd6c482 IM |
854 | * Disable all events to prevent PMU interrupts and to allow |
855 | * events to be added or removed. | |
4574910e | 856 | */ |
a4eaf7f1 | 857 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 858 | { |
cdd6c482 | 859 | struct cpu_hw_events *cpuhw; |
4574910e PM |
860 | unsigned long flags; |
861 | ||
f36a1a13 PM |
862 | if (!ppmu) |
863 | return; | |
4574910e | 864 | local_irq_save(flags); |
cdd6c482 | 865 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 866 | |
448d64f8 | 867 | if (!cpuhw->disabled) { |
4574910e PM |
868 | cpuhw->disabled = 1; |
869 | cpuhw->n_added = 0; | |
870 | ||
01d0287f PM |
871 | /* |
872 | * Check if we ever enabled the PMU on this cpu. | |
873 | */ | |
874 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 875 | ppc_enable_pmcs(); |
01d0287f PM |
876 | cpuhw->pmcs_enabled = 1; |
877 | } | |
878 | ||
f708223d PM |
879 | /* |
880 | * Disable instruction sampling if it was enabled | |
881 | */ | |
882 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
883 | mtspr(SPRN_MMCRA, | |
884 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
885 | mb(); | |
886 | } | |
887 | ||
4574910e | 888 | /* |
57c0c15b | 889 | * Set the 'freeze counters' bit. |
4574910e | 890 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 891 | * executed and the PMU has frozen the events |
4574910e PM |
892 | * before we return. |
893 | */ | |
ab7ef2e5 | 894 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
895 | mb(); |
896 | } | |
897 | local_irq_restore(flags); | |
4574910e PM |
898 | } |
899 | ||
900 | /* | |
cdd6c482 IM |
901 | * Re-enable all events if disable == 0. |
902 | * If we were previously disabled and events were added, then | |
4574910e PM |
903 | * put the new config on the PMU. |
904 | */ | |
a4eaf7f1 | 905 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 906 | { |
cdd6c482 IM |
907 | struct perf_event *event; |
908 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
909 | unsigned long flags; |
910 | long i; | |
911 | unsigned long val; | |
912 | s64 left; | |
cdd6c482 | 913 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
914 | int n_lim; |
915 | int idx; | |
4574910e | 916 | |
f36a1a13 PM |
917 | if (!ppmu) |
918 | return; | |
4574910e | 919 | local_irq_save(flags); |
cdd6c482 | 920 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
921 | if (!cpuhw->disabled) { |
922 | local_irq_restore(flags); | |
923 | return; | |
924 | } | |
4574910e PM |
925 | cpuhw->disabled = 0; |
926 | ||
927 | /* | |
cdd6c482 | 928 | * If we didn't change anything, or only removed events, |
4574910e PM |
929 | * no need to recalculate MMCR* settings and reset the PMCs. |
930 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 931 | * (possibly updated for removal of events). |
4574910e PM |
932 | */ |
933 | if (!cpuhw->n_added) { | |
f708223d | 934 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 935 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 936 | if (cpuhw->n_events == 0) |
a6dbf93a | 937 | ppc_set_pmu_inuse(0); |
f708223d | 938 | goto out_enable; |
4574910e PM |
939 | } |
940 | ||
941 | /* | |
cdd6c482 | 942 | * Compute MMCR* values for the new set of events |
4574910e | 943 | */ |
cdd6c482 | 944 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
945 | cpuhw->mmcr)) { |
946 | /* shouldn't ever get here */ | |
947 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
948 | goto out; | |
949 | } | |
950 | ||
0475f9ea PM |
951 | /* |
952 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
953 | * attr.exclude_* bits for the first event. |
954 | * We have already checked that all events have the | |
955 | * same values for these bits as the first event. | |
0475f9ea | 956 | */ |
cdd6c482 IM |
957 | event = cpuhw->event[0]; |
958 | if (event->attr.exclude_user) | |
0475f9ea | 959 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
960 | if (event->attr.exclude_kernel) |
961 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
962 | if (event->attr.exclude_hv) | |
0475f9ea PM |
963 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
964 | ||
4574910e PM |
965 | /* |
966 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
967 | * bit set and set the hardware events to their initial values. |
968 | * Then unfreeze the events. | |
4574910e | 969 | */ |
a6dbf93a | 970 | ppc_set_pmu_inuse(1); |
f708223d | 971 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
972 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
973 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
974 | | MMCR0_FC); | |
975 | ||
976 | /* | |
cdd6c482 | 977 | * Read off any pre-existing events that need to move |
4574910e PM |
978 | * to another PMC. |
979 | */ | |
cdd6c482 IM |
980 | for (i = 0; i < cpuhw->n_events; ++i) { |
981 | event = cpuhw->event[i]; | |
982 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
983 | power_pmu_read(event); | |
984 | write_pmc(event->hw.idx, 0); | |
985 | event->hw.idx = 0; | |
4574910e PM |
986 | } |
987 | } | |
988 | ||
989 | /* | |
cdd6c482 | 990 | * Initialize the PMCs for all the new and moved events. |
4574910e | 991 | */ |
ab7ef2e5 | 992 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
993 | for (i = 0; i < cpuhw->n_events; ++i) { |
994 | event = cpuhw->event[i]; | |
995 | if (event->hw.idx) | |
4574910e | 996 | continue; |
ab7ef2e5 PM |
997 | idx = hwc_index[i] + 1; |
998 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 999 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1000 | cpuhw->limited_hwidx[n_lim] = idx; |
1001 | ++n_lim; | |
1002 | continue; | |
1003 | } | |
4574910e | 1004 | val = 0; |
cdd6c482 | 1005 | if (event->hw.sample_period) { |
e7850595 | 1006 | left = local64_read(&event->hw.period_left); |
4574910e PM |
1007 | if (left < 0x80000000L) |
1008 | val = 0x80000000L - left; | |
1009 | } | |
e7850595 | 1010 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 1011 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1012 | if (event->hw.state & PERF_HES_STOPPED) |
1013 | val = 0; | |
ab7ef2e5 | 1014 | write_pmc(idx, val); |
cdd6c482 | 1015 | perf_event_update_userpage(event); |
4574910e | 1016 | } |
ab7ef2e5 | 1017 | cpuhw->n_limited = n_lim; |
4574910e | 1018 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1019 | |
1020 | out_enable: | |
1021 | mb(); | |
ab7ef2e5 | 1022 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1023 | |
f708223d PM |
1024 | /* |
1025 | * Enable instruction sampling if necessary | |
1026 | */ | |
1027 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1028 | mb(); | |
1029 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1030 | } | |
1031 | ||
4574910e | 1032 | out: |
3925f46b AK |
1033 | if (cpuhw->bhrb_users) |
1034 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1035 | ||
4574910e PM |
1036 | local_irq_restore(flags); |
1037 | } | |
1038 | ||
cdd6c482 IM |
1039 | static int collect_events(struct perf_event *group, int max_count, |
1040 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1041 | unsigned int *flags) |
4574910e PM |
1042 | { |
1043 | int n = 0; | |
cdd6c482 | 1044 | struct perf_event *event; |
4574910e | 1045 | |
cdd6c482 | 1046 | if (!is_software_event(group)) { |
4574910e PM |
1047 | if (n >= max_count) |
1048 | return -1; | |
1049 | ctrs[n] = group; | |
cdd6c482 | 1050 | flags[n] = group->hw.event_base; |
4574910e PM |
1051 | events[n++] = group->hw.config; |
1052 | } | |
a8f90e90 | 1053 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1054 | if (!is_software_event(event) && |
1055 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1056 | if (n >= max_count) |
1057 | return -1; | |
cdd6c482 IM |
1058 | ctrs[n] = event; |
1059 | flags[n] = event->hw.event_base; | |
1060 | events[n++] = event->hw.config; | |
4574910e PM |
1061 | } |
1062 | } | |
1063 | return n; | |
1064 | } | |
1065 | ||
4574910e | 1066 | /* |
cdd6c482 IM |
1067 | * Add a event to the PMU. |
1068 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1069 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1070 | * actual work of reconfiguring the PMU. |
1071 | */ | |
a4eaf7f1 | 1072 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1073 | { |
cdd6c482 | 1074 | struct cpu_hw_events *cpuhw; |
4574910e | 1075 | unsigned long flags; |
4574910e PM |
1076 | int n0; |
1077 | int ret = -EAGAIN; | |
1078 | ||
1079 | local_irq_save(flags); | |
33696fc0 | 1080 | perf_pmu_disable(event->pmu); |
4574910e PM |
1081 | |
1082 | /* | |
cdd6c482 | 1083 | * Add the event to the list (if there is room) |
4574910e PM |
1084 | * and check whether the total set is still feasible. |
1085 | */ | |
cdd6c482 IM |
1086 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1087 | n0 = cpuhw->n_events; | |
a8f90e90 | 1088 | if (n0 >= ppmu->n_counter) |
4574910e | 1089 | goto out; |
cdd6c482 IM |
1090 | cpuhw->event[n0] = event; |
1091 | cpuhw->events[n0] = event->hw.config; | |
1092 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1093 | |
f53d168c | 1094 | /* |
1095 | * This event may have been disabled/stopped in record_and_restart() | |
1096 | * because we exceeded the ->event_limit. If re-starting the event, | |
1097 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1098 | * notification is re-enabled. | |
1099 | */ | |
a4eaf7f1 PZ |
1100 | if (!(ef_flags & PERF_EF_START)) |
1101 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1102 | else |
1103 | event->hw.state = 0; | |
a4eaf7f1 | 1104 | |
8e6d5573 LM |
1105 | /* |
1106 | * If group events scheduling transaction was started, | |
25985edc | 1107 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1108 | * at commit time(->commit_txn) as a whole |
1109 | */ | |
8d2cacbb | 1110 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1111 | goto nocheck; |
1112 | ||
cdd6c482 | 1113 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1114 | goto out; |
e51ee31e | 1115 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1116 | goto out; |
cdd6c482 | 1117 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1118 | |
1119 | nocheck: | |
cdd6c482 | 1120 | ++cpuhw->n_events; |
4574910e PM |
1121 | ++cpuhw->n_added; |
1122 | ||
1123 | ret = 0; | |
1124 | out: | |
3925f46b AK |
1125 | if (has_branch_stack(event)) |
1126 | power_pmu_bhrb_enable(event); | |
1127 | ||
33696fc0 | 1128 | perf_pmu_enable(event->pmu); |
4574910e PM |
1129 | local_irq_restore(flags); |
1130 | return ret; | |
1131 | } | |
1132 | ||
1133 | /* | |
cdd6c482 | 1134 | * Remove a event from the PMU. |
4574910e | 1135 | */ |
a4eaf7f1 | 1136 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1137 | { |
cdd6c482 | 1138 | struct cpu_hw_events *cpuhw; |
4574910e | 1139 | long i; |
4574910e PM |
1140 | unsigned long flags; |
1141 | ||
1142 | local_irq_save(flags); | |
33696fc0 | 1143 | perf_pmu_disable(event->pmu); |
4574910e | 1144 | |
cdd6c482 IM |
1145 | power_pmu_read(event); |
1146 | ||
1147 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1148 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1149 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1150 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1151 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1152 | cpuhw->events[i-1] = cpuhw->events[i]; |
1153 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1154 | } | |
cdd6c482 IM |
1155 | --cpuhw->n_events; |
1156 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1157 | if (event->hw.idx) { | |
1158 | write_pmc(event->hw.idx, 0); | |
1159 | event->hw.idx = 0; | |
ab7ef2e5 | 1160 | } |
cdd6c482 | 1161 | perf_event_update_userpage(event); |
4574910e PM |
1162 | break; |
1163 | } | |
1164 | } | |
ab7ef2e5 | 1165 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1166 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1167 | break; |
1168 | if (i < cpuhw->n_limited) { | |
1169 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1170 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1171 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1172 | } | |
1173 | --cpuhw->n_limited; | |
1174 | } | |
cdd6c482 IM |
1175 | if (cpuhw->n_events == 0) { |
1176 | /* disable exceptions if no events are running */ | |
4574910e PM |
1177 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1178 | } | |
1179 | ||
3925f46b AK |
1180 | if (has_branch_stack(event)) |
1181 | power_pmu_bhrb_disable(event); | |
1182 | ||
33696fc0 | 1183 | perf_pmu_enable(event->pmu); |
4574910e PM |
1184 | local_irq_restore(flags); |
1185 | } | |
1186 | ||
8a7b8cb9 | 1187 | /* |
a4eaf7f1 PZ |
1188 | * POWER-PMU does not support disabling individual counters, hence |
1189 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1190 | */ |
a4eaf7f1 PZ |
1191 | |
1192 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1193 | { |
8a7b8cb9 | 1194 | unsigned long flags; |
a4eaf7f1 | 1195 | s64 left; |
9a45a940 | 1196 | unsigned long val; |
8a7b8cb9 | 1197 | |
cdd6c482 | 1198 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1199 | return; |
a4eaf7f1 PZ |
1200 | |
1201 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1202 | return; | |
1203 | ||
1204 | if (ef_flags & PERF_EF_RELOAD) | |
1205 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1206 | ||
1207 | local_irq_save(flags); | |
1208 | perf_pmu_disable(event->pmu); | |
1209 | ||
1210 | event->hw.state = 0; | |
1211 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1212 | |
1213 | val = 0; | |
1214 | if (left < 0x80000000L) | |
1215 | val = 0x80000000L - left; | |
1216 | ||
1217 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1218 | |
1219 | perf_event_update_userpage(event); | |
1220 | perf_pmu_enable(event->pmu); | |
1221 | local_irq_restore(flags); | |
1222 | } | |
1223 | ||
1224 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1225 | { | |
1226 | unsigned long flags; | |
1227 | ||
1228 | if (!event->hw.idx || !event->hw.sample_period) | |
1229 | return; | |
1230 | ||
1231 | if (event->hw.state & PERF_HES_STOPPED) | |
1232 | return; | |
1233 | ||
8a7b8cb9 | 1234 | local_irq_save(flags); |
33696fc0 | 1235 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1236 | |
cdd6c482 | 1237 | power_pmu_read(event); |
a4eaf7f1 PZ |
1238 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1239 | write_pmc(event->hw.idx, 0); | |
1240 | ||
cdd6c482 | 1241 | perf_event_update_userpage(event); |
33696fc0 | 1242 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1243 | local_irq_restore(flags); |
1244 | } | |
1245 | ||
8e6d5573 LM |
1246 | /* |
1247 | * Start group events scheduling transaction | |
1248 | * Set the flag to make pmu::enable() not perform the | |
1249 | * schedulability test, it will be performed at commit time | |
1250 | */ | |
51b0fe39 | 1251 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1252 | { |
1253 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1254 | ||
33696fc0 | 1255 | perf_pmu_disable(pmu); |
8d2cacbb | 1256 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1257 | cpuhw->n_txn_start = cpuhw->n_events; |
1258 | } | |
1259 | ||
1260 | /* | |
1261 | * Stop group events scheduling transaction | |
1262 | * Clear the flag and pmu::enable() will perform the | |
1263 | * schedulability test. | |
1264 | */ | |
51b0fe39 | 1265 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1266 | { |
1267 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1268 | ||
8d2cacbb | 1269 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1270 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1271 | } |
1272 | ||
1273 | /* | |
1274 | * Commit group events scheduling transaction | |
1275 | * Perform the group schedulability test as a whole | |
1276 | * Return 0 if success | |
1277 | */ | |
51b0fe39 | 1278 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1279 | { |
1280 | struct cpu_hw_events *cpuhw; | |
1281 | long i, n; | |
1282 | ||
1283 | if (!ppmu) | |
1284 | return -EAGAIN; | |
1285 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1286 | n = cpuhw->n_events; | |
1287 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1288 | return -EAGAIN; | |
1289 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1290 | if (i < 0) | |
1291 | return -EAGAIN; | |
1292 | ||
1293 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1294 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1295 | ||
8d2cacbb | 1296 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1297 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1298 | return 0; |
1299 | } | |
1300 | ||
ab7ef2e5 | 1301 | /* |
cdd6c482 | 1302 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1303 | * or 0 if not. |
cdd6c482 | 1304 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1305 | * that a limited PMC can count, doesn't require interrupts, and |
1306 | * doesn't exclude any processor mode. | |
1307 | */ | |
cdd6c482 | 1308 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1309 | unsigned int flags) |
1310 | { | |
1311 | int n; | |
ef923214 | 1312 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1313 | |
cdd6c482 IM |
1314 | if (event->attr.exclude_user |
1315 | || event->attr.exclude_kernel | |
1316 | || event->attr.exclude_hv | |
1317 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1318 | return 0; |
1319 | ||
1320 | if (ppmu->limited_pmc_event(ev)) | |
1321 | return 1; | |
1322 | ||
1323 | /* | |
cdd6c482 | 1324 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1325 | * see if any alternative code goes on a limited PMC. |
1326 | */ | |
1327 | if (!ppmu->get_alternatives) | |
1328 | return 0; | |
1329 | ||
1330 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1331 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1332 | |
ef923214 | 1333 | return n > 0; |
ab7ef2e5 PM |
1334 | } |
1335 | ||
1336 | /* | |
cdd6c482 IM |
1337 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1338 | * and return the event_id code, or 0 if there is no such alternative. | |
1339 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1340 | */ |
ef923214 | 1341 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1342 | { |
ef923214 | 1343 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1344 | int n; |
1345 | ||
1346 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1347 | n = ppmu->get_alternatives(ev, flags, alt); | |
1348 | if (!n) | |
1349 | return 0; | |
1350 | return alt[0]; | |
1351 | } | |
1352 | ||
cdd6c482 IM |
1353 | /* Number of perf_events counting hardware events */ |
1354 | static atomic_t num_events; | |
7595d63b PM |
1355 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1356 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1357 | ||
1358 | /* | |
cdd6c482 | 1359 | * Release the PMU if this is the last perf_event. |
7595d63b | 1360 | */ |
cdd6c482 | 1361 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1362 | { |
cdd6c482 | 1363 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1364 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1365 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1366 | release_pmc_hardware(); |
1367 | mutex_unlock(&pmc_reserve_mutex); | |
1368 | } | |
1369 | } | |
1370 | ||
106b506c | 1371 | /* |
cdd6c482 | 1372 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1373 | */ |
1374 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1375 | { | |
1376 | unsigned long type, op, result; | |
1377 | int ev; | |
1378 | ||
1379 | if (!ppmu->cache_events) | |
1380 | return -EINVAL; | |
1381 | ||
1382 | /* unpack config */ | |
1383 | type = config & 0xff; | |
1384 | op = (config >> 8) & 0xff; | |
1385 | result = (config >> 16) & 0xff; | |
1386 | ||
1387 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1388 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1389 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1390 | return -EINVAL; | |
1391 | ||
1392 | ev = (*ppmu->cache_events)[type][op][result]; | |
1393 | if (ev == 0) | |
1394 | return -EOPNOTSUPP; | |
1395 | if (ev == -1) | |
1396 | return -EINVAL; | |
1397 | *eventp = ev; | |
1398 | return 0; | |
1399 | } | |
1400 | ||
b0a873eb | 1401 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1402 | { |
ef923214 PM |
1403 | u64 ev; |
1404 | unsigned long flags; | |
cdd6c482 IM |
1405 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1406 | u64 events[MAX_HWEVENTS]; | |
1407 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1408 | int n; |
7595d63b | 1409 | int err; |
cdd6c482 | 1410 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1411 | |
1412 | if (!ppmu) | |
b0a873eb PZ |
1413 | return -ENOENT; |
1414 | ||
3925f46b AK |
1415 | if (has_branch_stack(event)) { |
1416 | /* PMU has BHRB enabled */ | |
1417 | if (!(ppmu->flags & PPMU_BHRB)) | |
1418 | return -EOPNOTSUPP; | |
1419 | } | |
2481c5fa | 1420 | |
cdd6c482 | 1421 | switch (event->attr.type) { |
106b506c | 1422 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1423 | ev = event->attr.config; |
9aaa131a | 1424 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1425 | return -EOPNOTSUPP; |
4574910e | 1426 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1427 | break; |
1428 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1429 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1430 | if (err) |
b0a873eb | 1431 | return err; |
106b506c PM |
1432 | break; |
1433 | case PERF_TYPE_RAW: | |
cdd6c482 | 1434 | ev = event->attr.config; |
106b506c | 1435 | break; |
90c8f954 | 1436 | default: |
b0a873eb | 1437 | return -ENOENT; |
4574910e | 1438 | } |
b0a873eb | 1439 | |
cdd6c482 IM |
1440 | event->hw.config_base = ev; |
1441 | event->hw.idx = 0; | |
4574910e | 1442 | |
0475f9ea PM |
1443 | /* |
1444 | * If we are not running on a hypervisor, force the | |
1445 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1446 | * the user set it to. |
0475f9ea PM |
1447 | */ |
1448 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1449 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1450 | |
1451 | /* | |
cdd6c482 | 1452 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1453 | * PM_RUN_* events interchangeably with their non RUN_* |
1454 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1455 | * XXX we should check if the task is an idle task. | |
1456 | */ | |
1457 | flags = 0; | |
57fa7214 | 1458 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1459 | flags |= PPMU_ONLY_COUNT_RUN; |
1460 | ||
1461 | /* | |
cdd6c482 IM |
1462 | * If this machine has limited events, check whether this |
1463 | * event_id could go on a limited event. | |
ab7ef2e5 | 1464 | */ |
0bbd0d4b | 1465 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1466 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1467 | flags |= PPMU_LIMITED_PMC_OK; |
1468 | } else if (ppmu->limited_pmc_event(ev)) { | |
1469 | /* | |
cdd6c482 | 1470 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1471 | * but we can't use a limited PMC; see if any |
1472 | * alternative goes on a normal PMC. | |
1473 | */ | |
1474 | ev = normal_pmc_alternative(ev, flags); | |
1475 | if (!ev) | |
b0a873eb | 1476 | return -EINVAL; |
ab7ef2e5 PM |
1477 | } |
1478 | } | |
1479 | ||
4574910e PM |
1480 | /* |
1481 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1482 | * other hardware events in the group. We assume the event |
4574910e PM |
1483 | * hasn't been linked into its leader's sibling list at this point. |
1484 | */ | |
1485 | n = 0; | |
cdd6c482 | 1486 | if (event->group_leader != event) { |
a8f90e90 | 1487 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1488 | ctrs, events, cflags); |
4574910e | 1489 | if (n < 0) |
b0a873eb | 1490 | return -EINVAL; |
4574910e | 1491 | } |
0475f9ea | 1492 | events[n] = ev; |
cdd6c482 | 1493 | ctrs[n] = event; |
ab7ef2e5 PM |
1494 | cflags[n] = flags; |
1495 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1496 | return -EINVAL; |
e51ee31e | 1497 | |
cdd6c482 | 1498 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1499 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1500 | |
1501 | if (has_branch_stack(event)) { | |
1502 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1503 | event->attr.branch_sample_type); | |
1504 | ||
1505 | if(cpuhw->bhrb_filter == -1) | |
1506 | return -EOPNOTSUPP; | |
1507 | } | |
1508 | ||
cdd6c482 | 1509 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1510 | if (err) |
b0a873eb | 1511 | return -EINVAL; |
4574910e | 1512 | |
cdd6c482 IM |
1513 | event->hw.config = events[n]; |
1514 | event->hw.event_base = cflags[n]; | |
1515 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1516 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1517 | |
1518 | /* | |
1519 | * See if we need to reserve the PMU. | |
cdd6c482 | 1520 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1521 | * mutex to ensure that we don't race with another task doing |
1522 | * reserve_pmc_hardware or release_pmc_hardware. | |
1523 | */ | |
1524 | err = 0; | |
cdd6c482 | 1525 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1526 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1527 | if (atomic_read(&num_events) == 0 && |
1528 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1529 | err = -EBUSY; |
1530 | else | |
cdd6c482 | 1531 | atomic_inc(&num_events); |
7595d63b PM |
1532 | mutex_unlock(&pmc_reserve_mutex); |
1533 | } | |
cdd6c482 | 1534 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1535 | |
b0a873eb | 1536 | return err; |
4574910e PM |
1537 | } |
1538 | ||
35edc2a5 PZ |
1539 | static int power_pmu_event_idx(struct perf_event *event) |
1540 | { | |
1541 | return event->hw.idx; | |
1542 | } | |
1543 | ||
1c53a270 SB |
1544 | ssize_t power_events_sysfs_show(struct device *dev, |
1545 | struct device_attribute *attr, char *page) | |
1546 | { | |
1547 | struct perf_pmu_events_attr *pmu_attr; | |
1548 | ||
1549 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1550 | ||
1551 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1552 | } | |
1553 | ||
b0a873eb | 1554 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1555 | .pmu_enable = power_pmu_enable, |
1556 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1557 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1558 | .add = power_pmu_add, |
1559 | .del = power_pmu_del, | |
1560 | .start = power_pmu_start, | |
1561 | .stop = power_pmu_stop, | |
b0a873eb | 1562 | .read = power_pmu_read, |
b0a873eb PZ |
1563 | .start_txn = power_pmu_start_txn, |
1564 | .cancel_txn = power_pmu_cancel_txn, | |
1565 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1566 | .event_idx = power_pmu_event_idx, |
3925f46b | 1567 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1568 | }; |
1569 | ||
4574910e | 1570 | /* |
57c0c15b | 1571 | * A counter has overflowed; update its count and record |
4574910e PM |
1572 | * things if requested. Note that interrupts are hard-disabled |
1573 | * here so there is no possibility of being interrupted. | |
1574 | */ | |
cdd6c482 | 1575 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1576 | struct pt_regs *regs) |
4574910e | 1577 | { |
cdd6c482 | 1578 | u64 period = event->hw.sample_period; |
4574910e PM |
1579 | s64 prev, delta, left; |
1580 | int record = 0; | |
1581 | ||
a4eaf7f1 PZ |
1582 | if (event->hw.state & PERF_HES_STOPPED) { |
1583 | write_pmc(event->hw.idx, 0); | |
1584 | return; | |
1585 | } | |
1586 | ||
4574910e | 1587 | /* we don't have to worry about interrupts here */ |
e7850595 | 1588 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1589 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1590 | local64_add(delta, &event->count); |
4574910e PM |
1591 | |
1592 | /* | |
cdd6c482 | 1593 | * See if the total period for this event has expired, |
4574910e PM |
1594 | * and update for the next period. |
1595 | */ | |
1596 | val = 0; | |
e7850595 | 1597 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1598 | if (delta == 0) |
1599 | left++; | |
60db5e09 | 1600 | if (period) { |
4574910e | 1601 | if (left <= 0) { |
60db5e09 | 1602 | left += period; |
4574910e | 1603 | if (left <= 0) |
60db5e09 | 1604 | left = period; |
e6878835 | 1605 | record = siar_valid(regs); |
4bca770e | 1606 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1607 | } |
98fb1807 PM |
1608 | if (left < 0x80000000LL) |
1609 | val = 0x80000000LL - left; | |
4574910e | 1610 | } |
4574910e | 1611 | |
a4eaf7f1 PZ |
1612 | write_pmc(event->hw.idx, val); |
1613 | local64_set(&event->hw.prev_count, val); | |
1614 | local64_set(&event->hw.period_left, left); | |
1615 | perf_event_update_userpage(event); | |
1616 | ||
4574910e PM |
1617 | /* |
1618 | * Finally record data if requested. | |
1619 | */ | |
0bbd0d4b | 1620 | if (record) { |
dc1d628a PZ |
1621 | struct perf_sample_data data; |
1622 | ||
fd0d000b | 1623 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1624 | |
cdd6c482 | 1625 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1626 | perf_get_data_addr(regs, &data.addr); |
1627 | ||
3925f46b AK |
1628 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1629 | struct cpu_hw_events *cpuhw; | |
1630 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1631 | power_pmu_bhrb_read(cpuhw); | |
1632 | data.br_stack = &cpuhw->bhrb_stack; | |
1633 | } | |
1634 | ||
a8b0ca17 | 1635 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1636 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1637 | } |
1638 | } | |
1639 | ||
1640 | /* | |
1641 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1642 | * for an event_id. |
0bbd0d4b PM |
1643 | */ |
1644 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1645 | { | |
98fb1807 | 1646 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1647 | |
98fb1807 PM |
1648 | if (flags) |
1649 | return flags; | |
cdd6c482 IM |
1650 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1651 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1652 | } |
1653 | ||
1654 | /* | |
1655 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1656 | * for an event_id. |
0bbd0d4b PM |
1657 | */ |
1658 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1659 | { | |
33904054 | 1660 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1661 | |
e6878835 | 1662 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1663 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1664 | else if (use_siar) |
1665 | return 0; // no valid instruction pointer | |
75382aa7 | 1666 | else |
1ce447b9 | 1667 | return regs->nip; |
4574910e PM |
1668 | } |
1669 | ||
bc09c219 | 1670 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1671 | { |
0837e324 AB |
1672 | /* |
1673 | * Events on POWER7 can roll back if a speculative event doesn't | |
1674 | * eventually complete. Unfortunately in some rare cases they will | |
1675 | * raise a performance monitor exception. We need to catch this to | |
1676 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1677 | * cycles from overflow. | |
1678 | * | |
1679 | * We only do this if the first pass fails to find any overflowing | |
1680 | * PMCs because a user might set a period of less than 256 and we | |
1681 | * don't want to mistakenly reset them. | |
1682 | */ | |
bc09c219 MN |
1683 | if ((0x80000000 - val) <= 256) |
1684 | return true; | |
1685 | ||
1686 | return false; | |
1687 | } | |
1688 | ||
1689 | static bool pmc_overflow(unsigned long val) | |
1690 | { | |
1691 | if ((int)val < 0) | |
0837e324 AB |
1692 | return true; |
1693 | ||
1694 | return false; | |
1695 | } | |
1696 | ||
4574910e PM |
1697 | /* |
1698 | * Performance monitor interrupt stuff | |
1699 | */ | |
cdd6c482 | 1700 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1701 | { |
bc09c219 | 1702 | int i, j; |
cdd6c482 IM |
1703 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1704 | struct perf_event *event; | |
bc09c219 MN |
1705 | unsigned long val[8]; |
1706 | int found, active; | |
ca8f2d7f PM |
1707 | int nmi; |
1708 | ||
ab7ef2e5 | 1709 | if (cpuhw->n_limited) |
a8f90e90 | 1710 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1711 | mfspr(SPRN_PMC6)); |
1712 | ||
98fb1807 | 1713 | perf_read_regs(regs); |
0bbd0d4b | 1714 | |
98fb1807 | 1715 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1716 | if (nmi) |
1717 | nmi_enter(); | |
1718 | else | |
1719 | irq_enter(); | |
4574910e | 1720 | |
bc09c219 MN |
1721 | /* Read all the PMCs since we'll need them a bunch of times */ |
1722 | for (i = 0; i < ppmu->n_counter; ++i) | |
1723 | val[i] = read_pmc(i + 1); | |
1724 | ||
1725 | /* Try to find what caused the IRQ */ | |
1726 | found = 0; | |
1727 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1728 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1729 | continue; |
bc09c219 MN |
1730 | if (is_limited_pmc(i + 1)) |
1731 | continue; /* these won't generate IRQs */ | |
1732 | /* | |
1733 | * We've found one that's overflowed. For active | |
1734 | * counters we need to log this. For inactive | |
1735 | * counters, we need to reset it anyway | |
1736 | */ | |
1737 | found = 1; | |
1738 | active = 0; | |
1739 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1740 | event = cpuhw->event[j]; | |
1741 | if (event->hw.idx == (i + 1)) { | |
1742 | active = 1; | |
1743 | record_and_restart(event, val[i], regs); | |
1744 | break; | |
1745 | } | |
4574910e | 1746 | } |
bc09c219 MN |
1747 | if (!active) |
1748 | /* reset non active counters that have overflowed */ | |
1749 | write_pmc(i + 1, 0); | |
4574910e | 1750 | } |
bc09c219 MN |
1751 | if (!found && pvr_version_is(PVR_POWER7)) { |
1752 | /* check active counters for special buggy p7 overflow */ | |
1753 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1754 | event = cpuhw->event[i]; | |
1755 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1756 | continue; |
bc09c219 MN |
1757 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1758 | /* event has overflowed in a buggy way*/ | |
1759 | found = 1; | |
1760 | record_and_restart(event, | |
1761 | val[event->hw.idx - 1], | |
1762 | regs); | |
1763 | } | |
4574910e PM |
1764 | } |
1765 | } | |
bc09c219 MN |
1766 | if ((!found) && printk_ratelimit()) |
1767 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); | |
4574910e PM |
1768 | |
1769 | /* | |
1770 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1771 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1772 | * and thus allow interrupts to occur again. |
cdd6c482 | 1773 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1774 | * we get back out of this interrupt. |
1775 | */ | |
ab7ef2e5 | 1776 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1777 | |
ca8f2d7f PM |
1778 | if (nmi) |
1779 | nmi_exit(); | |
1780 | else | |
db4fb5ac | 1781 | irq_exit(); |
4574910e PM |
1782 | } |
1783 | ||
3f6da390 | 1784 | static void power_pmu_setup(int cpu) |
01d0287f | 1785 | { |
cdd6c482 | 1786 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1787 | |
f36a1a13 PM |
1788 | if (!ppmu) |
1789 | return; | |
01d0287f PM |
1790 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1791 | cpuhw->mmcr[0] = MMCR0_FC; | |
1792 | } | |
1793 | ||
3f6da390 | 1794 | static int __cpuinit |
85cfabbc | 1795 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1796 | { |
1797 | unsigned int cpu = (long)hcpu; | |
1798 | ||
1799 | switch (action & ~CPU_TASKS_FROZEN) { | |
1800 | case CPU_UP_PREPARE: | |
1801 | power_pmu_setup(cpu); | |
1802 | break; | |
1803 | ||
1804 | default: | |
1805 | break; | |
1806 | } | |
1807 | ||
1808 | return NOTIFY_OK; | |
1809 | } | |
1810 | ||
77c2342a | 1811 | int __cpuinit register_power_pmu(struct power_pmu *pmu) |
4574910e | 1812 | { |
079b3c56 PM |
1813 | if (ppmu) |
1814 | return -EBUSY; /* something's already registered */ | |
1815 | ||
1816 | ppmu = pmu; | |
1817 | pr_info("%s performance monitor hardware support registered\n", | |
1818 | pmu->name); | |
d095cd46 | 1819 | |
1c53a270 SB |
1820 | power_pmu.attr_groups = ppmu->attr_groups; |
1821 | ||
98fb1807 | 1822 | #ifdef MSR_HV |
d095cd46 PM |
1823 | /* |
1824 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1825 | */ | |
1826 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1827 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1828 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1829 | |
2e80a82a | 1830 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1831 | perf_cpu_notifier(power_pmu_notifier); |
1832 | ||
4574910e PM |
1833 | return 0; |
1834 | } |