[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kvm / book3s_segment.S

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2010
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

/* Real mode helpers */

#if defined(CONFIG_PPC_BOOK3S_64)

#define GET_SHADOW_VCPU(reg)    \
	mr	reg, r13

#elif defined(CONFIG_PPC_BOOK3S_32)

#define GET_SHADOW_VCPU(reg)    			\
	tophys(reg, r2);       			\
	lwz     reg, (THREAD + THREAD_KVM_SVCPU)(reg);	\
	tophys(reg, reg)

#endif

/* Disable for nested KVM */
#define USE_QUICK_LAST_INST


/* Get helper functions for subarch specific functionality */

#if defined(CONFIG_PPC_BOOK3S_64)
#include "book3s_64_slb.S"
#elif defined(CONFIG_PPC_BOOK3S_32)
#include "book3s_32_sr.S"
#endif

/******************************************************************************
 *                                                                            *
 *                               Entry code                                   *
 *                                                                            *
 *****************************************************************************/

.global kvmppc_handler_trampoline_enter
kvmppc_handler_trampoline_enter:

	/* Required state:
	 *
	 * MSR = ~IR|DR
	 * R1 = host R1
	 * R2 = host R2
	 * R4 = guest shadow MSR
	 * R5 = normal host MSR
	 * R6 = current host MSR (EE, IR, DR off)
	 * LR = highmem guest exit code
	 * all other volatile GPRS = free
	 * SVCPU[CR] = guest CR
	 * SVCPU[XER] = guest XER
	 * SVCPU[CTR] = guest CTR
	 * SVCPU[LR] = guest LR
	 */

	/* r3 = shadow vcpu */
	GET_SHADOW_VCPU(r3)

	/* Save guest exit handler address and MSR */
	mflr	r0
	PPC_STL	r0, HSTATE_VMHANDLER(r3)
	PPC_STL	r5, HSTATE_HOST_MSR(r3)

	/* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
	PPC_STL	r1, HSTATE_HOST_R1(r3)
	PPC_STL	r2, HSTATE_HOST_R2(r3)

	/* Activate guest mode, so faults get handled by KVM */
	li	r11, KVM_GUEST_MODE_GUEST
	stb	r11, HSTATE_IN_GUEST(r3)

	/* Switch to guest segment. This is subarch specific. */
	LOAD_GUEST_SEGMENTS

#ifdef CONFIG_PPC_BOOK3S_64
	/* Some guests may need to have dcbz set to 32 byte length.
	 *
	 * Usually we ensure that by patching the guest's instructions
	 * to trap on dcbz and emulate it in the hypervisor.
	 *
	 * If we can, we should tell the CPU to use 32 byte dcbz though,
	 * because that's a lot faster.
	 */
	lbz	r0, HSTATE_RESTORE_HID5(r3)
	cmpwi	r0, 0
	beq	no_dcbz32_on

	mfspr   r0,SPRN_HID5
	ori     r0, r0, 0x80		/* XXX HID5_dcbz32 = 0x80 */
	mtspr   SPRN_HID5,r0
no_dcbz32_on:

#endif /* CONFIG_PPC_BOOK3S_64 */

	/* Enter guest */

	PPC_LL	r8, SVCPU_CTR(r3)
	PPC_LL	r9, SVCPU_LR(r3)
	lwz	r10, SVCPU_CR(r3)
	lwz	r11, SVCPU_XER(r3)

	mtctr	r8
	mtlr	r9
	mtcr	r10
	mtxer	r11

	/* Move SRR0 and SRR1 into the respective regs */
	PPC_LL  r9, SVCPU_PC(r3)
	/* First clear RI in our current MSR value */
	li	r0, MSR_RI
	andc	r6, r6, r0

	PPC_LL	r0, SVCPU_R0(r3)
	PPC_LL	r1, SVCPU_R1(r3)
	PPC_LL	r2, SVCPU_R2(r3)
	PPC_LL	r5, SVCPU_R5(r3)
	PPC_LL	r7, SVCPU_R7(r3)
	PPC_LL	r8, SVCPU_R8(r3)
	PPC_LL	r10, SVCPU_R10(r3)
	PPC_LL	r11, SVCPU_R11(r3)
	PPC_LL	r12, SVCPU_R12(r3)
	PPC_LL	r13, SVCPU_R13(r3)

	MTMSR_EERI(r6)
	mtsrr0	r9
	mtsrr1	r4

	PPC_LL	r4, SVCPU_R4(r3)
	PPC_LL	r6, SVCPU_R6(r3)
	PPC_LL	r9, SVCPU_R9(r3)
	PPC_LL	r3, (SVCPU_R3)(r3)

	RFI
kvmppc_handler_trampoline_enter_end:


/******************************************************************************
 *                                                                            *
 *                               Exit code                                    *
 *                                                                            *
 *****************************************************************************/

.global kvmppc_handler_trampoline_exit
kvmppc_handler_trampoline_exit:

.global kvmppc_interrupt
kvmppc_interrupt:

	/* Register usage at this point:
	 *
	 * SPRG_SCRATCH0  = guest R13
	 * R12            = exit handler id
	 * R13            = shadow vcpu (32-bit) or PACA (64-bit)
	 * HSTATE.SCRATCH0 = guest R12
	 * HSTATE.SCRATCH1 = guest CR
	 *
	 */

	/* Save registers */

	PPC_STL	r0, SVCPU_R0(r13)
	PPC_STL	r1, SVCPU_R1(r13)
	PPC_STL	r2, SVCPU_R2(r13)
	PPC_STL	r3, SVCPU_R3(r13)
	PPC_STL	r4, SVCPU_R4(r13)
	PPC_STL	r5, SVCPU_R5(r13)
	PPC_STL	r6, SVCPU_R6(r13)
	PPC_STL	r7, SVCPU_R7(r13)
	PPC_STL	r8, SVCPU_R8(r13)
	PPC_STL	r9, SVCPU_R9(r13)
	PPC_STL	r10, SVCPU_R10(r13)
	PPC_STL	r11, SVCPU_R11(r13)

	/* Restore R1/R2 so we can handle faults */
	PPC_LL	r1, HSTATE_HOST_R1(r13)
	PPC_LL	r2, HSTATE_HOST_R2(r13)

	/* Save guest PC and MSR */
#ifdef CONFIG_PPC64
BEGIN_FTR_SECTION
	andi.	r0, r12, 0x2
	cmpwi	cr1, r0, 0
	beq	1f
	mfspr	r3,SPRN_HSRR0
	mfspr	r4,SPRN_HSRR1
	andi.	r12,r12,0x3ffd
	b	2f
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
#endif
1:	mfsrr0	r3
	mfsrr1	r4
2:
	PPC_STL	r3, SVCPU_PC(r13)
	PPC_STL	r4, SVCPU_SHADOW_SRR1(r13)

	/* Get scratch'ed off registers */
	GET_SCRATCH0(r9)
	PPC_LL	r8, HSTATE_SCRATCH0(r13)
	lwz	r7, HSTATE_SCRATCH1(r13)

	PPC_STL	r9, SVCPU_R13(r13)
	PPC_STL	r8, SVCPU_R12(r13)
	stw	r7, SVCPU_CR(r13)

	/* Save more register state  */

	mfxer	r5
	mfdar	r6
	mfdsisr	r7
	mfctr	r8
	mflr	r9

	stw	r5, SVCPU_XER(r13)
	PPC_STL	r6, SVCPU_FAULT_DAR(r13)
	stw	r7, SVCPU_FAULT_DSISR(r13)
	PPC_STL	r8, SVCPU_CTR(r13)
	PPC_STL	r9, SVCPU_LR(r13)

	/*
	 * In order for us to easily get the last instruction,
	 * we got the #vmexit at, we exploit the fact that the
	 * virtual layout is still the same here, so we can just
	 * ld from the guest's PC address
	 */

	/* We only load the last instruction when it's safe */
	cmpwi	r12, BOOK3S_INTERRUPT_DATA_STORAGE
	beq	ld_last_inst
	cmpwi	r12, BOOK3S_INTERRUPT_PROGRAM
	beq	ld_last_inst
	cmpwi	r12, BOOK3S_INTERRUPT_SYSCALL
	beq	ld_last_prev_inst
	cmpwi	r12, BOOK3S_INTERRUPT_ALIGNMENT
	beq-	ld_last_inst
#ifdef CONFIG_PPC64
BEGIN_FTR_SECTION
	cmpwi	r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
	beq-	ld_last_inst
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
#endif

	b	no_ld_last_inst

ld_last_prev_inst:
	addi	r3, r3, -4

ld_last_inst:
	/* Save off the guest instruction we're at */

	/* In case lwz faults */
	li	r0, KVM_INST_FETCH_FAILED

#ifdef USE_QUICK_LAST_INST

	/* Set guest mode to 'jump over instruction' so if lwz faults
	 * we'll just continue at the next IP. */
	li	r9, KVM_GUEST_MODE_SKIP
	stb	r9, HSTATE_IN_GUEST(r13)

	/*    1) enable paging for data */
	mfmsr	r9
	ori	r11, r9, MSR_DR			/* Enable paging for data */
	mtmsr	r11
	sync
	/*    2) fetch the instruction */
	lwz	r0, 0(r3)
	/*    3) disable paging again */
	mtmsr	r9
	sync

#endif
	stw	r0, SVCPU_LAST_INST(r13)

no_ld_last_inst:

	/* Unset guest mode */
	li	r9, KVM_GUEST_MODE_NONE
	stb	r9, HSTATE_IN_GUEST(r13)

	/* Switch back to host MMU */
	LOAD_HOST_SEGMENTS

#ifdef CONFIG_PPC_BOOK3S_64

	lbz	r5, HSTATE_RESTORE_HID5(r13)
	cmpwi	r5, 0
	beq	no_dcbz32_off

	li	r4, 0
	mfspr   r5,SPRN_HID5
	rldimi  r5,r4,6,56
	mtspr   SPRN_HID5,r5

no_dcbz32_off:

#endif /* CONFIG_PPC_BOOK3S_64 */

	/*
	 * For some interrupts, we need to call the real Linux
	 * handler, so it can do work for us. This has to happen
	 * as if the interrupt arrived from the kernel though,
	 * so let's fake it here where most state is restored.
	 *
	 * Having set up SRR0/1 with the address where we want
	 * to continue with relocation on (potentially in module
	 * space), we either just go straight there with rfi[d],
	 * or we jump to an interrupt handler if there is an
	 * interrupt to be handled first.  In the latter case,
	 * the rfi[d] at the end of the interrupt handler will
	 * get us back to where we want to continue.
	 */

	/* Register usage at this point:
	 *
	 * R1       = host R1
	 * R2       = host R2
	 * R10      = raw exit handler id
	 * R12      = exit handler id
	 * R13      = shadow vcpu (32-bit) or PACA (64-bit)
	 * SVCPU.*  = guest *
	 *
	 */

	PPC_LL	r6, HSTATE_HOST_MSR(r13)
	PPC_LL	r8, HSTATE_VMHANDLER(r13)

#ifdef CONFIG_PPC64
BEGIN_FTR_SECTION
	beq	cr1, 1f
	mtspr	SPRN_HSRR1, r6
	mtspr	SPRN_HSRR0, r8
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
#endif
1:	/* Restore host msr -> SRR1 */
	mtsrr1	r6
	/* Load highmem handler address */
	mtsrr0	r8

	/* RFI into the highmem handler, or jump to interrupt handler */
	cmpwi	r12, BOOK3S_INTERRUPT_EXTERNAL
	beqa	BOOK3S_INTERRUPT_EXTERNAL
	cmpwi	r12, BOOK3S_INTERRUPT_DECREMENTER
	beqa	BOOK3S_INTERRUPT_DECREMENTER
	cmpwi	r12, BOOK3S_INTERRUPT_PERFMON
	beqa	BOOK3S_INTERRUPT_PERFMON

	RFI
kvmppc_handler_trampoline_exit_end:
Commit	Line	Data
07372794 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2010
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	/* Real mode helpers */
	21
	22	#if defined(CONFIG_PPC_BOOK3S_64)
	23
	24	#define GET_SHADOW_VCPU(reg) \
3c42bf8a	25	mr reg, r13
07372794 AG	26
	27	#elif defined(CONFIG_PPC_BOOK3S_32)
	28
	29	#define GET_SHADOW_VCPU(reg) \
	30	tophys(reg, r2); \
	31	lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
	32	tophys(reg, reg)
	33
	34	#endif
	35
	36	/* Disable for nested KVM */
	37	#define USE_QUICK_LAST_INST
	38
	39
	40	/* Get helper functions for subarch specific functionality */
	41
	42	#if defined(CONFIG_PPC_BOOK3S_64)
	43	#include "book3s_64_slb.S"
	44	#elif defined(CONFIG_PPC_BOOK3S_32)
	45	#include "book3s_32_sr.S"
	46	#endif
	47
	48	/******************************************************************************
	49	* *
	50	* Entry code *
	51	* *
	52	*****************************************************************************/
	53
	54	.global kvmppc_handler_trampoline_enter
	55	kvmppc_handler_trampoline_enter:
	56
	57	/* Required state:
	58	*
	59	* MSR = ~IR\|DR
07372794 AG	60	* R1 = host R1
07372794 AG	61	* R2 = host R2
02143947 PM	62	* R4 = guest shadow MSR
	63	* R5 = normal host MSR
	64	* R6 = current host MSR (EE, IR, DR off)
	65	* LR = highmem guest exit code
07372794 AG	66	* all other volatile GPRS = free
	67	* SVCPU[CR] = guest CR
	68	* SVCPU[XER] = guest XER
	69	* SVCPU[CTR] = guest CTR
	70	* SVCPU[LR] = guest LR
	71	*/
	72
	73	/* r3 = shadow vcpu */
	74	GET_SHADOW_VCPU(r3)
	75
02143947 PM	76	/* Save guest exit handler address and MSR */
	77	mflr r0
	78	PPC_STL r0, HSTATE_VMHANDLER(r3)
	79	PPC_STL r5, HSTATE_HOST_MSR(r3)
	80
3c42bf8a PM	81	/* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
	82	PPC_STL r1, HSTATE_HOST_R1(r3)
	83	PPC_STL r2, HSTATE_HOST_R2(r3)
	84
07372794 AG	85	/* Activate guest mode, so faults get handled by KVM */
07372794 AG	86	li r11, KVM_GUEST_MODE_GUEST
3c42bf8a	87	stb r11, HSTATE_IN_GUEST(r3)
07372794 AG	88
	89	/* Switch to guest segment. This is subarch specific. */
	90	LOAD_GUEST_SEGMENTS
	91
02143947 PM	92	#ifdef CONFIG_PPC_BOOK3S_64
	93	/* Some guests may need to have dcbz set to 32 byte length.
	94	*
	95	* Usually we ensure that by patching the guest's instructions
	96	* to trap on dcbz and emulate it in the hypervisor.
	97	*
	98	* If we can, we should tell the CPU to use 32 byte dcbz though,
	99	* because that's a lot faster.
	100	*/
	101	lbz r0, HSTATE_RESTORE_HID5(r3)
	102	cmpwi r0, 0
	103	beq no_dcbz32_on
	104
	105	mfspr r0,SPRN_HID5
	106	ori r0, r0, 0x80 /* XXX HID5_dcbz32 = 0x80 */
	107	mtspr SPRN_HID5,r0
	108	no_dcbz32_on:
	109
	110	#endif /* CONFIG_PPC_BOOK3S_64 */
	111
07372794 AG	112	/* Enter guest */
07372794 AG	113
02143947 PM	114	PPC_LL r8, SVCPU_CTR(r3)
	115	PPC_LL r9, SVCPU_LR(r3)
	116	lwz r10, SVCPU_CR(r3)
	117	lwz r11, SVCPU_XER(r3)
	118
	119	mtctr r8
	120	mtlr r9
	121	mtcr r10
	122	mtxer r11
07372794	123
02143947 PM	124	/* Move SRR0 and SRR1 into the respective regs */
	125	PPC_LL r9, SVCPU_PC(r3)
	126	/* First clear RI in our current MSR value */
	127	li r0, MSR_RI
	128	andc r6, r6, r0
07372794	129
de56a948 PM	130	PPC_LL r0, SVCPU_R0(r3)
	131	PPC_LL r1, SVCPU_R1(r3)
	132	PPC_LL r2, SVCPU_R2(r3)
de56a948	133	PPC_LL r5, SVCPU_R5(r3)
de56a948 PM	134	PPC_LL r7, SVCPU_R7(r3)
de56a948 PM	135	PPC_LL r8, SVCPU_R8(r3)
de56a948 PM	136	PPC_LL r10, SVCPU_R10(r3)
	137	PPC_LL r11, SVCPU_R11(r3)
	138	PPC_LL r12, SVCPU_R12(r3)
	139	PPC_LL r13, SVCPU_R13(r3)
07372794	140
8c2d0be7 AG	141	MTMSR_EERI(r6)
	142	mtsrr0 r9
	143	mtsrr1 r4
	144
	145	PPC_LL r4, SVCPU_R4(r3)
	146	PPC_LL r6, SVCPU_R6(r3)
	147	PPC_LL r9, SVCPU_R9(r3)
07372794 AG	148	PPC_LL r3, (SVCPU_R3)(r3)
	149
	150	RFI
	151	kvmppc_handler_trampoline_enter_end:
	152
	153
	154
	155	/******************************************************************************
	156	* *
	157	* Exit code *
	158	* *
	159	*****************************************************************************/
	160
	161	.global kvmppc_handler_trampoline_exit
	162	kvmppc_handler_trampoline_exit:
	163
b01c8b54 PM	164	.global kvmppc_interrupt
	165	kvmppc_interrupt:
	166
07372794 AG	167	/* Register usage at this point:
	168	*
	169	* SPRG_SCRATCH0 = guest R13
	170	* R12 = exit handler id
3c42bf8a PM	171	* R13 = shadow vcpu (32-bit) or PACA (64-bit)
	172	* HSTATE.SCRATCH0 = guest R12
	173	* HSTATE.SCRATCH1 = guest CR
07372794 AG	174	*
	175	*/
	176
	177	/* Save registers */
	178
3c42bf8a PM	179	PPC_STL r0, SVCPU_R0(r13)
	180	PPC_STL r1, SVCPU_R1(r13)
	181	PPC_STL r2, SVCPU_R2(r13)
	182	PPC_STL r3, SVCPU_R3(r13)
	183	PPC_STL r4, SVCPU_R4(r13)
	184	PPC_STL r5, SVCPU_R5(r13)
	185	PPC_STL r6, SVCPU_R6(r13)
	186	PPC_STL r7, SVCPU_R7(r13)
	187	PPC_STL r8, SVCPU_R8(r13)
	188	PPC_STL r9, SVCPU_R9(r13)
	189	PPC_STL r10, SVCPU_R10(r13)
	190	PPC_STL r11, SVCPU_R11(r13)
07372794 AG	191
07372794 AG	192	/* Restore R1/R2 so we can handle faults */
3c42bf8a PM	193	PPC_LL r1, HSTATE_HOST_R1(r13)
3c42bf8a PM	194	PPC_LL r2, HSTATE_HOST_R2(r13)
07372794 AG	195
07372794 AG	196	/* Save guest PC and MSR */
b01c8b54 PM	197	#ifdef CONFIG_PPC64
b01c8b54 PM	198	BEGIN_FTR_SECTION
32c7dbfd AG	199	andi. r0, r12, 0x2
32c7dbfd AG	200	cmpwi cr1, r0, 0
a5d4f3ad BH	201	beq 1f
	202	mfspr r3,SPRN_HSRR0
	203	mfspr r4,SPRN_HSRR1
	204	andi. r12,r12,0x3ffd
	205	b 2f
969391c5	206	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
b01c8b54	207	#endif
a5d4f3ad	208	1: mfsrr0 r3
07372794	209	mfsrr1 r4
a5d4f3ad	210	2:
3c42bf8a PM	211	PPC_STL r3, SVCPU_PC(r13)
3c42bf8a PM	212	PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
07372794 AG	213
07372794 AG	214	/* Get scratch'ed off registers */
673b189a	215	GET_SCRATCH0(r9)
3c42bf8a PM	216	PPC_LL r8, HSTATE_SCRATCH0(r13)
3c42bf8a PM	217	lwz r7, HSTATE_SCRATCH1(r13)
07372794	218
3c42bf8a PM	219	PPC_STL r9, SVCPU_R13(r13)
	220	PPC_STL r8, SVCPU_R12(r13)
	221	stw r7, SVCPU_CR(r13)
07372794 AG	222
	223	/* Save more register state */
	224
	225	mfxer r5
	226	mfdar r6
	227	mfdsisr r7
	228	mfctr r8
	229	mflr r9
	230
3c42bf8a PM	231	stw r5, SVCPU_XER(r13)
	232	PPC_STL r6, SVCPU_FAULT_DAR(r13)
	233	stw r7, SVCPU_FAULT_DSISR(r13)
	234	PPC_STL r8, SVCPU_CTR(r13)
	235	PPC_STL r9, SVCPU_LR(r13)
07372794 AG	236
	237	/*
	238	* In order for us to easily get the last instruction,
	239	* we got the #vmexit at, we exploit the fact that the
	240	* virtual layout is still the same here, so we can just
	241	* ld from the guest's PC address
	242	*/
	243
	244	/* We only load the last instruction when it's safe */
	245	cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
	246	beq ld_last_inst
	247	cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
	248	beq ld_last_inst
77e675ad AG	249	cmpwi r12, BOOK3S_INTERRUPT_SYSCALL
77e675ad AG	250	beq ld_last_prev_inst
6fc55825 AG	251	cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
6fc55825 AG	252	beq- ld_last_inst
7ef4e985 AG	253	#ifdef CONFIG_PPC64
	254	BEGIN_FTR_SECTION
	255	cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
	256	beq- ld_last_inst
	257	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
	258	#endif
07372794 AG	259
	260	b no_ld_last_inst
	261
77e675ad AG	262	ld_last_prev_inst:
	263	addi r3, r3, -4
	264
07372794 AG	265	ld_last_inst:
	266	/* Save off the guest instruction we're at */
	267
	268	/* In case lwz faults */
	269	li r0, KVM_INST_FETCH_FAILED
	270
	271	#ifdef USE_QUICK_LAST_INST
	272
	273	/* Set guest mode to 'jump over instruction' so if lwz faults
	274	* we'll just continue at the next IP. */
	275	li r9, KVM_GUEST_MODE_SKIP
3c42bf8a	276	stb r9, HSTATE_IN_GUEST(r13)
07372794 AG	277
	278	/* 1) enable paging for data */
	279	mfmsr r9
	280	ori r11, r9, MSR_DR /* Enable paging for data */
	281	mtmsr r11
	282	sync
	283	/* 2) fetch the instruction */
	284	lwz r0, 0(r3)
	285	/* 3) disable paging again */
	286	mtmsr r9
	287	sync
	288
	289	#endif
3c42bf8a	290	stw r0, SVCPU_LAST_INST(r13)
07372794 AG	291
	292	no_ld_last_inst:
	293
	294	/* Unset guest mode */
	295	li r9, KVM_GUEST_MODE_NONE
3c42bf8a	296	stb r9, HSTATE_IN_GUEST(r13)
07372794 AG	297
	298	/* Switch back to host MMU */
	299	LOAD_HOST_SEGMENTS
	300
02143947 PM	301	#ifdef CONFIG_PPC_BOOK3S_64
	302
	303	lbz r5, HSTATE_RESTORE_HID5(r13)
	304	cmpwi r5, 0
	305	beq no_dcbz32_off
	306
	307	li r4, 0
	308	mfspr r5,SPRN_HID5
	309	rldimi r5,r4,6,56
	310	mtspr SPRN_HID5,r5
	311
	312	no_dcbz32_off:
	313
	314	#endif /* CONFIG_PPC_BOOK3S_64 */
	315
	316	/*
	317	* For some interrupts, we need to call the real Linux
	318	* handler, so it can do work for us. This has to happen
	319	* as if the interrupt arrived from the kernel though,
	320	* so let's fake it here where most state is restored.
	321	*
	322	* Having set up SRR0/1 with the address where we want
	323	* to continue with relocation on (potentially in module
	324	* space), we either just go straight there with rfi[d],
56e13dba AG	325	* or we jump to an interrupt handler if there is an
	326	* interrupt to be handled first. In the latter case,
	327	* the rfi[d] at the end of the interrupt handler will
	328	* get us back to where we want to continue.
02143947 PM	329	*/
02143947 PM	330
07372794 AG	331	/* Register usage at this point:
	332	*
	333	* R1 = host R1
	334	* R2 = host R2
56e13dba	335	* R10 = raw exit handler id
07372794	336	* R12 = exit handler id
3c42bf8a	337	* R13 = shadow vcpu (32-bit) or PACA (64-bit)
07372794 AG	338	* SVCPU.* = guest *
	339	*
	340	*/
	341
02143947	342	PPC_LL r6, HSTATE_HOST_MSR(r13)
3c42bf8a	343	PPC_LL r8, HSTATE_VMHANDLER(r13)
02143947	344
56e13dba AG	345	#ifdef CONFIG_PPC64
56e13dba AG	346	BEGIN_FTR_SECTION
32c7dbfd	347	beq cr1, 1f
56e13dba AG	348	mtspr SPRN_HSRR1, r6
	349	mtspr SPRN_HSRR0, r8
	350	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
	351	#endif
	352	1: /* Restore host msr -> SRR1 */
02143947 PM	353	mtsrr1 r6
02143947 PM	354	/* Load highmem handler address */
07372794 AG	355	mtsrr0 r8
07372794 AG	356
02143947	357	/* RFI into the highmem handler, or jump to interrupt handler */
56e13dba AG	358	cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
	359	beqa BOOK3S_INTERRUPT_EXTERNAL
	360	cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
	361	beqa BOOK3S_INTERRUPT_DECREMENTER
	362	cmpwi r12, BOOK3S_INTERRUPT_PERFMON
	363	beqa BOOK3S_INTERRUPT_PERFMON
	364
07372794 AG	365	RFI
07372794 AG	366	kvmppc_handler_trampoline_exit_end: