Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Signal trampoline for 64 bits processes in a ppc64 kernel for | |
3 | * use in the vDSO | |
4 | * | |
5 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp. | |
6 | * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
1da177e4 LT |
13 | #include <asm/processor.h> |
14 | #include <asm/ppc_asm.h> | |
15 | #include <asm/unistd.h> | |
16 | #include <asm/vdso.h> | |
b60fc8bb | 17 | #include <asm/ptrace.h> /* XXX for __SIGNAL_FRAMESIZE */ |
1da177e4 LT |
18 | |
19 | .text | |
20 | ||
21 | /* The nop here is a hack. The dwarf2 unwind routines subtract 1 from | |
22 | the return address to get an address in the middle of the presumed | |
23 | call instruction. Since we don't have a call here, we artifically | |
24 | extend the range covered by the unwind info by padding before the | |
25 | real start. */ | |
26 | nop | |
27 | .balign 8 | |
28 | V_FUNCTION_BEGIN(__kernel_sigtramp_rt64) | |
29 | .Lsigrt_start = . - 4 | |
30 | addi r1, r1, __SIGNAL_FRAMESIZE | |
31 | li r0,__NR_rt_sigreturn | |
32 | sc | |
33 | .Lsigrt_end: | |
34 | V_FUNCTION_END(__kernel_sigtramp_rt64) | |
35 | /* The ".balign 8" above and the following zeros mimic the old stack | |
36 | trampoline layout. The last magic value is the ucontext pointer, | |
37 | chosen in such a way that older libgcc unwind code returns a zero | |
38 | for a sigcontext pointer. */ | |
39 | .long 0,0,0 | |
40 | .quad 0,-21*8 | |
41 | ||
42 | /* Register r1 can be found at offset 8 of a pt_regs structure. | |
43 | A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ | |
44 | #define cfa_save \ | |
45 | .byte 0x0f; /* DW_CFA_def_cfa_expression */ \ | |
46 | .uleb128 9f - 1f; /* length */ \ | |
47 | 1: \ | |
48 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ | |
49 | .byte 0x06; /* DW_OP_deref */ \ | |
50 | .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \ | |
51 | .byte 0x06; /* DW_OP_deref */ \ | |
52 | 9: | |
53 | ||
54 | /* Register REGNO can be found at offset OFS of a pt_regs structure. | |
55 | A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ | |
56 | #define rsave(regno, ofs) \ | |
57 | .byte 0x10; /* DW_CFA_expression */ \ | |
58 | .uleb128 regno; /* regno */ \ | |
59 | .uleb128 9f - 1f; /* length */ \ | |
60 | 1: \ | |
61 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ | |
62 | .byte 0x06; /* DW_OP_deref */ \ | |
63 | .ifne ofs; \ | |
64 | .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ | |
65 | .endif; \ | |
66 | 9: | |
67 | ||
68 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 | |
69 | of the VMX reg struct. A pointer to the VMX reg struct is at VREGS in | |
70 | the pt_regs struct. This macro is for REGNO == 0, and contains | |
71 | 'subroutines' that the other macros jump to. */ | |
72 | #define vsave_msr0(regno) \ | |
73 | .byte 0x10; /* DW_CFA_expression */ \ | |
74 | .uleb128 regno + 77; /* regno */ \ | |
75 | .uleb128 9f - 1f; /* length */ \ | |
76 | 1: \ | |
77 | .byte 0x30 + regno; /* DW_OP_lit0 */ \ | |
78 | 2: \ | |
79 | .byte 0x40; /* DW_OP_lit16 */ \ | |
80 | .byte 0x1e; /* DW_OP_mul */ \ | |
81 | 3: \ | |
82 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ | |
83 | .byte 0x06; /* DW_OP_deref */ \ | |
84 | .byte 0x12; /* DW_OP_dup */ \ | |
85 | .byte 0x23; /* DW_OP_plus_uconst */ \ | |
86 | .uleb128 33*RSIZE; /* msr offset */ \ | |
87 | .byte 0x06; /* DW_OP_deref */ \ | |
88 | .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \ | |
89 | .byte 0x1a; /* DW_OP_and */ \ | |
90 | .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \ | |
91 | .byte 0x30; /* DW_OP_lit0 */ \ | |
92 | .byte 0x29; /* DW_OP_eq */ \ | |
93 | .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \ | |
94 | .byte 0x13; /* DW_OP_drop, pop the 0 */ \ | |
95 | .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ | |
96 | .byte 0x06; /* DW_OP_deref */ \ | |
97 | .byte 0x22; /* DW_OP_plus */ \ | |
98 | .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \ | |
99 | 9: | |
100 | ||
101 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 | |
102 | of the VMX reg struct. REGNO is 1 thru 31. */ | |
103 | #define vsave_msr1(regno) \ | |
104 | .byte 0x10; /* DW_CFA_expression */ \ | |
105 | .uleb128 regno + 77; /* regno */ \ | |
106 | .uleb128 9f - 1f; /* length */ \ | |
107 | 1: \ | |
108 | .byte 0x30 + regno; /* DW_OP_lit n */ \ | |
109 | .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \ | |
110 | 9: | |
111 | ||
112 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of | |
113 | the VMX save block. */ | |
114 | #define vsave_msr2(regno, ofs) \ | |
115 | .byte 0x10; /* DW_CFA_expression */ \ | |
116 | .uleb128 regno + 77; /* regno */ \ | |
117 | .uleb128 9f - 1f; /* length */ \ | |
118 | 1: \ | |
119 | .byte 0x0a; .short ofs; /* DW_OP_const2u */ \ | |
120 | .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \ | |
121 | 9: | |
122 | ||
123 | /* VMX register REGNO is at offset OFS of the VMX save area. */ | |
124 | #define vsave(regno, ofs) \ | |
125 | .byte 0x10; /* DW_CFA_expression */ \ | |
126 | .uleb128 regno + 77; /* regno */ \ | |
127 | .uleb128 9f - 1f; /* length */ \ | |
128 | 1: \ | |
129 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ | |
130 | .byte 0x06; /* DW_OP_deref */ \ | |
131 | .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ | |
132 | .byte 0x06; /* DW_OP_deref */ \ | |
133 | .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ | |
134 | 9: | |
135 | ||
136 | /* This is where the pt_regs pointer can be found on the stack. */ | |
137 | #define PTREGS 128+168+56 | |
138 | ||
139 | /* Size of regs. */ | |
140 | #define RSIZE 8 | |
141 | ||
142 | /* This is the offset of the VMX reg pointer. */ | |
143 | #define VREGS 48*RSIZE+33*8 | |
144 | ||
145 | /* Describe where general purpose regs are saved. */ | |
146 | #define EH_FRAME_GEN \ | |
147 | cfa_save; \ | |
148 | rsave ( 0, 0*RSIZE); \ | |
149 | rsave ( 2, 2*RSIZE); \ | |
150 | rsave ( 3, 3*RSIZE); \ | |
151 | rsave ( 4, 4*RSIZE); \ | |
152 | rsave ( 5, 5*RSIZE); \ | |
153 | rsave ( 6, 6*RSIZE); \ | |
154 | rsave ( 7, 7*RSIZE); \ | |
155 | rsave ( 8, 8*RSIZE); \ | |
156 | rsave ( 9, 9*RSIZE); \ | |
157 | rsave (10, 10*RSIZE); \ | |
158 | rsave (11, 11*RSIZE); \ | |
159 | rsave (12, 12*RSIZE); \ | |
160 | rsave (13, 13*RSIZE); \ | |
161 | rsave (14, 14*RSIZE); \ | |
162 | rsave (15, 15*RSIZE); \ | |
163 | rsave (16, 16*RSIZE); \ | |
164 | rsave (17, 17*RSIZE); \ | |
165 | rsave (18, 18*RSIZE); \ | |
166 | rsave (19, 19*RSIZE); \ | |
167 | rsave (20, 20*RSIZE); \ | |
168 | rsave (21, 21*RSIZE); \ | |
169 | rsave (22, 22*RSIZE); \ | |
170 | rsave (23, 23*RSIZE); \ | |
171 | rsave (24, 24*RSIZE); \ | |
172 | rsave (25, 25*RSIZE); \ | |
173 | rsave (26, 26*RSIZE); \ | |
174 | rsave (27, 27*RSIZE); \ | |
175 | rsave (28, 28*RSIZE); \ | |
176 | rsave (29, 29*RSIZE); \ | |
177 | rsave (30, 30*RSIZE); \ | |
178 | rsave (31, 31*RSIZE); \ | |
179 | rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \ | |
180 | rsave (65, 36*RSIZE); /* lr */ \ | |
181 | rsave (70, 38*RSIZE) /* cr */ | |
182 | ||
183 | /* Describe where the FP regs are saved. */ | |
184 | #define EH_FRAME_FP \ | |
185 | rsave (32, 48*RSIZE + 0*8); \ | |
186 | rsave (33, 48*RSIZE + 1*8); \ | |
187 | rsave (34, 48*RSIZE + 2*8); \ | |
188 | rsave (35, 48*RSIZE + 3*8); \ | |
189 | rsave (36, 48*RSIZE + 4*8); \ | |
190 | rsave (37, 48*RSIZE + 5*8); \ | |
191 | rsave (38, 48*RSIZE + 6*8); \ | |
192 | rsave (39, 48*RSIZE + 7*8); \ | |
193 | rsave (40, 48*RSIZE + 8*8); \ | |
194 | rsave (41, 48*RSIZE + 9*8); \ | |
195 | rsave (42, 48*RSIZE + 10*8); \ | |
196 | rsave (43, 48*RSIZE + 11*8); \ | |
197 | rsave (44, 48*RSIZE + 12*8); \ | |
198 | rsave (45, 48*RSIZE + 13*8); \ | |
199 | rsave (46, 48*RSIZE + 14*8); \ | |
200 | rsave (47, 48*RSIZE + 15*8); \ | |
201 | rsave (48, 48*RSIZE + 16*8); \ | |
202 | rsave (49, 48*RSIZE + 17*8); \ | |
203 | rsave (50, 48*RSIZE + 18*8); \ | |
204 | rsave (51, 48*RSIZE + 19*8); \ | |
205 | rsave (52, 48*RSIZE + 20*8); \ | |
206 | rsave (53, 48*RSIZE + 21*8); \ | |
207 | rsave (54, 48*RSIZE + 22*8); \ | |
208 | rsave (55, 48*RSIZE + 23*8); \ | |
209 | rsave (56, 48*RSIZE + 24*8); \ | |
210 | rsave (57, 48*RSIZE + 25*8); \ | |
211 | rsave (58, 48*RSIZE + 26*8); \ | |
212 | rsave (59, 48*RSIZE + 27*8); \ | |
213 | rsave (60, 48*RSIZE + 28*8); \ | |
214 | rsave (61, 48*RSIZE + 29*8); \ | |
215 | rsave (62, 48*RSIZE + 30*8); \ | |
216 | rsave (63, 48*RSIZE + 31*8) | |
217 | ||
218 | /* Describe where the VMX regs are saved. */ | |
219 | #ifdef CONFIG_ALTIVEC | |
220 | #define EH_FRAME_VMX \ | |
221 | vsave_msr0 ( 0); \ | |
222 | vsave_msr1 ( 1); \ | |
223 | vsave_msr1 ( 2); \ | |
224 | vsave_msr1 ( 3); \ | |
225 | vsave_msr1 ( 4); \ | |
226 | vsave_msr1 ( 5); \ | |
227 | vsave_msr1 ( 6); \ | |
228 | vsave_msr1 ( 7); \ | |
229 | vsave_msr1 ( 8); \ | |
230 | vsave_msr1 ( 9); \ | |
231 | vsave_msr1 (10); \ | |
232 | vsave_msr1 (11); \ | |
233 | vsave_msr1 (12); \ | |
234 | vsave_msr1 (13); \ | |
235 | vsave_msr1 (14); \ | |
236 | vsave_msr1 (15); \ | |
237 | vsave_msr1 (16); \ | |
238 | vsave_msr1 (17); \ | |
239 | vsave_msr1 (18); \ | |
240 | vsave_msr1 (19); \ | |
241 | vsave_msr1 (20); \ | |
242 | vsave_msr1 (21); \ | |
243 | vsave_msr1 (22); \ | |
244 | vsave_msr1 (23); \ | |
245 | vsave_msr1 (24); \ | |
246 | vsave_msr1 (25); \ | |
247 | vsave_msr1 (26); \ | |
248 | vsave_msr1 (27); \ | |
249 | vsave_msr1 (28); \ | |
250 | vsave_msr1 (29); \ | |
251 | vsave_msr1 (30); \ | |
252 | vsave_msr1 (31); \ | |
253 | vsave_msr2 (33, 32*16+12); \ | |
254 | vsave (32, 33*16) | |
255 | #else | |
256 | #define EH_FRAME_VMX | |
257 | #endif | |
258 | ||
259 | .section .eh_frame,"a",@progbits | |
260 | .Lcie: | |
261 | .long .Lcie_end - .Lcie_start | |
262 | .Lcie_start: | |
263 | .long 0 /* CIE ID */ | |
264 | .byte 1 /* Version number */ | |
da2e9e1f | 265 | .string "zRS" /* NUL-terminated augmentation string */ |
1da177e4 LT |
266 | .uleb128 4 /* Code alignment factor */ |
267 | .sleb128 -8 /* Data alignment factor */ | |
268 | .byte 67 /* Return address register column, ap */ | |
269 | .uleb128 1 /* Augmentation value length */ | |
270 | .byte 0x14 /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */ | |
271 | .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */ | |
272 | .balign 8 | |
273 | .Lcie_end: | |
274 | ||
275 | .long .Lfde0_end - .Lfde0_start | |
276 | .Lfde0_start: | |
277 | .long .Lfde0_start - .Lcie /* CIE pointer. */ | |
278 | .quad .Lsigrt_start - . /* PC start, length */ | |
279 | .quad .Lsigrt_end - .Lsigrt_start | |
280 | .uleb128 0 /* Augmentation */ | |
281 | EH_FRAME_GEN | |
282 | EH_FRAME_FP | |
283 | EH_FRAME_VMX | |
284 | # Do we really need to describe the frame at this point? ie. will | |
285 | # we ever have some call chain that returns somewhere past the addi? | |
286 | # I don't think so, since gcc doesn't support async signals. | |
287 | # .byte 0x41 /* DW_CFA_advance_loc 1*4 */ | |
288 | #undef PTREGS | |
289 | #define PTREGS 168+56 | |
290 | # EH_FRAME_GEN | |
291 | # EH_FRAME_FP | |
292 | # EH_FRAME_VMX | |
293 | .balign 8 | |
294 | .Lfde0_end: |