[POWERPC] Remove ioremap64 and fixup_bigphys_addr
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / vdso64 / cacheflush.S
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1/*
2 * vDSO provided cache flush routines
3 *
4 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
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12#include <asm/processor.h>
13#include <asm/ppc_asm.h>
14#include <asm/vdso.h>
0013a854 15#include <asm/asm-offsets.h>
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16
17 .text
18
19/*
20 * Default "generic" version of __kernel_sync_dicache.
21 *
22 * void __kernel_sync_dicache(unsigned long start, unsigned long end)
23 *
24 * Flushes the data cache & invalidate the instruction cache for the
25 * provided range [start, end[
26 *
27 * Note: all CPUs supported by this kernel have a 128 bytes cache
28 * line size so we don't have to peek that info from the datapage
29 */
30V_FUNCTION_BEGIN(__kernel_sync_dicache)
31 .cfi_startproc
32 li r5,127
33 andc r6,r3,r5 /* round low to line bdy */
34 subf r8,r6,r4 /* compute length */
35 add r8,r8,r5 /* ensure we get enough */
36 srwi. r8,r8,7 /* compute line count */
5d66da3d 37 crclr cr0*4+so
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38 beqlr /* nothing to do? */
39 mtctr r8
40 mr r3,r6
411: dcbst 0,r3
42 addi r3,r3,128
43 bdnz 1b
44 sync
45 mtctr r8
461: icbi 0,r6
47 addi r6,r6,128
48 bdnz 1b
49 isync
bdceb6a0 50 li r3,0
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51 blr
52 .cfi_endproc
53V_FUNCTION_END(__kernel_sync_dicache)
54
55
56/*
57 * POWER5 version of __kernel_sync_dicache
58 */
59V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
60 .cfi_startproc
5d66da3d 61 crclr cr0*4+so
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62 sync
63 isync
bdceb6a0 64 li r3,0
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65 blr
66 .cfi_endproc
67V_FUNCTION_END(__kernel_sync_dicache_p5)