Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af | 25 | #include <linux/user.h> |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
14cf11af | 37 | |
80947e7c | 38 | #include <asm/emulated_ops.h> |
14cf11af PM |
39 | #include <asm/pgtable.h> |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/io.h> | |
86417780 PM |
43 | #include <asm/machdep.h> |
44 | #include <asm/rtas.h> | |
f7f6f4fe | 45 | #include <asm/pmc.h> |
dc1c1ca3 | 46 | #ifdef CONFIG_PPC32 |
14cf11af | 47 | #include <asm/reg.h> |
86417780 | 48 | #endif |
14cf11af PM |
49 | #ifdef CONFIG_PMAC_BACKLIGHT |
50 | #include <asm/backlight.h> | |
51 | #endif | |
dc1c1ca3 | 52 | #ifdef CONFIG_PPC64 |
86417780 | 53 | #include <asm/firmware.h> |
dc1c1ca3 | 54 | #include <asm/processor.h> |
dc1c1ca3 | 55 | #endif |
c0ce7d08 | 56 | #include <asm/kexec.h> |
16c57b36 | 57 | #include <asm/ppc-opcode.h> |
dc1c1ca3 | 58 | |
7dbb922c | 59 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
60 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
61 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
62 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
63 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
64 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
65 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
67 | |
68 | EXPORT_SYMBOL(__debugger); | |
69 | EXPORT_SYMBOL(__debugger_ipi); | |
70 | EXPORT_SYMBOL(__debugger_bpt); | |
71 | EXPORT_SYMBOL(__debugger_sstep); | |
72 | EXPORT_SYMBOL(__debugger_iabr_match); | |
73 | EXPORT_SYMBOL(__debugger_dabr_match); | |
74 | EXPORT_SYMBOL(__debugger_fault_handler); | |
75 | #endif | |
76 | ||
14cf11af PM |
77 | /* |
78 | * Trap & Exception support | |
79 | */ | |
80 | ||
6031d9d9 | 81 | #ifdef CONFIG_PMAC_BACKLIGHT |
82 | static void pmac_backlight_unblank(void) | |
83 | { | |
84 | mutex_lock(&pmac_backlight_mutex); | |
85 | if (pmac_backlight) { | |
86 | struct backlight_properties *props; | |
87 | ||
88 | props = &pmac_backlight->props; | |
89 | props->brightness = props->max_brightness; | |
90 | props->power = FB_BLANK_UNBLANK; | |
91 | backlight_update_status(pmac_backlight); | |
92 | } | |
93 | mutex_unlock(&pmac_backlight_mutex); | |
94 | } | |
95 | #else | |
96 | static inline void pmac_backlight_unblank(void) { } | |
97 | #endif | |
98 | ||
14cf11af PM |
99 | int die(const char *str, struct pt_regs *regs, long err) |
100 | { | |
34c2a14f | 101 | static struct { |
b8f87782 | 102 | raw_spinlock_t lock; |
34c2a14f | 103 | u32 lock_owner; |
104 | int lock_owner_depth; | |
105 | } die = { | |
b8f87782 | 106 | .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock), |
34c2a14f | 107 | .lock_owner = -1, |
108 | .lock_owner_depth = 0 | |
109 | }; | |
c0ce7d08 | 110 | static int die_counter; |
34c2a14f | 111 | unsigned long flags; |
14cf11af PM |
112 | |
113 | if (debugger(regs)) | |
114 | return 1; | |
115 | ||
293e4688 | 116 | oops_enter(); |
117 | ||
34c2a14f | 118 | if (die.lock_owner != raw_smp_processor_id()) { |
119 | console_verbose(); | |
b8f87782 | 120 | raw_spin_lock_irqsave(&die.lock, flags); |
34c2a14f | 121 | die.lock_owner = smp_processor_id(); |
122 | die.lock_owner_depth = 0; | |
123 | bust_spinlocks(1); | |
124 | if (machine_is(powermac)) | |
125 | pmac_backlight_unblank(); | |
126 | } else { | |
127 | local_save_flags(flags); | |
128 | } | |
5474c120 | 129 | |
34c2a14f | 130 | if (++die.lock_owner_depth < 3) { |
131 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 132 | #ifdef CONFIG_PREEMPT |
34c2a14f | 133 | printk("PREEMPT "); |
14cf11af PM |
134 | #endif |
135 | #ifdef CONFIG_SMP | |
34c2a14f | 136 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
137 | #endif |
138 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 139 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
140 | #endif |
141 | #ifdef CONFIG_NUMA | |
34c2a14f | 142 | printk("NUMA "); |
14cf11af | 143 | #endif |
ae7f4463 | 144 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 145 | |
66fcb105 AB |
146 | if (notify_die(DIE_OOPS, str, regs, err, 255, |
147 | SIGSEGV) == NOTIFY_STOP) | |
148 | return 1; | |
149 | ||
34c2a14f | 150 | print_modules(); |
151 | show_regs(regs); | |
152 | } else { | |
153 | printk("Recursive die() failure, output suppressed\n"); | |
154 | } | |
e8222502 | 155 | |
14cf11af | 156 | bust_spinlocks(0); |
34c2a14f | 157 | die.lock_owner = -1; |
bcdcd8e7 | 158 | add_taint(TAINT_DIE); |
b8f87782 | 159 | raw_spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 160 | |
c0ce7d08 DW |
161 | if (kexec_should_crash(current) || |
162 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 163 | crash_kexec(regs); |
c0ce7d08 | 164 | crash_kexec_secondary(regs); |
14cf11af PM |
165 | |
166 | if (in_interrupt()) | |
167 | panic("Fatal exception in interrupt"); | |
168 | ||
cea6a4ba | 169 | if (panic_on_oops) |
012c437d | 170 | panic("Fatal exception"); |
cea6a4ba | 171 | |
293e4688 | 172 | oops_exit(); |
14cf11af PM |
173 | do_exit(err); |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
25baa35b ON |
178 | void user_single_step_siginfo(struct task_struct *tsk, |
179 | struct pt_regs *regs, siginfo_t *info) | |
180 | { | |
181 | memset(info, 0, sizeof(*info)); | |
182 | info->si_signo = SIGTRAP; | |
183 | info->si_code = TRAP_TRACE; | |
184 | info->si_addr = (void __user *)regs->nip; | |
185 | } | |
186 | ||
14cf11af PM |
187 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
188 | { | |
189 | siginfo_t info; | |
d0c3d534 OJ |
190 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
191 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
192 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
193 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
194 | |
195 | if (!user_mode(regs)) { | |
196 | if (die("Exception in kernel mode", regs, signr)) | |
197 | return; | |
d0c3d534 OJ |
198 | } else if (show_unhandled_signals && |
199 | unhandled_signal(current, signr) && | |
200 | printk_ratelimit()) { | |
9f0b0793 | 201 | printk(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
d0c3d534 OJ |
202 | current->comm, current->pid, signr, |
203 | addr, regs->nip, regs->link, code); | |
204 | } | |
14cf11af PM |
205 | |
206 | memset(&info, 0, sizeof(info)); | |
207 | info.si_signo = signr; | |
208 | info.si_code = code; | |
209 | info.si_addr = (void __user *) addr; | |
210 | force_sig_info(signr, &info, current); | |
14cf11af PM |
211 | } |
212 | ||
213 | #ifdef CONFIG_PPC64 | |
214 | void system_reset_exception(struct pt_regs *regs) | |
215 | { | |
216 | /* See if any machine dependent calls */ | |
c902be71 AB |
217 | if (ppc_md.system_reset_exception) { |
218 | if (ppc_md.system_reset_exception(regs)) | |
219 | return; | |
220 | } | |
14cf11af | 221 | |
c0ce7d08 | 222 | #ifdef CONFIG_KEXEC |
104699c0 | 223 | cpumask_set_cpu(smp_processor_id(), &cpus_in_sr); |
c0ce7d08 DW |
224 | #endif |
225 | ||
8dad3f92 | 226 | die("System Reset", regs, SIGABRT); |
14cf11af | 227 | |
eac8392f DW |
228 | /* |
229 | * Some CPUs when released from the debugger will execute this path. | |
230 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
231 | * hung before entering the debugger it will return to the hung | |
232 | * state when exiting this function. This causes a problem in | |
233 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
234 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
235 | * here. If a kdump had not been initiated or we exit the debugger | |
236 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
237 | * will return after 5ms and the CPU returns to its previous state. | |
238 | */ | |
239 | crash_kexec_secondary(regs); | |
240 | ||
14cf11af PM |
241 | /* Must die if the interrupt is not recoverable */ |
242 | if (!(regs->msr & MSR_RI)) | |
243 | panic("Unrecoverable System Reset"); | |
244 | ||
245 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
246 | } | |
247 | #endif | |
248 | ||
249 | /* | |
250 | * I/O accesses can cause machine checks on powermacs. | |
251 | * Check if the NIP corresponds to the address of a sync | |
252 | * instruction for which there is an entry in the exception | |
253 | * table. | |
254 | * Note that the 601 only takes a machine check on TEA | |
255 | * (transfer error ack) signal assertion, and does not | |
256 | * set any of the top 16 bits of SRR1. | |
257 | * -- paulus. | |
258 | */ | |
259 | static inline int check_io_access(struct pt_regs *regs) | |
260 | { | |
68a64357 | 261 | #ifdef CONFIG_PPC32 |
14cf11af PM |
262 | unsigned long msr = regs->msr; |
263 | const struct exception_table_entry *entry; | |
264 | unsigned int *nip = (unsigned int *)regs->nip; | |
265 | ||
266 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
267 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
268 | /* | |
269 | * Check that it's a sync instruction, or somewhere | |
270 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
271 | * As the address is in the exception table | |
272 | * we should be able to read the instr there. | |
273 | * For the debug message, we look at the preceding | |
274 | * load or store. | |
275 | */ | |
276 | if (*nip == 0x60000000) /* nop */ | |
277 | nip -= 2; | |
278 | else if (*nip == 0x4c00012c) /* isync */ | |
279 | --nip; | |
280 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
281 | /* sync or twi */ | |
282 | unsigned int rb; | |
283 | ||
284 | --nip; | |
285 | rb = (*nip >> 11) & 0x1f; | |
286 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
287 | (*nip & 0x100)? "OUT to": "IN from", | |
288 | regs->gpr[rb] - _IO_BASE, nip); | |
289 | regs->msr |= MSR_RI; | |
290 | regs->nip = entry->fixup; | |
291 | return 1; | |
292 | } | |
293 | } | |
68a64357 | 294 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
295 | return 0; |
296 | } | |
297 | ||
172ae2e7 | 298 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
299 | /* On 4xx, the reason for the machine check or program exception |
300 | is in the ESR. */ | |
301 | #define get_reason(regs) ((regs)->dsisr) | |
302 | #ifndef CONFIG_FSL_BOOKE | |
303 | #define get_mc_reason(regs) ((regs)->dsisr) | |
304 | #else | |
fe04b112 | 305 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
306 | #endif |
307 | #define REASON_FP ESR_FP | |
308 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
309 | #define REASON_PRIVILEGED ESR_PPR | |
310 | #define REASON_TRAP ESR_PTR | |
311 | ||
312 | /* single-step stuff */ | |
313 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
314 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
315 | ||
316 | #else | |
317 | /* On non-4xx, the reason for the machine check or program | |
318 | exception is in the MSR. */ | |
319 | #define get_reason(regs) ((regs)->msr) | |
320 | #define get_mc_reason(regs) ((regs)->msr) | |
321 | #define REASON_FP 0x100000 | |
322 | #define REASON_ILLEGAL 0x80000 | |
323 | #define REASON_PRIVILEGED 0x40000 | |
324 | #define REASON_TRAP 0x20000 | |
325 | ||
326 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
327 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
328 | #endif | |
329 | ||
47c0bd1a BH |
330 | #if defined(CONFIG_4xx) |
331 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 332 | { |
1a6a4ffe | 333 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 334 | |
14cf11af PM |
335 | if (reason & ESR_IMCP) { |
336 | printk("Instruction"); | |
337 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
338 | } else | |
339 | printk("Data"); | |
340 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
345 | int machine_check_440A(struct pt_regs *regs) | |
346 | { | |
347 | unsigned long reason = get_mc_reason(regs); | |
348 | ||
14cf11af PM |
349 | printk("Machine check in kernel mode.\n"); |
350 | if (reason & ESR_IMCP){ | |
351 | printk("Instruction Synchronous Machine Check exception\n"); | |
352 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
353 | } | |
354 | else { | |
355 | u32 mcsr = mfspr(SPRN_MCSR); | |
356 | if (mcsr & MCSR_IB) | |
357 | printk("Instruction Read PLB Error\n"); | |
358 | if (mcsr & MCSR_DRB) | |
359 | printk("Data Read PLB Error\n"); | |
360 | if (mcsr & MCSR_DWB) | |
361 | printk("Data Write PLB Error\n"); | |
362 | if (mcsr & MCSR_TLBP) | |
363 | printk("TLB Parity Error\n"); | |
364 | if (mcsr & MCSR_ICP){ | |
365 | flush_instruction_cache(); | |
366 | printk("I-Cache Parity Error\n"); | |
367 | } | |
368 | if (mcsr & MCSR_DCSP) | |
369 | printk("D-Cache Search Parity Error\n"); | |
370 | if (mcsr & MCSR_DCFP) | |
371 | printk("D-Cache Flush Parity Error\n"); | |
372 | if (mcsr & MCSR_IMPE) | |
373 | printk("Machine Check exception is imprecise\n"); | |
374 | ||
375 | /* Clear MCSR */ | |
376 | mtspr(SPRN_MCSR, mcsr); | |
377 | } | |
47c0bd1a BH |
378 | return 0; |
379 | } | |
fc5e7097 DK |
380 | |
381 | int machine_check_47x(struct pt_regs *regs) | |
382 | { | |
383 | unsigned long reason = get_mc_reason(regs); | |
384 | u32 mcsr; | |
385 | ||
386 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
387 | if (reason & ESR_IMCP) { | |
388 | printk(KERN_ERR | |
389 | "Instruction Synchronous Machine Check exception\n"); | |
390 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
391 | return 0; | |
392 | } | |
393 | mcsr = mfspr(SPRN_MCSR); | |
394 | if (mcsr & MCSR_IB) | |
395 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
396 | if (mcsr & MCSR_DRB) | |
397 | printk(KERN_ERR "Data Read PLB Error\n"); | |
398 | if (mcsr & MCSR_DWB) | |
399 | printk(KERN_ERR "Data Write PLB Error\n"); | |
400 | if (mcsr & MCSR_TLBP) | |
401 | printk(KERN_ERR "TLB Parity Error\n"); | |
402 | if (mcsr & MCSR_ICP) { | |
403 | flush_instruction_cache(); | |
404 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
405 | } | |
406 | if (mcsr & MCSR_DCSP) | |
407 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
408 | if (mcsr & PPC47x_MCSR_GPR) | |
409 | printk(KERN_ERR "GPR Parity Error\n"); | |
410 | if (mcsr & PPC47x_MCSR_FPR) | |
411 | printk(KERN_ERR "FPR Parity Error\n"); | |
412 | if (mcsr & PPC47x_MCSR_IPR) | |
413 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
414 | ||
415 | /* Clear MCSR */ | |
416 | mtspr(SPRN_MCSR, mcsr); | |
417 | ||
418 | return 0; | |
419 | } | |
47c0bd1a | 420 | #elif defined(CONFIG_E500) |
fe04b112 SW |
421 | int machine_check_e500mc(struct pt_regs *regs) |
422 | { | |
423 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
424 | unsigned long reason = mcsr; | |
425 | int recoverable = 1; | |
426 | ||
427 | printk("Machine check in kernel mode.\n"); | |
428 | printk("Caused by (from MCSR=%lx): ", reason); | |
429 | ||
430 | if (reason & MCSR_MCP) | |
431 | printk("Machine Check Signal\n"); | |
432 | ||
433 | if (reason & MCSR_ICPERR) { | |
434 | printk("Instruction Cache Parity Error\n"); | |
435 | ||
436 | /* | |
437 | * This is recoverable by invalidating the i-cache. | |
438 | */ | |
439 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
440 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
441 | ; | |
442 | ||
443 | /* | |
444 | * This will generally be accompanied by an instruction | |
445 | * fetch error report -- only treat MCSR_IF as fatal | |
446 | * if it wasn't due to an L1 parity error. | |
447 | */ | |
448 | reason &= ~MCSR_IF; | |
449 | } | |
450 | ||
451 | if (reason & MCSR_DCPERR_MC) { | |
452 | printk("Data Cache Parity Error\n"); | |
453 | recoverable = 0; | |
454 | } | |
455 | ||
456 | if (reason & MCSR_L2MMU_MHIT) { | |
457 | printk("Hit on multiple TLB entries\n"); | |
458 | recoverable = 0; | |
459 | } | |
460 | ||
461 | if (reason & MCSR_NMI) | |
462 | printk("Non-maskable interrupt\n"); | |
463 | ||
464 | if (reason & MCSR_IF) { | |
465 | printk("Instruction Fetch Error Report\n"); | |
466 | recoverable = 0; | |
467 | } | |
468 | ||
469 | if (reason & MCSR_LD) { | |
470 | printk("Load Error Report\n"); | |
471 | recoverable = 0; | |
472 | } | |
473 | ||
474 | if (reason & MCSR_ST) { | |
475 | printk("Store Error Report\n"); | |
476 | recoverable = 0; | |
477 | } | |
478 | ||
479 | if (reason & MCSR_LDG) { | |
480 | printk("Guarded Load Error Report\n"); | |
481 | recoverable = 0; | |
482 | } | |
483 | ||
484 | if (reason & MCSR_TLBSYNC) | |
485 | printk("Simultaneous tlbsync operations\n"); | |
486 | ||
487 | if (reason & MCSR_BSL2_ERR) { | |
488 | printk("Level 2 Cache Error\n"); | |
489 | recoverable = 0; | |
490 | } | |
491 | ||
492 | if (reason & MCSR_MAV) { | |
493 | u64 addr; | |
494 | ||
495 | addr = mfspr(SPRN_MCAR); | |
496 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
497 | ||
498 | printk("Machine Check %s Address: %#llx\n", | |
499 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
500 | } | |
501 | ||
502 | mtspr(SPRN_MCSR, mcsr); | |
503 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
504 | } | |
505 | ||
47c0bd1a BH |
506 | int machine_check_e500(struct pt_regs *regs) |
507 | { | |
508 | unsigned long reason = get_mc_reason(regs); | |
509 | ||
14cf11af PM |
510 | printk("Machine check in kernel mode.\n"); |
511 | printk("Caused by (from MCSR=%lx): ", reason); | |
512 | ||
513 | if (reason & MCSR_MCP) | |
514 | printk("Machine Check Signal\n"); | |
515 | if (reason & MCSR_ICPERR) | |
516 | printk("Instruction Cache Parity Error\n"); | |
517 | if (reason & MCSR_DCP_PERR) | |
518 | printk("Data Cache Push Parity Error\n"); | |
519 | if (reason & MCSR_DCPERR) | |
520 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
521 | if (reason & MCSR_BUS_IAERR) |
522 | printk("Bus - Instruction Address Error\n"); | |
523 | if (reason & MCSR_BUS_RAERR) | |
524 | printk("Bus - Read Address Error\n"); | |
525 | if (reason & MCSR_BUS_WAERR) | |
526 | printk("Bus - Write Address Error\n"); | |
527 | if (reason & MCSR_BUS_IBERR) | |
528 | printk("Bus - Instruction Data Error\n"); | |
529 | if (reason & MCSR_BUS_RBERR) | |
530 | printk("Bus - Read Data Bus Error\n"); | |
531 | if (reason & MCSR_BUS_WBERR) | |
532 | printk("Bus - Read Data Bus Error\n"); | |
533 | if (reason & MCSR_BUS_IPERR) | |
534 | printk("Bus - Instruction Parity Error\n"); | |
535 | if (reason & MCSR_BUS_RPERR) | |
536 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
537 | |
538 | return 0; | |
539 | } | |
4490c06b KG |
540 | |
541 | int machine_check_generic(struct pt_regs *regs) | |
542 | { | |
543 | return 0; | |
544 | } | |
47c0bd1a BH |
545 | #elif defined(CONFIG_E200) |
546 | int machine_check_e200(struct pt_regs *regs) | |
547 | { | |
548 | unsigned long reason = get_mc_reason(regs); | |
549 | ||
14cf11af PM |
550 | printk("Machine check in kernel mode.\n"); |
551 | printk("Caused by (from MCSR=%lx): ", reason); | |
552 | ||
553 | if (reason & MCSR_MCP) | |
554 | printk("Machine Check Signal\n"); | |
555 | if (reason & MCSR_CP_PERR) | |
556 | printk("Cache Push Parity Error\n"); | |
557 | if (reason & MCSR_CPERR) | |
558 | printk("Cache Parity Error\n"); | |
559 | if (reason & MCSR_EXCP_ERR) | |
560 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
561 | if (reason & MCSR_BUS_IRERR) | |
562 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
563 | if (reason & MCSR_BUS_DRERR) | |
564 | printk("Bus - Read Bus Error on data load\n"); | |
565 | if (reason & MCSR_BUS_WRERR) | |
566 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
567 | |
568 | return 0; | |
569 | } | |
570 | #else | |
571 | int machine_check_generic(struct pt_regs *regs) | |
572 | { | |
573 | unsigned long reason = get_mc_reason(regs); | |
574 | ||
14cf11af PM |
575 | printk("Machine check in kernel mode.\n"); |
576 | printk("Caused by (from SRR1=%lx): ", reason); | |
577 | switch (reason & 0x601F0000) { | |
578 | case 0x80000: | |
579 | printk("Machine check signal\n"); | |
580 | break; | |
581 | case 0: /* for 601 */ | |
582 | case 0x40000: | |
583 | case 0x140000: /* 7450 MSS error and TEA */ | |
584 | printk("Transfer error ack signal\n"); | |
585 | break; | |
586 | case 0x20000: | |
587 | printk("Data parity error signal\n"); | |
588 | break; | |
589 | case 0x10000: | |
590 | printk("Address parity error signal\n"); | |
591 | break; | |
592 | case 0x20000000: | |
593 | printk("L1 Data Cache error\n"); | |
594 | break; | |
595 | case 0x40000000: | |
596 | printk("L1 Instruction Cache error\n"); | |
597 | break; | |
598 | case 0x00100000: | |
599 | printk("L2 data cache parity error\n"); | |
600 | break; | |
601 | default: | |
602 | printk("Unknown values in msr\n"); | |
603 | } | |
75918a4b OJ |
604 | return 0; |
605 | } | |
47c0bd1a | 606 | #endif /* everything else */ |
75918a4b OJ |
607 | |
608 | void machine_check_exception(struct pt_regs *regs) | |
609 | { | |
610 | int recover = 0; | |
611 | ||
89713ed1 AB |
612 | __get_cpu_var(irq_stat).mce_exceptions++; |
613 | ||
47c0bd1a BH |
614 | /* See if any machine dependent calls. In theory, we would want |
615 | * to call the CPU first, and call the ppc_md. one if the CPU | |
616 | * one returns a positive number. However there is existing code | |
617 | * that assumes the board gets a first chance, so let's keep it | |
618 | * that way for now and fix things later. --BenH. | |
619 | */ | |
75918a4b OJ |
620 | if (ppc_md.machine_check_exception) |
621 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
622 | else if (cur_cpu_spec->machine_check) |
623 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 624 | |
47c0bd1a | 625 | if (recover > 0) |
75918a4b OJ |
626 | return; |
627 | ||
75918a4b | 628 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
47c0bd1a BH |
629 | /* the qspan pci read routines can cause machine checks -- Cort |
630 | * | |
631 | * yuck !!! that totally needs to go away ! There are better ways | |
632 | * to deal with that than having a wart in the mcheck handler. | |
633 | * -- BenH | |
634 | */ | |
75918a4b OJ |
635 | bad_page_fault(regs, regs->dar, SIGBUS); |
636 | return; | |
637 | #endif | |
638 | ||
a443506b | 639 | if (debugger_fault_handler(regs)) |
75918a4b | 640 | return; |
75918a4b OJ |
641 | |
642 | if (check_io_access(regs)) | |
643 | return; | |
644 | ||
8dad3f92 | 645 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
646 | |
647 | /* Must die if the interrupt is not recoverable */ | |
648 | if (!(regs->msr & MSR_RI)) | |
649 | panic("Unrecoverable Machine check"); | |
650 | } | |
651 | ||
652 | void SMIException(struct pt_regs *regs) | |
653 | { | |
654 | die("System Management Interrupt", regs, SIGABRT); | |
655 | } | |
656 | ||
dc1c1ca3 | 657 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
658 | { |
659 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
660 | regs->nip, regs->msr, regs->trap); | |
661 | ||
662 | _exception(SIGTRAP, regs, 0, 0); | |
663 | } | |
664 | ||
dc1c1ca3 | 665 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
666 | { |
667 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
668 | 5, SIGTRAP) == NOTIFY_STOP) | |
669 | return; | |
670 | if (debugger_iabr_match(regs)) | |
671 | return; | |
672 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
673 | } | |
674 | ||
675 | void RunModeException(struct pt_regs *regs) | |
676 | { | |
677 | _exception(SIGTRAP, regs, 0, 0); | |
678 | } | |
679 | ||
8dad3f92 | 680 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af | 681 | { |
2538c2d0 | 682 | clear_single_step(regs); |
14cf11af PM |
683 | |
684 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
685 | 5, SIGTRAP) == NOTIFY_STOP) | |
686 | return; | |
687 | if (debugger_sstep(regs)) | |
688 | return; | |
689 | ||
690 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
691 | } | |
692 | ||
693 | /* | |
694 | * After we have successfully emulated an instruction, we have to | |
695 | * check if the instruction was being single-stepped, and if so, | |
696 | * pretend we got a single-step exception. This was pointed out | |
697 | * by Kumar Gala. -- paulus | |
698 | */ | |
8dad3f92 | 699 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 700 | { |
2538c2d0 P |
701 | if (single_stepping(regs)) |
702 | single_step_exception(regs); | |
14cf11af PM |
703 | } |
704 | ||
5fad293b | 705 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 706 | { |
5fad293b | 707 | int ret = 0; |
dc1c1ca3 SR |
708 | |
709 | /* Invalid operation */ | |
710 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 711 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
712 | |
713 | /* Overflow */ | |
714 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 715 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
716 | |
717 | /* Underflow */ | |
718 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 719 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
720 | |
721 | /* Divide by zero */ | |
722 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 723 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
724 | |
725 | /* Inexact result */ | |
726 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
727 | ret = FPE_FLTRES; |
728 | ||
729 | return ret; | |
730 | } | |
731 | ||
732 | static void parse_fpe(struct pt_regs *regs) | |
733 | { | |
734 | int code = 0; | |
735 | ||
736 | flush_fp_to_thread(current); | |
737 | ||
738 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
739 | |
740 | _exception(SIGFPE, regs, code, regs->nip); | |
741 | } | |
742 | ||
743 | /* | |
744 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
745 | * provide the PVR to user applications using the mfspr rd, PVR. |
746 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
747 | * memory access caused an access fault. Return zero on success. | |
748 | * | |
749 | * There are a couple of ways to do this, either "decode" the instruction | |
750 | * or directly match lots of bits. In this case, matching lots of | |
751 | * bits is faster and easier. | |
86417780 | 752 | * |
14cf11af | 753 | */ |
14cf11af PM |
754 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
755 | { | |
756 | u8 rT = (instword >> 21) & 0x1f; | |
757 | u8 rA = (instword >> 16) & 0x1f; | |
758 | u8 NB_RB = (instword >> 11) & 0x1f; | |
759 | u32 num_bytes; | |
760 | unsigned long EA; | |
761 | int pos = 0; | |
762 | ||
763 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 764 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
765 | if ((rT == rA) || (rT == NB_RB)) |
766 | return -EINVAL; | |
767 | ||
768 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
769 | ||
16c57b36 KG |
770 | switch (instword & PPC_INST_STRING_MASK) { |
771 | case PPC_INST_LSWX: | |
772 | case PPC_INST_STSWX: | |
14cf11af PM |
773 | EA += NB_RB; |
774 | num_bytes = regs->xer & 0x7f; | |
775 | break; | |
16c57b36 KG |
776 | case PPC_INST_LSWI: |
777 | case PPC_INST_STSWI: | |
14cf11af PM |
778 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
779 | break; | |
780 | default: | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | while (num_bytes != 0) | |
785 | { | |
786 | u8 val; | |
787 | u32 shift = 8 * (3 - (pos & 0x3)); | |
788 | ||
16c57b36 KG |
789 | switch ((instword & PPC_INST_STRING_MASK)) { |
790 | case PPC_INST_LSWX: | |
791 | case PPC_INST_LSWI: | |
14cf11af PM |
792 | if (get_user(val, (u8 __user *)EA)) |
793 | return -EFAULT; | |
794 | /* first time updating this reg, | |
795 | * zero it out */ | |
796 | if (pos == 0) | |
797 | regs->gpr[rT] = 0; | |
798 | regs->gpr[rT] |= val << shift; | |
799 | break; | |
16c57b36 KG |
800 | case PPC_INST_STSWI: |
801 | case PPC_INST_STSWX: | |
14cf11af PM |
802 | val = regs->gpr[rT] >> shift; |
803 | if (put_user(val, (u8 __user *)EA)) | |
804 | return -EFAULT; | |
805 | break; | |
806 | } | |
807 | /* move EA to next address */ | |
808 | EA += 1; | |
809 | num_bytes--; | |
810 | ||
811 | /* manage our position within the register */ | |
812 | if (++pos == 4) { | |
813 | pos = 0; | |
814 | if (++rT == 32) | |
815 | rT = 0; | |
816 | } | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
c3412dcb WS |
822 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
823 | { | |
824 | u32 ra,rs; | |
825 | unsigned long tmp; | |
826 | ||
827 | ra = (instword >> 16) & 0x1f; | |
828 | rs = (instword >> 21) & 0x1f; | |
829 | ||
830 | tmp = regs->gpr[rs]; | |
831 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
832 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
833 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
834 | regs->gpr[ra] = tmp; | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
c1469f13 KG |
839 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
840 | { | |
841 | u8 rT = (instword >> 21) & 0x1f; | |
842 | u8 rA = (instword >> 16) & 0x1f; | |
843 | u8 rB = (instword >> 11) & 0x1f; | |
844 | u8 BC = (instword >> 6) & 0x1f; | |
845 | u8 bit; | |
846 | unsigned long tmp; | |
847 | ||
848 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
849 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
850 | ||
851 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
14cf11af PM |
856 | static int emulate_instruction(struct pt_regs *regs) |
857 | { | |
858 | u32 instword; | |
859 | u32 rd; | |
860 | ||
fab5db97 | 861 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
862 | return -EINVAL; |
863 | CHECK_FULL_REGS(regs); | |
864 | ||
865 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
866 | return -EFAULT; | |
867 | ||
868 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 869 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 870 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
871 | rd = (instword >> 21) & 0x1f; |
872 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
873 | return 0; | |
874 | } | |
875 | ||
876 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 877 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 878 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 879 | return 0; |
80947e7c | 880 | } |
14cf11af PM |
881 | |
882 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 883 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 884 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
885 | unsigned long msk = 0xf0000000UL >> shift; |
886 | ||
eecff81d | 887 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
888 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
889 | regs->xer &= ~0xf0000000UL; | |
890 | return 0; | |
891 | } | |
892 | ||
893 | /* Emulate load/store string insn. */ | |
80947e7c | 894 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 895 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 896 | return emulate_string_inst(regs, instword); |
80947e7c | 897 | } |
14cf11af | 898 | |
c3412dcb | 899 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 900 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 901 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
902 | return emulate_popcntb_inst(regs, instword); |
903 | } | |
904 | ||
c1469f13 | 905 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 906 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 907 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
908 | return emulate_isel(regs, instword); |
909 | } | |
910 | ||
efcac658 AK |
911 | #ifdef CONFIG_PPC64 |
912 | /* Emulate the mfspr rD, DSCR. */ | |
913 | if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && | |
914 | cpu_has_feature(CPU_FTR_DSCR)) { | |
915 | PPC_WARN_EMULATED(mfdscr, regs); | |
916 | rd = (instword >> 21) & 0x1f; | |
917 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
918 | return 0; | |
919 | } | |
920 | /* Emulate the mtspr DSCR, rD. */ | |
921 | if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && | |
922 | cpu_has_feature(CPU_FTR_DSCR)) { | |
923 | PPC_WARN_EMULATED(mtdscr, regs); | |
924 | rd = (instword >> 21) & 0x1f; | |
925 | mtspr(SPRN_DSCR, regs->gpr[rd]); | |
926 | current->thread.dscr_inherit = 1; | |
927 | return 0; | |
928 | } | |
929 | #endif | |
930 | ||
14cf11af PM |
931 | return -EINVAL; |
932 | } | |
933 | ||
73c9ceab | 934 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 935 | { |
73c9ceab | 936 | return is_kernel_addr(addr); |
14cf11af PM |
937 | } |
938 | ||
8dad3f92 | 939 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
940 | { |
941 | unsigned int reason = get_reason(regs); | |
942 | extern int do_mathemu(struct pt_regs *regs); | |
943 | ||
aa42c69c | 944 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 945 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 946 | |
dc1c1ca3 SR |
947 | if (reason & REASON_FP) { |
948 | /* IEEE FP exception */ | |
949 | parse_fpe(regs); | |
8dad3f92 PM |
950 | return; |
951 | } | |
952 | if (reason & REASON_TRAP) { | |
ba797b28 JW |
953 | /* Debugger is first in line to stop recursive faults in |
954 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
955 | if (debugger_bpt(regs)) | |
956 | return; | |
957 | ||
14cf11af | 958 | /* trap exception */ |
dc1c1ca3 SR |
959 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
960 | == NOTIFY_STOP) | |
961 | return; | |
73c9ceab JF |
962 | |
963 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 964 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
965 | regs->nip += 4; |
966 | return; | |
967 | } | |
8dad3f92 PM |
968 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
969 | return; | |
970 | } | |
971 | ||
cd8a5673 PM |
972 | local_irq_enable(); |
973 | ||
04903a30 KG |
974 | #ifdef CONFIG_MATH_EMULATION |
975 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
976 | * but there seems to be a hardware bug on the 405GP (RevD) | |
977 | * that means ESR is sometimes set incorrectly - either to | |
978 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
979 | * hardware people - not sure if it can happen on any illegal | |
980 | * instruction or only on FP instructions, whether there is a | |
25985edc | 981 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
5fad293b KG |
982 | switch (do_mathemu(regs)) { |
983 | case 0: | |
04903a30 KG |
984 | emulate_single_step(regs); |
985 | return; | |
5fad293b KG |
986 | case 1: { |
987 | int code = 0; | |
988 | code = __parse_fpscr(current->thread.fpscr.val); | |
989 | _exception(SIGFPE, regs, code, regs->nip); | |
990 | return; | |
991 | } | |
992 | case -EFAULT: | |
993 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
994 | return; | |
04903a30 | 995 | } |
5fad293b | 996 | /* fall through on any other errors */ |
04903a30 KG |
997 | #endif /* CONFIG_MATH_EMULATION */ |
998 | ||
8dad3f92 PM |
999 | /* Try to emulate it if we should. */ |
1000 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1001 | switch (emulate_instruction(regs)) { |
1002 | case 0: | |
1003 | regs->nip += 4; | |
1004 | emulate_single_step(regs); | |
8dad3f92 | 1005 | return; |
14cf11af PM |
1006 | case -EFAULT: |
1007 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 1008 | return; |
14cf11af PM |
1009 | } |
1010 | } | |
8dad3f92 PM |
1011 | |
1012 | if (reason & REASON_PRIVILEGED) | |
1013 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1014 | else | |
1015 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
1016 | } |
1017 | ||
dc1c1ca3 | 1018 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1019 | { |
4393c4f6 | 1020 | int sig, code, fixed = 0; |
14cf11af | 1021 | |
e9370ae1 PM |
1022 | /* we don't implement logging of alignment exceptions */ |
1023 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1024 | fixed = fix_alignment(regs); | |
14cf11af PM |
1025 | |
1026 | if (fixed == 1) { | |
1027 | regs->nip += 4; /* skip over emulated instruction */ | |
1028 | emulate_single_step(regs); | |
1029 | return; | |
1030 | } | |
1031 | ||
dc1c1ca3 | 1032 | /* Operand address was bad */ |
14cf11af | 1033 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1034 | sig = SIGSEGV; |
1035 | code = SEGV_ACCERR; | |
1036 | } else { | |
1037 | sig = SIGBUS; | |
1038 | code = BUS_ADRALN; | |
14cf11af | 1039 | } |
4393c4f6 BH |
1040 | if (user_mode(regs)) |
1041 | _exception(sig, regs, code, regs->dar); | |
1042 | else | |
1043 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
1044 | } |
1045 | ||
1046 | void StackOverflow(struct pt_regs *regs) | |
1047 | { | |
1048 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1049 | current, regs->gpr[1]); | |
1050 | debugger(regs); | |
1051 | show_regs(regs); | |
1052 | panic("kernel stack overflow"); | |
1053 | } | |
1054 | ||
1055 | void nonrecoverable_exception(struct pt_regs *regs) | |
1056 | { | |
1057 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1058 | regs->nip, regs->msr); | |
1059 | debugger(regs); | |
1060 | die("nonrecoverable exception", regs, SIGKILL); | |
1061 | } | |
1062 | ||
1063 | void trace_syscall(struct pt_regs *regs) | |
1064 | { | |
1065 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 1066 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
1067 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
1068 | } | |
dc1c1ca3 | 1069 | |
dc1c1ca3 SR |
1070 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1071 | { | |
1072 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
1073 | "%lx at %lx\n", regs->trap, regs->nip); | |
1074 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
1075 | } | |
dc1c1ca3 SR |
1076 | |
1077 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1078 | { | |
dc1c1ca3 SR |
1079 | if (user_mode(regs)) { |
1080 | /* A user program has executed an altivec instruction, | |
1081 | but this kernel doesn't support altivec. */ | |
1082 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1083 | return; | |
1084 | } | |
6c4841c2 | 1085 | |
dc1c1ca3 SR |
1086 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1087 | "%lx at %lx\n", regs->trap, regs->nip); | |
1088 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
1089 | } |
1090 | ||
ce48b210 MN |
1091 | void vsx_unavailable_exception(struct pt_regs *regs) |
1092 | { | |
1093 | if (user_mode(regs)) { | |
1094 | /* A user program has executed an vsx instruction, | |
1095 | but this kernel doesn't support vsx. */ | |
1096 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1097 | return; | |
1098 | } | |
1099 | ||
1100 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1101 | "%lx at %lx\n", regs->trap, regs->nip); | |
1102 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1103 | } | |
1104 | ||
dc1c1ca3 SR |
1105 | void performance_monitor_exception(struct pt_regs *regs) |
1106 | { | |
89713ed1 AB |
1107 | __get_cpu_var(irq_stat).pmu_irqs++; |
1108 | ||
dc1c1ca3 SR |
1109 | perf_irq(regs); |
1110 | } | |
dc1c1ca3 | 1111 | |
8dad3f92 | 1112 | #ifdef CONFIG_8xx |
14cf11af PM |
1113 | void SoftwareEmulation(struct pt_regs *regs) |
1114 | { | |
1115 | extern int do_mathemu(struct pt_regs *); | |
1116 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 1117 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1118 | int errcode; |
5dd57a13 | 1119 | #endif |
14cf11af PM |
1120 | |
1121 | CHECK_FULL_REGS(regs); | |
1122 | ||
1123 | if (!user_mode(regs)) { | |
1124 | debugger(regs); | |
1125 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
1126 | } | |
1127 | ||
1128 | #ifdef CONFIG_MATH_EMULATION | |
1129 | errcode = do_mathemu(regs); | |
80947e7c | 1130 | if (errcode >= 0) |
eecff81d | 1131 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
1132 | |
1133 | switch (errcode) { | |
1134 | case 0: | |
1135 | emulate_single_step(regs); | |
1136 | return; | |
1137 | case 1: { | |
1138 | int code = 0; | |
1139 | code = __parse_fpscr(current->thread.fpscr.val); | |
1140 | _exception(SIGFPE, regs, code, regs->nip); | |
1141 | return; | |
1142 | } | |
1143 | case -EFAULT: | |
1144 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1145 | return; | |
1146 | default: | |
1147 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1148 | return; | |
1149 | } | |
1150 | ||
5dd57a13 | 1151 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1152 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1153 | if (errcode >= 0) |
eecff81d | 1154 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1155 | |
5fad293b KG |
1156 | switch (errcode) { |
1157 | case 0: | |
14cf11af | 1158 | emulate_single_step(regs); |
5fad293b KG |
1159 | return; |
1160 | case 1: | |
1161 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1162 | return; | |
1163 | case -EFAULT: | |
1164 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1165 | return; | |
1166 | } | |
5dd57a13 SW |
1167 | #else |
1168 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1169 | #endif |
14cf11af | 1170 | } |
8dad3f92 | 1171 | #endif /* CONFIG_8xx */ |
14cf11af | 1172 | |
172ae2e7 | 1173 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1174 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1175 | { | |
1176 | int changed = 0; | |
1177 | /* | |
1178 | * Determine the cause of the debug event, clear the | |
1179 | * event flags and send a trap to the handler. Torez | |
1180 | */ | |
1181 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1182 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1183 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1184 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1185 | #endif | |
1186 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1187 | 5); | |
1188 | changed |= 0x01; | |
1189 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1190 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1191 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1192 | 6); | |
1193 | changed |= 0x01; | |
1194 | } else if (debug_status & DBSR_IAC1) { | |
1195 | current->thread.dbcr0 &= ~DBCR0_IAC1; | |
1196 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | |
1197 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1198 | 1); | |
1199 | changed |= 0x01; | |
1200 | } else if (debug_status & DBSR_IAC2) { | |
1201 | current->thread.dbcr0 &= ~DBCR0_IAC2; | |
1202 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | |
1203 | 2); | |
1204 | changed |= 0x01; | |
1205 | } else if (debug_status & DBSR_IAC3) { | |
1206 | current->thread.dbcr0 &= ~DBCR0_IAC3; | |
1207 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | |
1208 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1209 | 3); | |
1210 | changed |= 0x01; | |
1211 | } else if (debug_status & DBSR_IAC4) { | |
1212 | current->thread.dbcr0 &= ~DBCR0_IAC4; | |
1213 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | |
1214 | 4); | |
1215 | changed |= 0x01; | |
1216 | } | |
1217 | /* | |
1218 | * At the point this routine was called, the MSR(DE) was turned off. | |
1219 | * Check all other debug flags and see if that bit needs to be turned | |
1220 | * back on or not. | |
1221 | */ | |
1222 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | |
1223 | regs->msr |= MSR_DE; | |
1224 | else | |
1225 | /* Make sure the IDM flag is off */ | |
1226 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1227 | ||
1228 | if (changed & 0x01) | |
1229 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | |
1230 | } | |
14cf11af | 1231 | |
f8279621 | 1232 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1233 | { |
3bffb652 DK |
1234 | current->thread.dbsr = debug_status; |
1235 | ||
ec097c84 RM |
1236 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1237 | * on server, it stops on the target of the branch. In order to simulate | |
1238 | * the server behaviour, we thus restart right away with a single step | |
1239 | * instead of stopping here when hitting a BT | |
1240 | */ | |
1241 | if (debug_status & DBSR_BT) { | |
1242 | regs->msr &= ~MSR_DE; | |
1243 | ||
1244 | /* Disable BT */ | |
1245 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1246 | /* Clear the BT event */ | |
1247 | mtspr(SPRN_DBSR, DBSR_BT); | |
1248 | ||
1249 | /* Do the single step trick only when coming from userspace */ | |
1250 | if (user_mode(regs)) { | |
1251 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1252 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1253 | regs->msr |= MSR_DE; | |
1254 | return; | |
1255 | } | |
1256 | ||
1257 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1258 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1259 | return; | |
1260 | } | |
1261 | if (debugger_sstep(regs)) | |
1262 | return; | |
1263 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1264 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1265 | |
1266 | /* Disable instruction completion */ | |
1267 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1268 | /* Clear the instruction completion event */ | |
1269 | mtspr(SPRN_DBSR, DBSR_IC); | |
1270 | ||
1271 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1272 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1273 | return; | |
1274 | } | |
1275 | ||
1276 | if (debugger_sstep(regs)) | |
1277 | return; | |
1278 | ||
d6a61bfc | 1279 | if (user_mode(regs)) { |
3bffb652 DK |
1280 | current->thread.dbcr0 &= ~DBCR0_IC; |
1281 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
1282 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, | |
1283 | current->thread.dbcr1)) | |
1284 | regs->msr |= MSR_DE; | |
1285 | else | |
1286 | /* Make sure the IDM bit is off */ | |
1287 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1288 | #endif | |
d6a61bfc | 1289 | } |
3bffb652 DK |
1290 | |
1291 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1292 | } else | |
1293 | handle_debug(regs, debug_status); | |
14cf11af | 1294 | } |
172ae2e7 | 1295 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1296 | |
1297 | #if !defined(CONFIG_TAU_INT) | |
1298 | void TAUException(struct pt_regs *regs) | |
1299 | { | |
1300 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1301 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1302 | } | |
1303 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1304 | |
1305 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1306 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1307 | { |
1308 | int err; | |
1309 | ||
14cf11af PM |
1310 | if (!user_mode(regs)) { |
1311 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1312 | " at %lx\n", regs->nip); | |
8dad3f92 | 1313 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1314 | } |
1315 | ||
dc1c1ca3 | 1316 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1317 | |
eecff81d | 1318 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1319 | err = emulate_altivec(regs); |
1320 | if (err == 0) { | |
1321 | regs->nip += 4; /* skip emulated instruction */ | |
1322 | emulate_single_step(regs); | |
1323 | return; | |
1324 | } | |
1325 | ||
1326 | if (err == -EFAULT) { | |
1327 | /* got an error reading the instruction */ | |
1328 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1329 | } else { | |
1330 | /* didn't recognize the instruction */ | |
1331 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1332 | if (printk_ratelimit()) | |
1333 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1334 | "in %s at %lx\n", current->comm, regs->nip); | |
1335 | current->thread.vscr.u[3] |= 0x10000; | |
1336 | } | |
1337 | } | |
1338 | #endif /* CONFIG_ALTIVEC */ | |
1339 | ||
ce48b210 MN |
1340 | #ifdef CONFIG_VSX |
1341 | void vsx_assist_exception(struct pt_regs *regs) | |
1342 | { | |
1343 | if (!user_mode(regs)) { | |
1344 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1345 | " at %lx\n", regs->nip); | |
1346 | die("Kernel VSX assist exception", regs, SIGILL); | |
1347 | } | |
1348 | ||
1349 | flush_vsx_to_thread(current); | |
1350 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1351 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1352 | } | |
1353 | #endif /* CONFIG_VSX */ | |
1354 | ||
14cf11af PM |
1355 | #ifdef CONFIG_FSL_BOOKE |
1356 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1357 | unsigned long error_code) | |
1358 | { | |
1359 | /* We treat cache locking instructions from the user | |
1360 | * as priv ops, in the future we could try to do | |
1361 | * something smarter | |
1362 | */ | |
1363 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1364 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1365 | return; | |
1366 | } | |
1367 | #endif /* CONFIG_FSL_BOOKE */ | |
1368 | ||
1369 | #ifdef CONFIG_SPE | |
1370 | void SPEFloatingPointException(struct pt_regs *regs) | |
1371 | { | |
6a800f36 | 1372 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1373 | unsigned long spefscr; |
1374 | int fpexc_mode; | |
1375 | int code = 0; | |
6a800f36 LY |
1376 | int err; |
1377 | ||
1378 | preempt_disable(); | |
1379 | if (regs->msr & MSR_SPE) | |
1380 | giveup_spe(current); | |
1381 | preempt_enable(); | |
14cf11af PM |
1382 | |
1383 | spefscr = current->thread.spefscr; | |
1384 | fpexc_mode = current->thread.fpexc_mode; | |
1385 | ||
14cf11af PM |
1386 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1387 | code = FPE_FLTOVF; | |
14cf11af PM |
1388 | } |
1389 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1390 | code = FPE_FLTUND; | |
14cf11af PM |
1391 | } |
1392 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1393 | code = FPE_FLTDIV; | |
1394 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1395 | code = FPE_FLTINV; | |
14cf11af PM |
1396 | } |
1397 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1398 | code = FPE_FLTRES; | |
1399 | ||
6a800f36 LY |
1400 | err = do_spe_mathemu(regs); |
1401 | if (err == 0) { | |
1402 | regs->nip += 4; /* skip emulated instruction */ | |
1403 | emulate_single_step(regs); | |
1404 | return; | |
1405 | } | |
1406 | ||
1407 | if (err == -EFAULT) { | |
1408 | /* got an error reading the instruction */ | |
1409 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1410 | } else if (err == -EINVAL) { | |
1411 | /* didn't recognize the instruction */ | |
1412 | printk(KERN_ERR "unrecognized spe instruction " | |
1413 | "in %s at %lx\n", current->comm, regs->nip); | |
1414 | } else { | |
1415 | _exception(SIGFPE, regs, code, regs->nip); | |
1416 | } | |
14cf11af | 1417 | |
14cf11af PM |
1418 | return; |
1419 | } | |
6a800f36 LY |
1420 | |
1421 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1422 | { | |
1423 | extern int speround_handler(struct pt_regs *regs); | |
1424 | int err; | |
1425 | ||
1426 | preempt_disable(); | |
1427 | if (regs->msr & MSR_SPE) | |
1428 | giveup_spe(current); | |
1429 | preempt_enable(); | |
1430 | ||
1431 | regs->nip -= 4; | |
1432 | err = speround_handler(regs); | |
1433 | if (err == 0) { | |
1434 | regs->nip += 4; /* skip emulated instruction */ | |
1435 | emulate_single_step(regs); | |
1436 | return; | |
1437 | } | |
1438 | ||
1439 | if (err == -EFAULT) { | |
1440 | /* got an error reading the instruction */ | |
1441 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1442 | } else if (err == -EINVAL) { | |
1443 | /* didn't recognize the instruction */ | |
1444 | printk(KERN_ERR "unrecognized spe instruction " | |
1445 | "in %s at %lx\n", current->comm, regs->nip); | |
1446 | } else { | |
1447 | _exception(SIGFPE, regs, 0, regs->nip); | |
1448 | return; | |
1449 | } | |
1450 | } | |
14cf11af PM |
1451 | #endif |
1452 | ||
dc1c1ca3 SR |
1453 | /* |
1454 | * We enter here if we get an unrecoverable exception, that is, one | |
1455 | * that happened at a point where the RI (recoverable interrupt) bit | |
1456 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1457 | * we therefore lost state by taking this exception. | |
1458 | */ | |
1459 | void unrecoverable_exception(struct pt_regs *regs) | |
1460 | { | |
1461 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1462 | regs->trap, regs->nip); | |
1463 | die("Unrecoverable exception", regs, SIGABRT); | |
1464 | } | |
dc1c1ca3 | 1465 | |
14cf11af PM |
1466 | #ifdef CONFIG_BOOKE_WDT |
1467 | /* | |
1468 | * Default handler for a Watchdog exception, | |
1469 | * spins until a reboot occurs | |
1470 | */ | |
1471 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1472 | { | |
1473 | /* Generic WatchdogHandler, implement your own */ | |
1474 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1475 | return; | |
1476 | } | |
1477 | ||
1478 | void WatchdogException(struct pt_regs *regs) | |
1479 | { | |
1480 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1481 | WatchdogHandler(regs); | |
1482 | } | |
1483 | #endif | |
dc1c1ca3 | 1484 | |
dc1c1ca3 SR |
1485 | /* |
1486 | * We enter here if we discover during exception entry that we are | |
1487 | * running in supervisor mode with a userspace value in the stack pointer. | |
1488 | */ | |
1489 | void kernel_bad_stack(struct pt_regs *regs) | |
1490 | { | |
1491 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1492 | regs->gpr[1], regs->nip); | |
1493 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1494 | } | |
14cf11af PM |
1495 | |
1496 | void __init trap_init(void) | |
1497 | { | |
1498 | } | |
80947e7c GU |
1499 | |
1500 | ||
1501 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1502 | ||
1503 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1504 | ||
1505 | struct ppc_emulated ppc_emulated = { | |
1506 | #ifdef CONFIG_ALTIVEC | |
1507 | WARN_EMULATED_SETUP(altivec), | |
1508 | #endif | |
1509 | WARN_EMULATED_SETUP(dcba), | |
1510 | WARN_EMULATED_SETUP(dcbz), | |
1511 | WARN_EMULATED_SETUP(fp_pair), | |
1512 | WARN_EMULATED_SETUP(isel), | |
1513 | WARN_EMULATED_SETUP(mcrxr), | |
1514 | WARN_EMULATED_SETUP(mfpvr), | |
1515 | WARN_EMULATED_SETUP(multiple), | |
1516 | WARN_EMULATED_SETUP(popcntb), | |
1517 | WARN_EMULATED_SETUP(spe), | |
1518 | WARN_EMULATED_SETUP(string), | |
1519 | WARN_EMULATED_SETUP(unaligned), | |
1520 | #ifdef CONFIG_MATH_EMULATION | |
1521 | WARN_EMULATED_SETUP(math), | |
1522 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1523 | WARN_EMULATED_SETUP(8xx), | |
1524 | #endif | |
1525 | #ifdef CONFIG_VSX | |
1526 | WARN_EMULATED_SETUP(vsx), | |
1527 | #endif | |
efcac658 AK |
1528 | #ifdef CONFIG_PPC64 |
1529 | WARN_EMULATED_SETUP(mfdscr), | |
1530 | WARN_EMULATED_SETUP(mtdscr), | |
1531 | #endif | |
80947e7c GU |
1532 | }; |
1533 | ||
1534 | u32 ppc_warn_emulated; | |
1535 | ||
1536 | void ppc_warn_emulated_print(const char *type) | |
1537 | { | |
1538 | if (printk_ratelimit()) | |
1539 | pr_warning("%s used emulated %s instruction\n", current->comm, | |
1540 | type); | |
1541 | } | |
1542 | ||
1543 | static int __init ppc_warn_emulated_init(void) | |
1544 | { | |
1545 | struct dentry *dir, *d; | |
1546 | unsigned int i; | |
1547 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1548 | ||
1549 | if (!powerpc_debugfs_root) | |
1550 | return -ENODEV; | |
1551 | ||
1552 | dir = debugfs_create_dir("emulated_instructions", | |
1553 | powerpc_debugfs_root); | |
1554 | if (!dir) | |
1555 | return -ENOMEM; | |
1556 | ||
1557 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1558 | &ppc_warn_emulated); | |
1559 | if (!d) | |
1560 | goto fail; | |
1561 | ||
1562 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1563 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1564 | (u32 *)&entries[i].val.counter); | |
1565 | if (!d) | |
1566 | goto fail; | |
1567 | } | |
1568 | ||
1569 | return 0; | |
1570 | ||
1571 | fail: | |
1572 | debugfs_remove_recursive(dir); | |
1573 | return -ENOMEM; | |
1574 | } | |
1575 | ||
1576 | device_initcall(ppc_warn_emulated_init); | |
1577 | ||
1578 | #endif /* CONFIG_PPC_EMULATED_STATS */ |