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powerpc: New macros for transactional memory support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
fe04b112 3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
14cf11af
PM		 4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14/*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
14cf11af
PM		 18#include <linux/errno.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
8dad3f92 24#include <linux/ptrace.h>
14cf11af 25#include <linux/user.h>
14cf11af 26#include <linux/interrupt.h>
14cf11af
PM		 27#include <linux/init.h>
28#include <linux/module.h>
8dad3f92 29#include <linux/prctl.h>
14cf11af
PM		 30#include <linux/delay.h>
31#include <linux/kprobes.h>
cc532915 32#include <linux/kexec.h>
5474c120 33#include <linux/backlight.h>
73c9ceab 34#include <linux/bug.h>
1eeb66a1 35#include <linux/kdebug.h>
80947e7c 36#include <linux/debugfs.h>
76462232 37#include <linux/ratelimit.h>
14cf11af 38
80947e7c 39#include <asm/emulated_ops.h>
14cf11af
PM		 40#include <asm/pgtable.h>
41#include <asm/uaccess.h>
14cf11af 42#include <asm/io.h>
86417780
PM		 43#include <asm/machdep.h>
44#include <asm/rtas.h>
f7f6f4fe 45#include <asm/pmc.h>
dc1c1ca3 46#ifdef CONFIG_PPC32
14cf11af 47#include <asm/reg.h>
86417780 48#endif
14cf11af
PM		 49#ifdef CONFIG_PMAC_BACKLIGHT
50#include <asm/backlight.h>
51#endif
dc1c1ca3 52#ifdef CONFIG_PPC64
86417780 53#include <asm/firmware.h>
dc1c1ca3 54#include <asm/processor.h>
dc1c1ca3 55#endif
c0ce7d08 56#include <asm/kexec.h>
16c57b36 57#include <asm/ppc-opcode.h>
cce1f106 58#include <asm/rio.h>
ebaeb5ae 59#include <asm/fadump.h>
ae3a197e
DH		 60#include <asm/switch_to.h>
61#include <asm/debug.h>
dc1c1ca3 62
7dbb922c 63#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
5be3492f
AB		 64int (*__debugger)(struct pt_regs *regs) __read_mostly;
65int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
66int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
67int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
68int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
9422de3e 69int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
5be3492f 70int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
14cf11af
PM		 71
72EXPORT_SYMBOL(__debugger);
73EXPORT_SYMBOL(__debugger_ipi);
74EXPORT_SYMBOL(__debugger_bpt);
75EXPORT_SYMBOL(__debugger_sstep);
76EXPORT_SYMBOL(__debugger_iabr_match);
9422de3e 77EXPORT_SYMBOL(__debugger_break_match);
14cf11af
PM		 78EXPORT_SYMBOL(__debugger_fault_handler);
79#endif
80
8b3c34cf
MN		 81/* Transactional Memory trap debug */
82#ifdef TM_DEBUG_SW
83#define TM_DEBUG(x...) printk(KERN_INFO x)
84#else
85#define TM_DEBUG(x...) do { } while(0)
86#endif
87
14cf11af
PM		 88/*
89 * Trap & Exception support
90 */
91
6031d9d9 92#ifdef CONFIG_PMAC_BACKLIGHT
93static void pmac_backlight_unblank(void)
94{
95 mutex_lock(&pmac_backlight_mutex);
96 if (pmac_backlight) {
97 struct backlight_properties *props;
98
99 props = &pmac_backlight->props;
100 props->brightness = props->max_brightness;
101 props->power = FB_BLANK_UNBLANK;
102 backlight_update_status(pmac_backlight);
103 }
104 mutex_unlock(&pmac_backlight_mutex);
105}
106#else
107static inline void pmac_backlight_unblank(void) { }
108#endif
109
760ca4dc
AB		 110static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
111static int die_owner = -1;
112static unsigned int die_nest_count;
113static int die_counter;
114
115static unsigned __kprobes long oops_begin(struct pt_regs *regs)
14cf11af 116{
760ca4dc 117 int cpu;
34c2a14f 118 unsigned long flags;
14cf11af
PM		 119
120 if (debugger(regs))
121 return 1;
122
293e4688 123 oops_enter();
124
760ca4dc
AB		 125 /* racy, but better than risking deadlock. */
126 raw_local_irq_save(flags);
127 cpu = smp_processor_id();
128 if (!arch_spin_trylock(&die_lock)) {
129 if (cpu == die_owner)
130 /* nested oops. should stop eventually */;
131 else
132 arch_spin_lock(&die_lock);
34c2a14f 133 }
760ca4dc
AB		 134 die_nest_count++;
135 die_owner = cpu;
136 console_verbose();
137 bust_spinlocks(1);
138 if (machine_is(powermac))
139 pmac_backlight_unblank();
140 return flags;
141}
e8222502 142
760ca4dc
AB		 143static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
144 int signr)
145{
14cf11af 146 bust_spinlocks(0);
760ca4dc 147 die_owner = -1;
bcdcd8e7 148 add_taint(TAINT_DIE);
760ca4dc 149 die_nest_count--;
58154c8c
AB		 150 oops_exit();
151 printk("\n");
760ca4dc
AB		 152 if (!die_nest_count)
153 /* Nest count reaches zero, release the lock. */
154 arch_spin_unlock(&die_lock);
155 raw_local_irq_restore(flags);
cc532915 156
ebaeb5ae
MS		 157 crash_fadump(regs, "die oops");
158
9b00ac06
AB		 159 /*
160 * A system reset (0x100) is a request to dump, so we always send
161 * it through the crashdump code.
162 */
163 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
cc532915 164 crash_kexec(regs);
9b00ac06
AB		 165
166 /*
167 * We aren't the primary crash CPU. We need to send it
168 * to a holding pattern to avoid it ending up in the panic
169 * code.
170 */
171 crash_kexec_secondary(regs);
172 }
14cf11af 173
760ca4dc
AB		 174 if (!signr)
175 return;
176
58154c8c
AB		 177 /*
178 * While our oops output is serialised by a spinlock, output
179 * from panic() called below can race and corrupt it. If we
180 * know we are going to panic, delay for 1 second so we have a
181 * chance to get clean backtraces from all CPUs that are oopsing.
182 */
183 if (in_interrupt() || panic_on_oops || !current->pid ||
184 is_global_init(current)) {
185 mdelay(MSEC_PER_SEC);
186 }
187
14cf11af
PM		 188 if (in_interrupt())
189 panic("Fatal exception in interrupt");
cea6a4ba 190 if (panic_on_oops)
012c437d 191 panic("Fatal exception");
760ca4dc
AB		 192 do_exit(signr);
193}
cea6a4ba 194
760ca4dc
AB		 195static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
196{
197 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
198#ifdef CONFIG_PREEMPT
199 printk("PREEMPT ");
200#endif
201#ifdef CONFIG_SMP
202 printk("SMP NR_CPUS=%d ", NR_CPUS);
203#endif
204#ifdef CONFIG_DEBUG_PAGEALLOC
205 printk("DEBUG_PAGEALLOC ");
206#endif
207#ifdef CONFIG_NUMA
208 printk("NUMA ");
209#endif
210 printk("%s\n", ppc_md.name ? ppc_md.name : "");
211
212 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
213 return 1;
214
215 print_modules();
216 show_regs(regs);
14cf11af
PM		 217
218 return 0;
219}
220
760ca4dc
AB		 221void die(const char *str, struct pt_regs *regs, long err)
222{
223 unsigned long flags = oops_begin(regs);
224
225 if (__die(str, regs, err))
226 err = 0;
227 oops_end(flags, regs, err);
228}
229
25baa35b
ON		 230void user_single_step_siginfo(struct task_struct *tsk,
231 struct pt_regs *regs, siginfo_t *info)
232{
233 memset(info, 0, sizeof(*info));
234 info->si_signo = SIGTRAP;
235 info->si_code = TRAP_TRACE;
236 info->si_addr = (void __user *)regs->nip;
237}
238
14cf11af
PM		 239void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
240{
241 siginfo_t info;
d0c3d534
OJ		 242 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
243 "at %08lx nip %08lx lr %08lx code %x\n";
244 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
245 "at %016lx nip %016lx lr %016lx code %x\n";
14cf11af
PM		 246
247 if (!user_mode(regs)) {
760ca4dc
AB		 248 die("Exception in kernel mode", regs, signr);
249 return;
250 }
251
252 if (show_unhandled_signals && unhandled_signal(current, signr)) {
76462232
CD		 253 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
254 current->comm, current->pid, signr,
255 addr, regs->nip, regs->link, code);
256 }
14cf11af 257
a3512b2d 258 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
9f2f79e3
BH		 259 local_irq_enable();
260
41ab5266 261 current->thread.trap_nr = code;
14cf11af
PM		 262 memset(&info, 0, sizeof(info));
263 info.si_signo = signr;
264 info.si_code = code;
265 info.si_addr = (void __user *) addr;
266 force_sig_info(signr, &info, current);
14cf11af
PM		 267}
268
269#ifdef CONFIG_PPC64
270void system_reset_exception(struct pt_regs *regs)
271{
272 /* See if any machine dependent calls */
c902be71
AB		 273 if (ppc_md.system_reset_exception) {
274 if (ppc_md.system_reset_exception(regs))
275 return;
276 }
14cf11af 277
8dad3f92 278 die("System Reset", regs, SIGABRT);
14cf11af
PM		 279
280 /* Must die if the interrupt is not recoverable */
281 if (!(regs->msr & MSR_RI))
282 panic("Unrecoverable System Reset");
283
284 /* What should we do here? We could issue a shutdown or hard reset. */
285}
286#endif
287
288/*
289 * I/O accesses can cause machine checks on powermacs.
290 * Check if the NIP corresponds to the address of a sync
291 * instruction for which there is an entry in the exception
292 * table.
293 * Note that the 601 only takes a machine check on TEA
294 * (transfer error ack) signal assertion, and does not
295 * set any of the top 16 bits of SRR1.
296 * -- paulus.
297 */
298static inline int check_io_access(struct pt_regs *regs)
299{
68a64357 300#ifdef CONFIG_PPC32
14cf11af
PM		 301 unsigned long msr = regs->msr;
302 const struct exception_table_entry *entry;
303 unsigned int *nip = (unsigned int *)regs->nip;
304
305 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
306 && (entry = search_exception_tables(regs->nip)) != NULL) {
307 /*
308 * Check that it's a sync instruction, or somewhere
309 * in the twi; isync; nop sequence that inb/inw/inl uses.
310 * As the address is in the exception table
311 * we should be able to read the instr there.
312 * For the debug message, we look at the preceding
313 * load or store.
314 */
315 if (*nip == 0x60000000) /* nop */
316 nip -= 2;
317 else if (*nip == 0x4c00012c) /* isync */
318 --nip;
319 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
320 /* sync or twi */
321 unsigned int rb;
322
323 --nip;
324 rb = (*nip >> 11) & 0x1f;
325 printk(KERN_DEBUG "%s bad port %lx at %p\n",
326 (*nip & 0x100)? "OUT to": "IN from",
327 regs->gpr[rb] - _IO_BASE, nip);
328 regs->msr |= MSR_RI;
329 regs->nip = entry->fixup;
330 return 1;
331 }
332 }
68a64357 333#endif /* CONFIG_PPC32 */
14cf11af
PM		 334 return 0;
335}
336
172ae2e7 337#ifdef CONFIG_PPC_ADV_DEBUG_REGS
14cf11af
PM		 338/* On 4xx, the reason for the machine check or program exception
339 is in the ESR. */
340#define get_reason(regs) ((regs)->dsisr)
341#ifndef CONFIG_FSL_BOOKE
342#define get_mc_reason(regs) ((regs)->dsisr)
343#else
fe04b112 344#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
14cf11af
PM		 345#endif
346#define REASON_FP ESR_FP
347#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
348#define REASON_PRIVILEGED ESR_PPR
349#define REASON_TRAP ESR_PTR
350
351/* single-step stuff */
352#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
353#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
354
355#else
356/* On non-4xx, the reason for the machine check or program
357 exception is in the MSR. */
358#define get_reason(regs) ((regs)->msr)
359#define get_mc_reason(regs) ((regs)->msr)
8b3c34cf 360#define REASON_TM 0x200000
14cf11af
PM		 361#define REASON_FP 0x100000
362#define REASON_ILLEGAL 0x80000
363#define REASON_PRIVILEGED 0x40000
364#define REASON_TRAP 0x20000
365
366#define single_stepping(regs) ((regs)->msr & MSR_SE)
367#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
368#endif
369
47c0bd1a
BH		 370#if defined(CONFIG_4xx)
371int machine_check_4xx(struct pt_regs *regs)
14cf11af 372{
1a6a4ffe 373 unsigned long reason = get_mc_reason(regs);
14cf11af 374
14cf11af
PM		 375 if (reason & ESR_IMCP) {
376 printk("Instruction");
377 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
378 } else
379 printk("Data");
380 printk(" machine check in kernel mode.\n");
47c0bd1a
BH		 381
382 return 0;
383}
384
385int machine_check_440A(struct pt_regs *regs)
386{
387 unsigned long reason = get_mc_reason(regs);
388
14cf11af
PM		 389 printk("Machine check in kernel mode.\n");
390 if (reason & ESR_IMCP){
391 printk("Instruction Synchronous Machine Check exception\n");
392 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
393 }
394 else {
395 u32 mcsr = mfspr(SPRN_MCSR);
396 if (mcsr & MCSR_IB)
397 printk("Instruction Read PLB Error\n");
398 if (mcsr & MCSR_DRB)
399 printk("Data Read PLB Error\n");
400 if (mcsr & MCSR_DWB)
401 printk("Data Write PLB Error\n");
402 if (mcsr & MCSR_TLBP)
403 printk("TLB Parity Error\n");
404 if (mcsr & MCSR_ICP){
405 flush_instruction_cache();
406 printk("I-Cache Parity Error\n");
407 }
408 if (mcsr & MCSR_DCSP)
409 printk("D-Cache Search Parity Error\n");
410 if (mcsr & MCSR_DCFP)
411 printk("D-Cache Flush Parity Error\n");
412 if (mcsr & MCSR_IMPE)
413 printk("Machine Check exception is imprecise\n");
414
415 /* Clear MCSR */
416 mtspr(SPRN_MCSR, mcsr);
417 }
47c0bd1a
BH		 418 return 0;
419}
fc5e7097
DK		 420
421int machine_check_47x(struct pt_regs *regs)
422{
423 unsigned long reason = get_mc_reason(regs);
424 u32 mcsr;
425
426 printk(KERN_ERR "Machine check in kernel mode.\n");
427 if (reason & ESR_IMCP) {
428 printk(KERN_ERR
429 "Instruction Synchronous Machine Check exception\n");
430 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
431 return 0;
432 }
433 mcsr = mfspr(SPRN_MCSR);
434 if (mcsr & MCSR_IB)
435 printk(KERN_ERR "Instruction Read PLB Error\n");
436 if (mcsr & MCSR_DRB)
437 printk(KERN_ERR "Data Read PLB Error\n");
438 if (mcsr & MCSR_DWB)
439 printk(KERN_ERR "Data Write PLB Error\n");
440 if (mcsr & MCSR_TLBP)
441 printk(KERN_ERR "TLB Parity Error\n");
442 if (mcsr & MCSR_ICP) {
443 flush_instruction_cache();
444 printk(KERN_ERR "I-Cache Parity Error\n");
445 }
446 if (mcsr & MCSR_DCSP)
447 printk(KERN_ERR "D-Cache Search Parity Error\n");
448 if (mcsr & PPC47x_MCSR_GPR)
449 printk(KERN_ERR "GPR Parity Error\n");
450 if (mcsr & PPC47x_MCSR_FPR)
451 printk(KERN_ERR "FPR Parity Error\n");
452 if (mcsr & PPC47x_MCSR_IPR)
453 printk(KERN_ERR "Machine Check exception is imprecise\n");
454
455 /* Clear MCSR */
456 mtspr(SPRN_MCSR, mcsr);
457
458 return 0;
459}
47c0bd1a 460#elif defined(CONFIG_E500)
fe04b112
SW		 461int machine_check_e500mc(struct pt_regs *regs)
462{
463 unsigned long mcsr = mfspr(SPRN_MCSR);
464 unsigned long reason = mcsr;
465 int recoverable = 1;
466
82a9a480 467 if (reason & MCSR_LD) {
cce1f106
SX		 468 recoverable = fsl_rio_mcheck_exception(regs);
469 if (recoverable == 1)
470 goto silent_out;
471 }
472
fe04b112
SW		 473 printk("Machine check in kernel mode.\n");
474 printk("Caused by (from MCSR=%lx): ", reason);
475
476 if (reason & MCSR_MCP)
477 printk("Machine Check Signal\n");
478
479 if (reason & MCSR_ICPERR) {
480 printk("Instruction Cache Parity Error\n");
481
482 /*
483 * This is recoverable by invalidating the i-cache.
484 */
485 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
486 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
487 ;
488
489 /*
490 * This will generally be accompanied by an instruction
491 * fetch error report -- only treat MCSR_IF as fatal
492 * if it wasn't due to an L1 parity error.
493 */
494 reason &= ~MCSR_IF;
495 }
496
497 if (reason & MCSR_DCPERR_MC) {
498 printk("Data Cache Parity Error\n");
37caf9f2
KG		 499
500 /*
501 * In write shadow mode we auto-recover from the error, but it
502 * may still get logged and cause a machine check. We should
503 * only treat the non-write shadow case as non-recoverable.
504 */
505 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
506 recoverable = 0;
fe04b112
SW		 507 }
508
509 if (reason & MCSR_L2MMU_MHIT) {
510 printk("Hit on multiple TLB entries\n");
511 recoverable = 0;
512 }
513
514 if (reason & MCSR_NMI)
515 printk("Non-maskable interrupt\n");
516
517 if (reason & MCSR_IF) {
518 printk("Instruction Fetch Error Report\n");
519 recoverable = 0;
520 }
521
522 if (reason & MCSR_LD) {
523 printk("Load Error Report\n");
524 recoverable = 0;
525 }
526
527 if (reason & MCSR_ST) {
528 printk("Store Error Report\n");
529 recoverable = 0;
530 }
531
532 if (reason & MCSR_LDG) {
533 printk("Guarded Load Error Report\n");
534 recoverable = 0;
535 }
536
537 if (reason & MCSR_TLBSYNC)
538 printk("Simultaneous tlbsync operations\n");
539
540 if (reason & MCSR_BSL2_ERR) {
541 printk("Level 2 Cache Error\n");
542 recoverable = 0;
543 }
544
545 if (reason & MCSR_MAV) {
546 u64 addr;
547
548 addr = mfspr(SPRN_MCAR);
549 addr |= (u64)mfspr(SPRN_MCARU) << 32;
550
551 printk("Machine Check %s Address: %#llx\n",
552 reason & MCSR_MEA ? "Effective" : "Physical", addr);
553 }
554
cce1f106 555silent_out:
fe04b112
SW		 556 mtspr(SPRN_MCSR, mcsr);
557 return mfspr(SPRN_MCSR) == 0 && recoverable;
558}
559
47c0bd1a
BH		 560int machine_check_e500(struct pt_regs *regs)
561{
562 unsigned long reason = get_mc_reason(regs);
563
cce1f106
SX		 564 if (reason & MCSR_BUS_RBERR) {
565 if (fsl_rio_mcheck_exception(regs))
566 return 1;
567 }
568
14cf11af
PM		 569 printk("Machine check in kernel mode.\n");
570 printk("Caused by (from MCSR=%lx): ", reason);
571
572 if (reason & MCSR_MCP)
573 printk("Machine Check Signal\n");
574 if (reason & MCSR_ICPERR)
575 printk("Instruction Cache Parity Error\n");
576 if (reason & MCSR_DCP_PERR)
577 printk("Data Cache Push Parity Error\n");
578 if (reason & MCSR_DCPERR)
579 printk("Data Cache Parity Error\n");
14cf11af
PM		 580 if (reason & MCSR_BUS_IAERR)
581 printk("Bus - Instruction Address Error\n");
582 if (reason & MCSR_BUS_RAERR)
583 printk("Bus - Read Address Error\n");
584 if (reason & MCSR_BUS_WAERR)
585 printk("Bus - Write Address Error\n");
586 if (reason & MCSR_BUS_IBERR)
587 printk("Bus - Instruction Data Error\n");
588 if (reason & MCSR_BUS_RBERR)
589 printk("Bus - Read Data Bus Error\n");
590 if (reason & MCSR_BUS_WBERR)
591 printk("Bus - Read Data Bus Error\n");
592 if (reason & MCSR_BUS_IPERR)
593 printk("Bus - Instruction Parity Error\n");
594 if (reason & MCSR_BUS_RPERR)
595 printk("Bus - Read Parity Error\n");
47c0bd1a
BH		 596
597 return 0;
598}
4490c06b
KG		 599
600int machine_check_generic(struct pt_regs *regs)
601{
602 return 0;
603}
47c0bd1a
BH		 604#elif defined(CONFIG_E200)
605int machine_check_e200(struct pt_regs *regs)
606{
607 unsigned long reason = get_mc_reason(regs);
608
14cf11af
PM		 609 printk("Machine check in kernel mode.\n");
610 printk("Caused by (from MCSR=%lx): ", reason);
611
612 if (reason & MCSR_MCP)
613 printk("Machine Check Signal\n");
614 if (reason & MCSR_CP_PERR)
615 printk("Cache Push Parity Error\n");
616 if (reason & MCSR_CPERR)
617 printk("Cache Parity Error\n");
618 if (reason & MCSR_EXCP_ERR)
619 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
620 if (reason & MCSR_BUS_IRERR)
621 printk("Bus - Read Bus Error on instruction fetch\n");
622 if (reason & MCSR_BUS_DRERR)
623 printk("Bus - Read Bus Error on data load\n");
624 if (reason & MCSR_BUS_WRERR)
625 printk("Bus - Write Bus Error on buffered store or cache line push\n");
47c0bd1a
BH		 626
627 return 0;
628}
629#else
630int machine_check_generic(struct pt_regs *regs)
631{
632 unsigned long reason = get_mc_reason(regs);
633
14cf11af
PM		 634 printk("Machine check in kernel mode.\n");
635 printk("Caused by (from SRR1=%lx): ", reason);
636 switch (reason & 0x601F0000) {
637 case 0x80000:
638 printk("Machine check signal\n");
639 break;
640 case 0: /* for 601 */
641 case 0x40000:
642 case 0x140000: /* 7450 MSS error and TEA */
643 printk("Transfer error ack signal\n");
644 break;
645 case 0x20000:
646 printk("Data parity error signal\n");
647 break;
648 case 0x10000:
649 printk("Address parity error signal\n");
650 break;
651 case 0x20000000:
652 printk("L1 Data Cache error\n");
653 break;
654 case 0x40000000:
655 printk("L1 Instruction Cache error\n");
656 break;
657 case 0x00100000:
658 printk("L2 data cache parity error\n");
659 break;
660 default:
661 printk("Unknown values in msr\n");
662 }
75918a4b
OJ		 663 return 0;
664}
47c0bd1a 665#endif /* everything else */
75918a4b
OJ		 666
667void machine_check_exception(struct pt_regs *regs)
668{
669 int recover = 0;
670
89713ed1
AB		 671 __get_cpu_var(irq_stat).mce_exceptions++;
672
47c0bd1a
BH		 673 /* See if any machine dependent calls. In theory, we would want
674 * to call the CPU first, and call the ppc_md. one if the CPU
675 * one returns a positive number. However there is existing code
676 * that assumes the board gets a first chance, so let's keep it
677 * that way for now and fix things later. --BenH.
678 */
75918a4b
OJ		 679 if (ppc_md.machine_check_exception)
680 recover = ppc_md.machine_check_exception(regs);
47c0bd1a
BH		 681 else if (cur_cpu_spec->machine_check)
682 recover = cur_cpu_spec->machine_check(regs);
75918a4b 683
47c0bd1a 684 if (recover > 0)
75918a4b
OJ		 685 return;
686
75918a4b 687#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
47c0bd1a
BH		 688 /* the qspan pci read routines can cause machine checks -- Cort
689 *
690 * yuck !!! that totally needs to go away ! There are better ways
691 * to deal with that than having a wart in the mcheck handler.
692 * -- BenH
693 */
75918a4b
OJ		 694 bad_page_fault(regs, regs->dar, SIGBUS);
695 return;
696#endif
697
a443506b 698 if (debugger_fault_handler(regs))
75918a4b 699 return;
75918a4b
OJ		 700
701 if (check_io_access(regs))
702 return;
703
8dad3f92 704 die("Machine check", regs, SIGBUS);
14cf11af
PM		 705
706 /* Must die if the interrupt is not recoverable */
707 if (!(regs->msr & MSR_RI))
708 panic("Unrecoverable Machine check");
709}
710
711void SMIException(struct pt_regs *regs)
712{
713 die("System Management Interrupt", regs, SIGABRT);
714}
715
dc1c1ca3 716void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 717{
718 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
719 regs->nip, regs->msr, regs->trap);
720
721 _exception(SIGTRAP, regs, 0, 0);
722}
723
dc1c1ca3 724void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 725{
726 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
727 5, SIGTRAP) == NOTIFY_STOP)
728 return;
729 if (debugger_iabr_match(regs))
730 return;
731 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
732}
733
734void RunModeException(struct pt_regs *regs)
735{
736 _exception(SIGTRAP, regs, 0, 0);
737}
738
8dad3f92 739void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af 740{
2538c2d0 741 clear_single_step(regs);
14cf11af
PM		 742
743 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
744 5, SIGTRAP) == NOTIFY_STOP)
745 return;
746 if (debugger_sstep(regs))
747 return;
748
749 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
750}
751
752/*
753 * After we have successfully emulated an instruction, we have to
754 * check if the instruction was being single-stepped, and if so,
755 * pretend we got a single-step exception. This was pointed out
756 * by Kumar Gala. -- paulus
757 */
8dad3f92 758static void emulate_single_step(struct pt_regs *regs)
14cf11af 759{
2538c2d0
P		 760 if (single_stepping(regs))
761 single_step_exception(regs);
14cf11af
PM		 762}
763
5fad293b 764static inline int __parse_fpscr(unsigned long fpscr)
dc1c1ca3 765{
5fad293b 766 int ret = 0;
dc1c1ca3
SR		 767
768 /* Invalid operation */
769 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
5fad293b 770 ret = FPE_FLTINV;
dc1c1ca3
SR		 771
772 /* Overflow */
773 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
5fad293b 774 ret = FPE_FLTOVF;
dc1c1ca3
SR		 775
776 /* Underflow */
777 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
5fad293b 778 ret = FPE_FLTUND;
dc1c1ca3
SR		 779
780 /* Divide by zero */
781 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
5fad293b 782 ret = FPE_FLTDIV;
dc1c1ca3
SR		 783
784 /* Inexact result */
785 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
5fad293b
KG		 786 ret = FPE_FLTRES;
787
788 return ret;
789}
790
791static void parse_fpe(struct pt_regs *regs)
792{
793 int code = 0;
794
795 flush_fp_to_thread(current);
796
797 code = __parse_fpscr(current->thread.fpscr.val);
dc1c1ca3
SR		 798
799 _exception(SIGFPE, regs, code, regs->nip);
800}
801
802/*
803 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 804 * provide the PVR to user applications using the mfspr rd, PVR.
805 * Return non-zero if we can't emulate, or -EFAULT if the associated
806 * memory access caused an access fault. Return zero on success.
807 *
808 * There are a couple of ways to do this, either "decode" the instruction
809 * or directly match lots of bits. In this case, matching lots of
810 * bits is faster and easier.
86417780 811 *
14cf11af 812 */
14cf11af
PM		 813static int emulate_string_inst(struct pt_regs *regs, u32 instword)
814{
815 u8 rT = (instword >> 21) & 0x1f;
816 u8 rA = (instword >> 16) & 0x1f;
817 u8 NB_RB = (instword >> 11) & 0x1f;
818 u32 num_bytes;
819 unsigned long EA;
820 int pos = 0;
821
822 /* Early out if we are an invalid form of lswx */
16c57b36 823 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
14cf11af
PM		 824 if ((rT == rA) || (rT == NB_RB))
825 return -EINVAL;
826
827 EA = (rA == 0) ? 0 : regs->gpr[rA];
828
16c57b36
KG		 829 switch (instword & PPC_INST_STRING_MASK) {
830 case PPC_INST_LSWX:
831 case PPC_INST_STSWX:
14cf11af
PM		 832 EA += NB_RB;
833 num_bytes = regs->xer & 0x7f;
834 break;
16c57b36
KG		 835 case PPC_INST_LSWI:
836 case PPC_INST_STSWI:
14cf11af
PM		 837 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
838 break;
839 default:
840 return -EINVAL;
841 }
842
843 while (num_bytes != 0)
844 {
845 u8 val;
846 u32 shift = 8 * (3 - (pos & 0x3));
847
16c57b36
KG		 848 switch ((instword & PPC_INST_STRING_MASK)) {
849 case PPC_INST_LSWX:
850 case PPC_INST_LSWI:
14cf11af
PM		 851 if (get_user(val, (u8 __user *)EA))
852 return -EFAULT;
853 /* first time updating this reg,
854 * zero it out */
855 if (pos == 0)
856 regs->gpr[rT] = 0;
857 regs->gpr[rT] |= val << shift;
858 break;
16c57b36
KG		 859 case PPC_INST_STSWI:
860 case PPC_INST_STSWX:
14cf11af
PM		 861 val = regs->gpr[rT] >> shift;
862 if (put_user(val, (u8 __user *)EA))
863 return -EFAULT;
864 break;
865 }
866 /* move EA to next address */
867 EA += 1;
868 num_bytes--;
869
870 /* manage our position within the register */
871 if (++pos == 4) {
872 pos = 0;
873 if (++rT == 32)
874 rT = 0;
875 }
876 }
877
878 return 0;
879}
880
c3412dcb
WS		 881static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
882{
883 u32 ra,rs;
884 unsigned long tmp;
885
886 ra = (instword >> 16) & 0x1f;
887 rs = (instword >> 21) & 0x1f;
888
889 tmp = regs->gpr[rs];
890 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
891 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
892 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
893 regs->gpr[ra] = tmp;
894
895 return 0;
896}
897
c1469f13
KG		 898static int emulate_isel(struct pt_regs *regs, u32 instword)
899{
900 u8 rT = (instword >> 21) & 0x1f;
901 u8 rA = (instword >> 16) & 0x1f;
902 u8 rB = (instword >> 11) & 0x1f;
903 u8 BC = (instword >> 6) & 0x1f;
904 u8 bit;
905 unsigned long tmp;
906
907 tmp = (rA == 0) ? 0 : regs->gpr[rA];
908 bit = (regs->ccr >> (31 - BC)) & 0x1;
909
910 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
911
912 return 0;
913}
914
14cf11af
PM		 915static int emulate_instruction(struct pt_regs *regs)
916{
917 u32 instword;
918 u32 rd;
919
fab5db97 920 if (!user_mode(regs) || (regs->msr & MSR_LE))
14cf11af
PM		 921 return -EINVAL;
922 CHECK_FULL_REGS(regs);
923
924 if (get_user(instword, (u32 __user *)(regs->nip)))
925 return -EFAULT;
926
927 /* Emulate the mfspr rD, PVR. */
16c57b36 928 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
eecff81d 929 PPC_WARN_EMULATED(mfpvr, regs);
14cf11af
PM		 930 rd = (instword >> 21) & 0x1f;
931 regs->gpr[rd] = mfspr(SPRN_PVR);
932 return 0;
933 }
934
935 /* Emulating the dcba insn is just a no-op. */
80947e7c 936 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
eecff81d 937 PPC_WARN_EMULATED(dcba, regs);
14cf11af 938 return 0;
80947e7c 939 }
14cf11af
PM		 940
941 /* Emulate the mcrxr insn. */
16c57b36 942 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
86417780 943 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 944 unsigned long msk = 0xf0000000UL >> shift;
945
eecff81d 946 PPC_WARN_EMULATED(mcrxr, regs);
14cf11af
PM		 947 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
948 regs->xer &= ~0xf0000000UL;
949 return 0;
950 }
951
952 /* Emulate load/store string insn. */
80947e7c 953 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
eecff81d 954 PPC_WARN_EMULATED(string, regs);
14cf11af 955 return emulate_string_inst(regs, instword);
80947e7c 956 }
14cf11af 957
c3412dcb 958 /* Emulate the popcntb (Population Count Bytes) instruction. */
16c57b36 959 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
eecff81d 960 PPC_WARN_EMULATED(popcntb, regs);
c3412dcb
WS		 961 return emulate_popcntb_inst(regs, instword);
962 }
963
c1469f13 964 /* Emulate isel (Integer Select) instruction */
16c57b36 965 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
eecff81d 966 PPC_WARN_EMULATED(isel, regs);
c1469f13
KG		 967 return emulate_isel(regs, instword);
968 }
969
efcac658
AK		 970#ifdef CONFIG_PPC64
971 /* Emulate the mfspr rD, DSCR. */
972 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
973 cpu_has_feature(CPU_FTR_DSCR)) {
974 PPC_WARN_EMULATED(mfdscr, regs);
975 rd = (instword >> 21) & 0x1f;
976 regs->gpr[rd] = mfspr(SPRN_DSCR);
977 return 0;
978 }
979 /* Emulate the mtspr DSCR, rD. */
980 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
981 cpu_has_feature(CPU_FTR_DSCR)) {
982 PPC_WARN_EMULATED(mtdscr, regs);
983 rd = (instword >> 21) & 0x1f;
00ca0de0 984 current->thread.dscr = regs->gpr[rd];
efcac658 985 current->thread.dscr_inherit = 1;
00ca0de0 986 mtspr(SPRN_DSCR, current->thread.dscr);
efcac658
AK		 987 return 0;
988 }
989#endif
990
14cf11af
PM		 991 return -EINVAL;
992}
993
73c9ceab 994int is_valid_bugaddr(unsigned long addr)
14cf11af 995{
73c9ceab 996 return is_kernel_addr(addr);
14cf11af
PM		 997}
998
8dad3f92 999void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 1000{
1001 unsigned int reason = get_reason(regs);
1002 extern int do_mathemu(struct pt_regs *regs);
1003
aa42c69c 1004 /* We can now get here via a FP Unavailable exception if the core
04903a30 1005 * has no FPU, in that case the reason flags will be 0 */
14cf11af 1006
dc1c1ca3
SR		 1007 if (reason & REASON_FP) {
1008 /* IEEE FP exception */
1009 parse_fpe(regs);
8dad3f92
PM		 1010 return;
1011 }
1012 if (reason & REASON_TRAP) {
ba797b28
JW		 1013 /* Debugger is first in line to stop recursive faults in
1014 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1015 if (debugger_bpt(regs))
1016 return;
1017
14cf11af 1018 /* trap exception */
dc1c1ca3
SR		 1019 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1020 == NOTIFY_STOP)
1021 return;
73c9ceab
JF		 1022
1023 if (!(regs->msr & MSR_PR) && /* not user-mode */
608e2619 1024 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
14cf11af
PM		 1025 regs->nip += 4;
1026 return;
1027 }
8dad3f92
PM		 1028 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1029 return;
1030 }
1031
a3512b2d
BH		 1032 /* We restore the interrupt state now */
1033 if (!arch_irq_disabled_regs(regs))
1034 local_irq_enable();
cd8a5673 1035
04903a30
KG		 1036#ifdef CONFIG_MATH_EMULATION
1037 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1038 * but there seems to be a hardware bug on the 405GP (RevD)
1039 * that means ESR is sometimes set incorrectly - either to
1040 * ESR_DST (!?) or 0. In the process of chasing this with the
1041 * hardware people - not sure if it can happen on any illegal
1042 * instruction or only on FP instructions, whether there is a
25985edc 1043 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
5fad293b
KG		 1044 switch (do_mathemu(regs)) {
1045 case 0:
04903a30
KG		 1046 emulate_single_step(regs);
1047 return;
5fad293b
KG		 1048 case 1: {
1049 int code = 0;
1050 code = __parse_fpscr(current->thread.fpscr.val);
1051 _exception(SIGFPE, regs, code, regs->nip);
1052 return;
1053 }
1054 case -EFAULT:
1055 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1056 return;
04903a30 1057 }
5fad293b 1058 /* fall through on any other errors */
04903a30
KG		 1059#endif /* CONFIG_MATH_EMULATION */
1060
8dad3f92
PM		 1061 /* Try to emulate it if we should. */
1062 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 1063 switch (emulate_instruction(regs)) {
1064 case 0:
1065 regs->nip += 4;
1066 emulate_single_step(regs);
8dad3f92 1067 return;
14cf11af
PM		 1068 case -EFAULT:
1069 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 1070 return;
14cf11af
PM		 1071 }
1072 }
8dad3f92
PM		 1073
1074 if (reason & REASON_PRIVILEGED)
1075 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1076 else
1077 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 1078}
1079
dc1c1ca3 1080void alignment_exception(struct pt_regs *regs)
14cf11af 1081{
4393c4f6 1082 int sig, code, fixed = 0;
14cf11af 1083
a3512b2d
BH		 1084 /* We restore the interrupt state now */
1085 if (!arch_irq_disabled_regs(regs))
1086 local_irq_enable();
1087
e9370ae1
PM		 1088 /* we don't implement logging of alignment exceptions */
1089 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1090 fixed = fix_alignment(regs);
14cf11af
PM		 1091
1092 if (fixed == 1) {
1093 regs->nip += 4; /* skip over emulated instruction */
1094 emulate_single_step(regs);
1095 return;
1096 }
1097
dc1c1ca3 1098 /* Operand address was bad */
14cf11af 1099 if (fixed == -EFAULT) {
4393c4f6
BH		 1100 sig = SIGSEGV;
1101 code = SEGV_ACCERR;
1102 } else {
1103 sig = SIGBUS;
1104 code = BUS_ADRALN;
14cf11af 1105 }
4393c4f6
BH		 1106 if (user_mode(regs))
1107 _exception(sig, regs, code, regs->dar);
1108 else
1109 bad_page_fault(regs, regs->dar, sig);
14cf11af
PM		 1110}
1111
1112void StackOverflow(struct pt_regs *regs)
1113{
1114 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1115 current, regs->gpr[1]);
1116 debugger(regs);
1117 show_regs(regs);
1118 panic("kernel stack overflow");
1119}
1120
1121void nonrecoverable_exception(struct pt_regs *regs)
1122{
1123 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1124 regs->nip, regs->msr);
1125 debugger(regs);
1126 die("nonrecoverable exception", regs, SIGKILL);
1127}
1128
1129void trace_syscall(struct pt_regs *regs)
1130{
1131 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
19c5870c 1132 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
14cf11af
PM		 1133 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1134}
dc1c1ca3 1135
dc1c1ca3
SR		 1136void kernel_fp_unavailable_exception(struct pt_regs *regs)
1137{
1138 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1139 "%lx at %lx\n", regs->trap, regs->nip);
1140 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1141}
dc1c1ca3
SR		 1142
1143void altivec_unavailable_exception(struct pt_regs *regs)
1144{
dc1c1ca3
SR		 1145 if (user_mode(regs)) {
1146 /* A user program has executed an altivec instruction,
1147 but this kernel doesn't support altivec. */
1148 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1149 return;
1150 }
6c4841c2 1151
dc1c1ca3
SR		 1152 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1153 "%lx at %lx\n", regs->trap, regs->nip);
1154 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 1155}
1156
ce48b210
MN		 1157void vsx_unavailable_exception(struct pt_regs *regs)
1158{
1159 if (user_mode(regs)) {
1160 /* A user program has executed an vsx instruction,
1161 but this kernel doesn't support vsx. */
1162 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1163 return;
1164 }
1165
1166 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1167 "%lx at %lx\n", regs->trap, regs->nip);
1168 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1169}
1170
dc1c1ca3
SR		 1171void performance_monitor_exception(struct pt_regs *regs)
1172{
89713ed1
AB		 1173 __get_cpu_var(irq_stat).pmu_irqs++;
1174
dc1c1ca3
SR		 1175 perf_irq(regs);
1176}
dc1c1ca3 1177
8dad3f92 1178#ifdef CONFIG_8xx
14cf11af
PM		 1179void SoftwareEmulation(struct pt_regs *regs)
1180{
1181 extern int do_mathemu(struct pt_regs *);
1182 extern int Soft_emulate_8xx(struct pt_regs *);
5dd57a13 1183#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 1184 int errcode;
5dd57a13 1185#endif
14cf11af
PM		 1186
1187 CHECK_FULL_REGS(regs);
1188
1189 if (!user_mode(regs)) {
1190 debugger(regs);
1191 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1192 }
1193
1194#ifdef CONFIG_MATH_EMULATION
1195 errcode = do_mathemu(regs);
80947e7c 1196 if (errcode >= 0)
eecff81d 1197 PPC_WARN_EMULATED(math, regs);
5fad293b
KG		 1198
1199 switch (errcode) {
1200 case 0:
1201 emulate_single_step(regs);
1202 return;
1203 case 1: {
1204 int code = 0;
1205 code = __parse_fpscr(current->thread.fpscr.val);
1206 _exception(SIGFPE, regs, code, regs->nip);
1207 return;
1208 }
1209 case -EFAULT:
1210 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1211 return;
1212 default:
1213 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1214 return;
1215 }
1216
5dd57a13 1217#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 1218 errcode = Soft_emulate_8xx(regs);
80947e7c 1219 if (errcode >= 0)
eecff81d 1220 PPC_WARN_EMULATED(8xx, regs);
80947e7c 1221
5fad293b
KG		 1222 switch (errcode) {
1223 case 0:
14cf11af 1224 emulate_single_step(regs);
5fad293b
KG		 1225 return;
1226 case 1:
1227 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1228 return;
1229 case -EFAULT:
1230 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1231 return;
1232 }
5dd57a13
SW		 1233#else
1234 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
5fad293b 1235#endif
14cf11af 1236}
8dad3f92 1237#endif /* CONFIG_8xx */
14cf11af 1238
172ae2e7 1239#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652
DK		 1240static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1241{
1242 int changed = 0;
1243 /*
1244 * Determine the cause of the debug event, clear the
1245 * event flags and send a trap to the handler. Torez
1246 */
1247 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1248 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1249#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1250 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1251#endif
1252 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1253 5);
1254 changed |= 0x01;
1255 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1256 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1257 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1258 6);
1259 changed |= 0x01;
1260 } else if (debug_status & DBSR_IAC1) {
1261 current->thread.dbcr0 &= ~DBCR0_IAC1;
1262 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1263 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1264 1);
1265 changed |= 0x01;
1266 } else if (debug_status & DBSR_IAC2) {
1267 current->thread.dbcr0 &= ~DBCR0_IAC2;
1268 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1269 2);
1270 changed |= 0x01;
1271 } else if (debug_status & DBSR_IAC3) {
1272 current->thread.dbcr0 &= ~DBCR0_IAC3;
1273 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1274 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1275 3);
1276 changed |= 0x01;
1277 } else if (debug_status & DBSR_IAC4) {
1278 current->thread.dbcr0 &= ~DBCR0_IAC4;
1279 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1280 4);
1281 changed |= 0x01;
1282 }
1283 /*
1284 * At the point this routine was called, the MSR(DE) was turned off.
1285 * Check all other debug flags and see if that bit needs to be turned
1286 * back on or not.
1287 */
1288 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1289 regs->msr |= MSR_DE;
1290 else
1291 /* Make sure the IDM flag is off */
1292 current->thread.dbcr0 &= ~DBCR0_IDM;
1293
1294 if (changed & 0x01)
1295 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1296}
14cf11af 1297
f8279621 1298void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
14cf11af 1299{
3bffb652
DK		 1300 current->thread.dbsr = debug_status;
1301
ec097c84
RM		 1302 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1303 * on server, it stops on the target of the branch. In order to simulate
1304 * the server behaviour, we thus restart right away with a single step
1305 * instead of stopping here when hitting a BT
1306 */
1307 if (debug_status & DBSR_BT) {
1308 regs->msr &= ~MSR_DE;
1309
1310 /* Disable BT */
1311 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1312 /* Clear the BT event */
1313 mtspr(SPRN_DBSR, DBSR_BT);
1314
1315 /* Do the single step trick only when coming from userspace */
1316 if (user_mode(regs)) {
1317 current->thread.dbcr0 &= ~DBCR0_BT;
1318 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1319 regs->msr |= MSR_DE;
1320 return;
1321 }
1322
1323 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1324 5, SIGTRAP) == NOTIFY_STOP) {
1325 return;
1326 }
1327 if (debugger_sstep(regs))
1328 return;
1329 } else if (debug_status & DBSR_IC) { /* Instruction complete */
14cf11af 1330 regs->msr &= ~MSR_DE;
f8279621
KG		 1331
1332 /* Disable instruction completion */
1333 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1334 /* Clear the instruction completion event */
1335 mtspr(SPRN_DBSR, DBSR_IC);
1336
1337 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1338 5, SIGTRAP) == NOTIFY_STOP) {
1339 return;
1340 }
1341
1342 if (debugger_sstep(regs))
1343 return;
1344
d6a61bfc 1345 if (user_mode(regs)) {
3bffb652 1346 current->thread.dbcr0 &= ~DBCR0_IC;
3bffb652
DK		 1347 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1348 current->thread.dbcr1))
1349 regs->msr |= MSR_DE;
1350 else
1351 /* Make sure the IDM bit is off */
1352 current->thread.dbcr0 &= ~DBCR0_IDM;
d6a61bfc 1353 }
3bffb652
DK		 1354
1355 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1356 } else
1357 handle_debug(regs, debug_status);
14cf11af 1358}
172ae2e7 1359#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
14cf11af
PM		 1360
1361#if !defined(CONFIG_TAU_INT)
1362void TAUException(struct pt_regs *regs)
1363{
1364 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1365 regs->nip, regs->msr, regs->trap, print_tainted());
1366}
1367#endif /* CONFIG_INT_TAU */
14cf11af
PM		 1368
1369#ifdef CONFIG_ALTIVEC
dc1c1ca3 1370void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 1371{
1372 int err;
1373
14cf11af
PM		 1374 if (!user_mode(regs)) {
1375 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1376 " at %lx\n", regs->nip);
8dad3f92 1377 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 1378 }
1379
dc1c1ca3 1380 flush_altivec_to_thread(current);
dc1c1ca3 1381
eecff81d 1382 PPC_WARN_EMULATED(altivec, regs);
14cf11af
PM		 1383 err = emulate_altivec(regs);
1384 if (err == 0) {
1385 regs->nip += 4; /* skip emulated instruction */
1386 emulate_single_step(regs);
1387 return;
1388 }
1389
1390 if (err == -EFAULT) {
1391 /* got an error reading the instruction */
1392 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1393 } else {
1394 /* didn't recognize the instruction */
1395 /* XXX quick hack for now: set the non-Java bit in the VSCR */
76462232
CD		 1396 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1397 "in %s at %lx\n", current->comm, regs->nip);
14cf11af
PM		 1398 current->thread.vscr.u[3] |= 0x10000;
1399 }
1400}
1401#endif /* CONFIG_ALTIVEC */
1402
ce48b210
MN		 1403#ifdef CONFIG_VSX
1404void vsx_assist_exception(struct pt_regs *regs)
1405{
1406 if (!user_mode(regs)) {
1407 printk(KERN_EMERG "VSX assist exception in kernel mode"
1408 " at %lx\n", regs->nip);
1409 die("Kernel VSX assist exception", regs, SIGILL);
1410 }
1411
1412 flush_vsx_to_thread(current);
1413 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1414 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1415}
1416#endif /* CONFIG_VSX */
1417
14cf11af
PM		 1418#ifdef CONFIG_FSL_BOOKE
1419void CacheLockingException(struct pt_regs *regs, unsigned long address,
1420 unsigned long error_code)
1421{
1422 /* We treat cache locking instructions from the user
1423 * as priv ops, in the future we could try to do
1424 * something smarter
1425 */
1426 if (error_code & (ESR_DLK|ESR_ILK))
1427 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1428 return;
1429}
1430#endif /* CONFIG_FSL_BOOKE */
1431
1432#ifdef CONFIG_SPE
1433void SPEFloatingPointException(struct pt_regs *regs)
1434{
6a800f36 1435 extern int do_spe_mathemu(struct pt_regs *regs);
14cf11af
PM		 1436 unsigned long spefscr;
1437 int fpexc_mode;
1438 int code = 0;
6a800f36
LY		 1439 int err;
1440
685659ee 1441 flush_spe_to_thread(current);
14cf11af
PM		 1442
1443 spefscr = current->thread.spefscr;
1444 fpexc_mode = current->thread.fpexc_mode;
1445
14cf11af
PM		 1446 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1447 code = FPE_FLTOVF;
14cf11af
PM		 1448 }
1449 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1450 code = FPE_FLTUND;
14cf11af
PM		 1451 }
1452 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1453 code = FPE_FLTDIV;
1454 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1455 code = FPE_FLTINV;
14cf11af
PM		 1456 }
1457 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1458 code = FPE_FLTRES;
1459
6a800f36
LY		 1460 err = do_spe_mathemu(regs);
1461 if (err == 0) {
1462 regs->nip += 4; /* skip emulated instruction */
1463 emulate_single_step(regs);
1464 return;
1465 }
1466
1467 if (err == -EFAULT) {
1468 /* got an error reading the instruction */
1469 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1470 } else if (err == -EINVAL) {
1471 /* didn't recognize the instruction */
1472 printk(KERN_ERR "unrecognized spe instruction "
1473 "in %s at %lx\n", current->comm, regs->nip);
1474 } else {
1475 _exception(SIGFPE, regs, code, regs->nip);
1476 }
14cf11af 1477
14cf11af
PM		 1478 return;
1479}
6a800f36
LY		 1480
1481void SPEFloatingPointRoundException(struct pt_regs *regs)
1482{
1483 extern int speround_handler(struct pt_regs *regs);
1484 int err;
1485
1486 preempt_disable();
1487 if (regs->msr & MSR_SPE)
1488 giveup_spe(current);
1489 preempt_enable();
1490
1491 regs->nip -= 4;
1492 err = speround_handler(regs);
1493 if (err == 0) {
1494 regs->nip += 4; /* skip emulated instruction */
1495 emulate_single_step(regs);
1496 return;
1497 }
1498
1499 if (err == -EFAULT) {
1500 /* got an error reading the instruction */
1501 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1502 } else if (err == -EINVAL) {
1503 /* didn't recognize the instruction */
1504 printk(KERN_ERR "unrecognized spe instruction "
1505 "in %s at %lx\n", current->comm, regs->nip);
1506 } else {
1507 _exception(SIGFPE, regs, 0, regs->nip);
1508 return;
1509 }
1510}
14cf11af
PM		 1511#endif
1512
dc1c1ca3
SR		 1513/*
1514 * We enter here if we get an unrecoverable exception, that is, one
1515 * that happened at a point where the RI (recoverable interrupt) bit
1516 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1517 * we therefore lost state by taking this exception.
1518 */
1519void unrecoverable_exception(struct pt_regs *regs)
1520{
1521 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1522 regs->trap, regs->nip);
1523 die("Unrecoverable exception", regs, SIGABRT);
1524}
dc1c1ca3 1525
1e18c17a 1526#if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
14cf11af
PM		 1527/*
1528 * Default handler for a Watchdog exception,
1529 * spins until a reboot occurs
1530 */
1531void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1532{
1533 /* Generic WatchdogHandler, implement your own */
1534 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1535 return;
1536}
1537
1538void WatchdogException(struct pt_regs *regs)
1539{
1540 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1541 WatchdogHandler(regs);
1542}
1543#endif
dc1c1ca3 1544
dc1c1ca3
SR		 1545/*
1546 * We enter here if we discover during exception entry that we are
1547 * running in supervisor mode with a userspace value in the stack pointer.
1548 */
1549void kernel_bad_stack(struct pt_regs *regs)
1550{
1551 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1552 regs->gpr[1], regs->nip);
1553 die("Bad kernel stack pointer", regs, SIGABRT);
1554}
14cf11af
PM		 1555
1556void __init trap_init(void)
1557{
1558}
80947e7c
GU		 1559
1560
1561#ifdef CONFIG_PPC_EMULATED_STATS
1562
1563#define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1564
1565struct ppc_emulated ppc_emulated = {
1566#ifdef CONFIG_ALTIVEC
1567 WARN_EMULATED_SETUP(altivec),
1568#endif
1569 WARN_EMULATED_SETUP(dcba),
1570 WARN_EMULATED_SETUP(dcbz),
1571 WARN_EMULATED_SETUP(fp_pair),
1572 WARN_EMULATED_SETUP(isel),
1573 WARN_EMULATED_SETUP(mcrxr),
1574 WARN_EMULATED_SETUP(mfpvr),
1575 WARN_EMULATED_SETUP(multiple),
1576 WARN_EMULATED_SETUP(popcntb),
1577 WARN_EMULATED_SETUP(spe),
1578 WARN_EMULATED_SETUP(string),
1579 WARN_EMULATED_SETUP(unaligned),
1580#ifdef CONFIG_MATH_EMULATION
1581 WARN_EMULATED_SETUP(math),
1582#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1583 WARN_EMULATED_SETUP(8xx),
1584#endif
1585#ifdef CONFIG_VSX
1586 WARN_EMULATED_SETUP(vsx),
1587#endif
efcac658
AK		 1588#ifdef CONFIG_PPC64
1589 WARN_EMULATED_SETUP(mfdscr),
1590 WARN_EMULATED_SETUP(mtdscr),
1591#endif
80947e7c
GU		 1592};
1593
1594u32 ppc_warn_emulated;
1595
1596void ppc_warn_emulated_print(const char *type)
1597{
76462232
CD		 1598 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1599 type);
80947e7c
GU		 1600}
1601
1602static int __init ppc_warn_emulated_init(void)
1603{
1604 struct dentry *dir, *d;
1605 unsigned int i;
1606 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1607
1608 if (!powerpc_debugfs_root)
1609 return -ENODEV;
1610
1611 dir = debugfs_create_dir("emulated_instructions",
1612 powerpc_debugfs_root);
1613 if (!dir)
1614 return -ENOMEM;
1615
1616 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1617 &ppc_warn_emulated);
1618 if (!d)
1619 goto fail;
1620
1621 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1622 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1623 (u32 *)&entries[i].val.counter);
1624 if (!d)
1625 goto fail;
1626 }
1627
1628 return 0;
1629
1630fail:
1631 debugfs_remove_recursive(dir);
1632 return -ENOMEM;
1633}
1634
1635device_initcall(ppc_warn_emulated_init);
1636
1637#endif /* CONFIG_PPC_EMULATED_STATS */
kernel source for telekom puls (alcatel/mediatek)