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[POWERPC] Added kprobes support to ppc32
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
14cf11af
PM		 17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/stddef.h>
22#include <linux/unistd.h>
8dad3f92 23#include <linux/ptrace.h>
14cf11af
PM		 24#include <linux/slab.h>
25#include <linux/user.h>
26#include <linux/a.out.h>
27#include <linux/interrupt.h>
14cf11af
PM		 28#include <linux/init.h>
29#include <linux/module.h>
8dad3f92 30#include <linux/prctl.h>
14cf11af
PM		 31#include <linux/delay.h>
32#include <linux/kprobes.h>
cc532915 33#include <linux/kexec.h>
5474c120 34#include <linux/backlight.h>
73c9ceab 35#include <linux/bug.h>
14cf11af 36
86417780 37#include <asm/kdebug.h>
14cf11af
PM		 38#include <asm/pgtable.h>
39#include <asm/uaccess.h>
40#include <asm/system.h>
41#include <asm/io.h>
86417780
PM		 42#include <asm/machdep.h>
43#include <asm/rtas.h>
f7f6f4fe 44#include <asm/pmc.h>
dc1c1ca3 45#ifdef CONFIG_PPC32
14cf11af 46#include <asm/reg.h>
86417780 47#endif
14cf11af
PM		 48#ifdef CONFIG_PMAC_BACKLIGHT
49#include <asm/backlight.h>
50#endif
dc1c1ca3 51#ifdef CONFIG_PPC64
86417780 52#include <asm/firmware.h>
dc1c1ca3 53#include <asm/processor.h>
dc1c1ca3 54#endif
c0ce7d08 55#include <asm/kexec.h>
dc1c1ca3 56
14cf11af
PM		 57#ifdef CONFIG_DEBUGGER
58int (*__debugger)(struct pt_regs *regs);
59int (*__debugger_ipi)(struct pt_regs *regs);
60int (*__debugger_bpt)(struct pt_regs *regs);
61int (*__debugger_sstep)(struct pt_regs *regs);
62int (*__debugger_iabr_match)(struct pt_regs *regs);
63int (*__debugger_dabr_match)(struct pt_regs *regs);
64int (*__debugger_fault_handler)(struct pt_regs *regs);
65
66EXPORT_SYMBOL(__debugger);
67EXPORT_SYMBOL(__debugger_ipi);
68EXPORT_SYMBOL(__debugger_bpt);
69EXPORT_SYMBOL(__debugger_sstep);
70EXPORT_SYMBOL(__debugger_iabr_match);
71EXPORT_SYMBOL(__debugger_dabr_match);
72EXPORT_SYMBOL(__debugger_fault_handler);
73#endif
74
e041c683 75ATOMIC_NOTIFIER_HEAD(powerpc_die_chain);
14cf11af
PM		 76
77int register_die_notifier(struct notifier_block *nb)
78{
e041c683
AS		 79 return atomic_notifier_chain_register(&powerpc_die_chain, nb);
80}
81EXPORT_SYMBOL(register_die_notifier);
14cf11af 82
e041c683
AS		 83int unregister_die_notifier(struct notifier_block *nb)
84{
85 return atomic_notifier_chain_unregister(&powerpc_die_chain, nb);
14cf11af 86}
e041c683 87EXPORT_SYMBOL(unregister_die_notifier);
14cf11af
PM		 88
89/*
90 * Trap & Exception support
91 */
92
93static DEFINE_SPINLOCK(die_lock);
94
95int die(const char *str, struct pt_regs *regs, long err)
96{
c0ce7d08 97 static int die_counter;
14cf11af
PM		 98
99 if (debugger(regs))
100 return 1;
101
102 console_verbose();
103 spin_lock_irq(&die_lock);
104 bust_spinlocks(1);
8dad3f92 105#ifdef CONFIG_PMAC_BACKLIGHT
5474c120
MH		 106 mutex_lock(&pmac_backlight_mutex);
107 if (machine_is(powermac) && pmac_backlight) {
108 struct backlight_properties *props;
109
110 down(&pmac_backlight->sem);
111 props = pmac_backlight->props;
112 props->brightness = props->max_brightness;
113 props->power = FB_BLANK_UNBLANK;
114 props->update_status(pmac_backlight);
115 up(&pmac_backlight->sem);
14cf11af 116 }
5474c120 117 mutex_unlock(&pmac_backlight_mutex);
14cf11af
PM		 118#endif
119 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
120#ifdef CONFIG_PREEMPT
121 printk("PREEMPT ");
14cf11af
PM		 122#endif
123#ifdef CONFIG_SMP
124 printk("SMP NR_CPUS=%d ", NR_CPUS);
14cf11af
PM		 125#endif
126#ifdef CONFIG_DEBUG_PAGEALLOC
127 printk("DEBUG_PAGEALLOC ");
14cf11af
PM		 128#endif
129#ifdef CONFIG_NUMA
130 printk("NUMA ");
14cf11af 131#endif
e8222502
BH		 132 printk("%s\n", ppc_md.name ? "" : ppc_md.name);
133
14cf11af
PM		 134 print_modules();
135 show_regs(regs);
136 bust_spinlocks(0);
c0ce7d08 137 spin_unlock_irq(&die_lock);
cc532915 138
c0ce7d08
DW		 139 if (kexec_should_crash(current) ||
140 kexec_sr_activated(smp_processor_id()))
cc532915 141 crash_kexec(regs);
c0ce7d08 142 crash_kexec_secondary(regs);
14cf11af
PM		 143
144 if (in_interrupt())
145 panic("Fatal exception in interrupt");
146
cea6a4ba 147 if (panic_on_oops)
012c437d 148 panic("Fatal exception");
cea6a4ba 149
14cf11af
PM		 150 do_exit(err);
151
152 return 0;
153}
154
155void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
156{
157 siginfo_t info;
158
159 if (!user_mode(regs)) {
160 if (die("Exception in kernel mode", regs, signr))
161 return;
162 }
163
164 memset(&info, 0, sizeof(info));
165 info.si_signo = signr;
166 info.si_code = code;
167 info.si_addr = (void __user *) addr;
168 force_sig_info(signr, &info, current);
169
170 /*
171 * Init gets no signals that it doesn't have a handler for.
172 * That's all very well, but if it has caused a synchronous
173 * exception and we ignore the resulting signal, it will just
174 * generate the same exception over and over again and we get
175 * nowhere. Better to kill it and let the kernel panic.
176 */
60bccbed 177 if (is_init(current)) {
14cf11af
PM		 178 __sighandler_t handler;
179
180 spin_lock_irq(&current->sighand->siglock);
181 handler = current->sighand->action[signr-1].sa.sa_handler;
182 spin_unlock_irq(&current->sighand->siglock);
183 if (handler == SIG_DFL) {
184 /* init has generated a synchronous exception
185 and it doesn't have a handler for the signal */
186 printk(KERN_CRIT "init has generated signal %d "
187 "but has no handler for it\n", signr);
188 do_exit(signr);
189 }
190 }
191}
192
193#ifdef CONFIG_PPC64
194void system_reset_exception(struct pt_regs *regs)
195{
196 /* See if any machine dependent calls */
c902be71
AB		 197 if (ppc_md.system_reset_exception) {
198 if (ppc_md.system_reset_exception(regs))
199 return;
200 }
14cf11af 201
c0ce7d08
DW		 202#ifdef CONFIG_KEXEC
203 cpu_set(smp_processor_id(), cpus_in_sr);
204#endif
205
8dad3f92 206 die("System Reset", regs, SIGABRT);
14cf11af 207
eac8392f
DW		 208 /*
209 * Some CPUs when released from the debugger will execute this path.
210 * These CPUs entered the debugger via a soft-reset. If the CPU was
211 * hung before entering the debugger it will return to the hung
212 * state when exiting this function. This causes a problem in
213 * kdump since the hung CPU(s) will not respond to the IPI sent
214 * from kdump. To prevent the problem we call crash_kexec_secondary()
215 * here. If a kdump had not been initiated or we exit the debugger
216 * with the "exit and recover" command (x) crash_kexec_secondary()
217 * will return after 5ms and the CPU returns to its previous state.
218 */
219 crash_kexec_secondary(regs);
220
14cf11af
PM		 221 /* Must die if the interrupt is not recoverable */
222 if (!(regs->msr & MSR_RI))
223 panic("Unrecoverable System Reset");
224
225 /* What should we do here? We could issue a shutdown or hard reset. */
226}
227#endif
228
229/*
230 * I/O accesses can cause machine checks on powermacs.
231 * Check if the NIP corresponds to the address of a sync
232 * instruction for which there is an entry in the exception
233 * table.
234 * Note that the 601 only takes a machine check on TEA
235 * (transfer error ack) signal assertion, and does not
236 * set any of the top 16 bits of SRR1.
237 * -- paulus.
238 */
239static inline int check_io_access(struct pt_regs *regs)
240{
68a64357 241#ifdef CONFIG_PPC32
14cf11af
PM		 242 unsigned long msr = regs->msr;
243 const struct exception_table_entry *entry;
244 unsigned int *nip = (unsigned int *)regs->nip;
245
246 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
247 && (entry = search_exception_tables(regs->nip)) != NULL) {
248 /*
249 * Check that it's a sync instruction, or somewhere
250 * in the twi; isync; nop sequence that inb/inw/inl uses.
251 * As the address is in the exception table
252 * we should be able to read the instr there.
253 * For the debug message, we look at the preceding
254 * load or store.
255 */
256 if (*nip == 0x60000000) /* nop */
257 nip -= 2;
258 else if (*nip == 0x4c00012c) /* isync */
259 --nip;
260 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
261 /* sync or twi */
262 unsigned int rb;
263
264 --nip;
265 rb = (*nip >> 11) & 0x1f;
266 printk(KERN_DEBUG "%s bad port %lx at %p\n",
267 (*nip & 0x100)? "OUT to": "IN from",
268 regs->gpr[rb] - _IO_BASE, nip);
269 regs->msr |= MSR_RI;
270 regs->nip = entry->fixup;
271 return 1;
272 }
273 }
68a64357 274#endif /* CONFIG_PPC32 */
14cf11af
PM		 275 return 0;
276}
277
278#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
279/* On 4xx, the reason for the machine check or program exception
280 is in the ESR. */
281#define get_reason(regs) ((regs)->dsisr)
282#ifndef CONFIG_FSL_BOOKE
283#define get_mc_reason(regs) ((regs)->dsisr)
284#else
285#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
286#endif
287#define REASON_FP ESR_FP
288#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
289#define REASON_PRIVILEGED ESR_PPR
290#define REASON_TRAP ESR_PTR
291
292/* single-step stuff */
293#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
294#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
295
296#else
297/* On non-4xx, the reason for the machine check or program
298 exception is in the MSR. */
299#define get_reason(regs) ((regs)->msr)
300#define get_mc_reason(regs) ((regs)->msr)
301#define REASON_FP 0x100000
302#define REASON_ILLEGAL 0x80000
303#define REASON_PRIVILEGED 0x40000
304#define REASON_TRAP 0x20000
305
306#define single_stepping(regs) ((regs)->msr & MSR_SE)
307#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
308#endif
309
310/*
311 * This is "fall-back" implementation for configurations
312 * which don't provide platform-specific machine check info
313 */
314void __attribute__ ((weak))
315platform_machine_check(struct pt_regs *regs)
316{
317}
318
dc1c1ca3 319void machine_check_exception(struct pt_regs *regs)
14cf11af 320{
14cf11af 321 int recover = 0;
1a6a4ffe 322 unsigned long reason = get_mc_reason(regs);
14cf11af
PM		 323
324 /* See if any machine dependent calls */
325 if (ppc_md.machine_check_exception)
326 recover = ppc_md.machine_check_exception(regs);
327
328 if (recover)
329 return;
14cf11af
PM		 330
331 if (user_mode(regs)) {
332 regs->msr |= MSR_RI;
333 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
334 return;
335 }
336
337#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
338 /* the qspan pci read routines can cause machine checks -- Cort */
339 bad_page_fault(regs, regs->dar, SIGBUS);
340 return;
341#endif
342
343 if (debugger_fault_handler(regs)) {
344 regs->msr |= MSR_RI;
345 return;
346 }
347
348 if (check_io_access(regs))
349 return;
350
351#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
352 if (reason & ESR_IMCP) {
353 printk("Instruction");
354 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
355 } else
356 printk("Data");
357 printk(" machine check in kernel mode.\n");
358#elif defined(CONFIG_440A)
359 printk("Machine check in kernel mode.\n");
360 if (reason & ESR_IMCP){
361 printk("Instruction Synchronous Machine Check exception\n");
362 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
363 }
364 else {
365 u32 mcsr = mfspr(SPRN_MCSR);
366 if (mcsr & MCSR_IB)
367 printk("Instruction Read PLB Error\n");
368 if (mcsr & MCSR_DRB)
369 printk("Data Read PLB Error\n");
370 if (mcsr & MCSR_DWB)
371 printk("Data Write PLB Error\n");
372 if (mcsr & MCSR_TLBP)
373 printk("TLB Parity Error\n");
374 if (mcsr & MCSR_ICP){
375 flush_instruction_cache();
376 printk("I-Cache Parity Error\n");
377 }
378 if (mcsr & MCSR_DCSP)
379 printk("D-Cache Search Parity Error\n");
380 if (mcsr & MCSR_DCFP)
381 printk("D-Cache Flush Parity Error\n");
382 if (mcsr & MCSR_IMPE)
383 printk("Machine Check exception is imprecise\n");
384
385 /* Clear MCSR */
386 mtspr(SPRN_MCSR, mcsr);
387 }
388#elif defined (CONFIG_E500)
389 printk("Machine check in kernel mode.\n");
390 printk("Caused by (from MCSR=%lx): ", reason);
391
392 if (reason & MCSR_MCP)
393 printk("Machine Check Signal\n");
394 if (reason & MCSR_ICPERR)
395 printk("Instruction Cache Parity Error\n");
396 if (reason & MCSR_DCP_PERR)
397 printk("Data Cache Push Parity Error\n");
398 if (reason & MCSR_DCPERR)
399 printk("Data Cache Parity Error\n");
400 if (reason & MCSR_GL_CI)
401 printk("Guarded Load or Cache-Inhibited stwcx.\n");
402 if (reason & MCSR_BUS_IAERR)
403 printk("Bus - Instruction Address Error\n");
404 if (reason & MCSR_BUS_RAERR)
405 printk("Bus - Read Address Error\n");
406 if (reason & MCSR_BUS_WAERR)
407 printk("Bus - Write Address Error\n");
408 if (reason & MCSR_BUS_IBERR)
409 printk("Bus - Instruction Data Error\n");
410 if (reason & MCSR_BUS_RBERR)
411 printk("Bus - Read Data Bus Error\n");
412 if (reason & MCSR_BUS_WBERR)
413 printk("Bus - Read Data Bus Error\n");
414 if (reason & MCSR_BUS_IPERR)
415 printk("Bus - Instruction Parity Error\n");
416 if (reason & MCSR_BUS_RPERR)
417 printk("Bus - Read Parity Error\n");
418#elif defined (CONFIG_E200)
419 printk("Machine check in kernel mode.\n");
420 printk("Caused by (from MCSR=%lx): ", reason);
421
422 if (reason & MCSR_MCP)
423 printk("Machine Check Signal\n");
424 if (reason & MCSR_CP_PERR)
425 printk("Cache Push Parity Error\n");
426 if (reason & MCSR_CPERR)
427 printk("Cache Parity Error\n");
428 if (reason & MCSR_EXCP_ERR)
429 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
430 if (reason & MCSR_BUS_IRERR)
431 printk("Bus - Read Bus Error on instruction fetch\n");
432 if (reason & MCSR_BUS_DRERR)
433 printk("Bus - Read Bus Error on data load\n");
434 if (reason & MCSR_BUS_WRERR)
435 printk("Bus - Write Bus Error on buffered store or cache line push\n");
436#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
437 printk("Machine check in kernel mode.\n");
438 printk("Caused by (from SRR1=%lx): ", reason);
439 switch (reason & 0x601F0000) {
440 case 0x80000:
441 printk("Machine check signal\n");
442 break;
443 case 0: /* for 601 */
444 case 0x40000:
445 case 0x140000: /* 7450 MSS error and TEA */
446 printk("Transfer error ack signal\n");
447 break;
448 case 0x20000:
449 printk("Data parity error signal\n");
450 break;
451 case 0x10000:
452 printk("Address parity error signal\n");
453 break;
454 case 0x20000000:
455 printk("L1 Data Cache error\n");
456 break;
457 case 0x40000000:
458 printk("L1 Instruction Cache error\n");
459 break;
460 case 0x00100000:
461 printk("L2 data cache parity error\n");
462 break;
463 default:
464 printk("Unknown values in msr\n");
465 }
466#endif /* CONFIG_4xx */
467
468 /*
469 * Optional platform-provided routine to print out
470 * additional info, e.g. bus error registers.
471 */
472 platform_machine_check(regs);
14cf11af
PM		 473
474 if (debugger_fault_handler(regs))
475 return;
8dad3f92 476 die("Machine check", regs, SIGBUS);
14cf11af
PM		 477
478 /* Must die if the interrupt is not recoverable */
479 if (!(regs->msr & MSR_RI))
480 panic("Unrecoverable Machine check");
481}
482
483void SMIException(struct pt_regs *regs)
484{
485 die("System Management Interrupt", regs, SIGABRT);
486}
487
dc1c1ca3 488void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 489{
490 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
491 regs->nip, regs->msr, regs->trap);
492
493 _exception(SIGTRAP, regs, 0, 0);
494}
495
dc1c1ca3 496void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 497{
498 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
499 5, SIGTRAP) == NOTIFY_STOP)
500 return;
501 if (debugger_iabr_match(regs))
502 return;
503 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
504}
505
506void RunModeException(struct pt_regs *regs)
507{
508 _exception(SIGTRAP, regs, 0, 0);
509}
510
8dad3f92 511void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af
PM		 512{
513 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
514
515 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
516 5, SIGTRAP) == NOTIFY_STOP)
517 return;
518 if (debugger_sstep(regs))
519 return;
520
521 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
522}
523
524/*
525 * After we have successfully emulated an instruction, we have to
526 * check if the instruction was being single-stepped, and if so,
527 * pretend we got a single-step exception. This was pointed out
528 * by Kumar Gala. -- paulus
529 */
8dad3f92 530static void emulate_single_step(struct pt_regs *regs)
14cf11af
PM		 531{
532 if (single_stepping(regs)) {
533 clear_single_step(regs);
534 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
535 }
536}
537
dc1c1ca3
SR		 538static void parse_fpe(struct pt_regs *regs)
539{
540 int code = 0;
541 unsigned long fpscr;
542
dc1c1ca3 543 flush_fp_to_thread(current);
dc1c1ca3 544
25c8a78b 545 fpscr = current->thread.fpscr.val;
dc1c1ca3
SR		 546
547 /* Invalid operation */
548 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
549 code = FPE_FLTINV;
550
551 /* Overflow */
552 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
553 code = FPE_FLTOVF;
554
555 /* Underflow */
556 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
557 code = FPE_FLTUND;
558
559 /* Divide by zero */
560 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
561 code = FPE_FLTDIV;
562
563 /* Inexact result */
564 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
565 code = FPE_FLTRES;
566
567 _exception(SIGFPE, regs, code, regs->nip);
568}
569
570/*
571 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 572 * provide the PVR to user applications using the mfspr rd, PVR.
573 * Return non-zero if we can't emulate, or -EFAULT if the associated
574 * memory access caused an access fault. Return zero on success.
575 *
576 * There are a couple of ways to do this, either "decode" the instruction
577 * or directly match lots of bits. In this case, matching lots of
578 * bits is faster and easier.
86417780 579 *
14cf11af
PM		 580 */
581#define INST_MFSPR_PVR 0x7c1f42a6
582#define INST_MFSPR_PVR_MASK 0xfc1fffff
583
584#define INST_DCBA 0x7c0005ec
87589f08 585#define INST_DCBA_MASK 0xfc0007fe
14cf11af
PM		 586
587#define INST_MCRXR 0x7c000400
87589f08 588#define INST_MCRXR_MASK 0xfc0007fe
14cf11af
PM		 589
590#define INST_STRING 0x7c00042a
87589f08
PM		 591#define INST_STRING_MASK 0xfc0007fe
592#define INST_STRING_GEN_MASK 0xfc00067e
14cf11af
PM		 593#define INST_LSWI 0x7c0004aa
594#define INST_LSWX 0x7c00042a
595#define INST_STSWI 0x7c0005aa
596#define INST_STSWX 0x7c00052a
597
c3412dcb
WS		 598#define INST_POPCNTB 0x7c0000f4
599#define INST_POPCNTB_MASK 0xfc0007fe
600
14cf11af
PM		 601static int emulate_string_inst(struct pt_regs *regs, u32 instword)
602{
603 u8 rT = (instword >> 21) & 0x1f;
604 u8 rA = (instword >> 16) & 0x1f;
605 u8 NB_RB = (instword >> 11) & 0x1f;
606 u32 num_bytes;
607 unsigned long EA;
608 int pos = 0;
609
610 /* Early out if we are an invalid form of lswx */
611 if ((instword & INST_STRING_MASK) == INST_LSWX)
612 if ((rT == rA) || (rT == NB_RB))
613 return -EINVAL;
614
615 EA = (rA == 0) ? 0 : regs->gpr[rA];
616
617 switch (instword & INST_STRING_MASK) {
618 case INST_LSWX:
619 case INST_STSWX:
620 EA += NB_RB;
621 num_bytes = regs->xer & 0x7f;
622 break;
623 case INST_LSWI:
624 case INST_STSWI:
625 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
626 break;
627 default:
628 return -EINVAL;
629 }
630
631 while (num_bytes != 0)
632 {
633 u8 val;
634 u32 shift = 8 * (3 - (pos & 0x3));
635
636 switch ((instword & INST_STRING_MASK)) {
637 case INST_LSWX:
638 case INST_LSWI:
639 if (get_user(val, (u8 __user *)EA))
640 return -EFAULT;
641 /* first time updating this reg,
642 * zero it out */
643 if (pos == 0)
644 regs->gpr[rT] = 0;
645 regs->gpr[rT] |= val << shift;
646 break;
647 case INST_STSWI:
648 case INST_STSWX:
649 val = regs->gpr[rT] >> shift;
650 if (put_user(val, (u8 __user *)EA))
651 return -EFAULT;
652 break;
653 }
654 /* move EA to next address */
655 EA += 1;
656 num_bytes--;
657
658 /* manage our position within the register */
659 if (++pos == 4) {
660 pos = 0;
661 if (++rT == 32)
662 rT = 0;
663 }
664 }
665
666 return 0;
667}
668
c3412dcb
WS		 669static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
670{
671 u32 ra,rs;
672 unsigned long tmp;
673
674 ra = (instword >> 16) & 0x1f;
675 rs = (instword >> 21) & 0x1f;
676
677 tmp = regs->gpr[rs];
678 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
679 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
680 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
681 regs->gpr[ra] = tmp;
682
683 return 0;
684}
685
14cf11af
PM		 686static int emulate_instruction(struct pt_regs *regs)
687{
688 u32 instword;
689 u32 rd;
690
fab5db97 691 if (!user_mode(regs) || (regs->msr & MSR_LE))
14cf11af
PM		 692 return -EINVAL;
693 CHECK_FULL_REGS(regs);
694
695 if (get_user(instword, (u32 __user *)(regs->nip)))
696 return -EFAULT;
697
698 /* Emulate the mfspr rD, PVR. */
699 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
700 rd = (instword >> 21) & 0x1f;
701 regs->gpr[rd] = mfspr(SPRN_PVR);
702 return 0;
703 }
704
705 /* Emulating the dcba insn is just a no-op. */
8dad3f92 706 if ((instword & INST_DCBA_MASK) == INST_DCBA)
14cf11af
PM		 707 return 0;
708
709 /* Emulate the mcrxr insn. */
710 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
86417780 711 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 712 unsigned long msk = 0xf0000000UL >> shift;
713
714 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
715 regs->xer &= ~0xf0000000UL;
716 return 0;
717 }
718
719 /* Emulate load/store string insn. */
720 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
721 return emulate_string_inst(regs, instword);
722
c3412dcb
WS		 723 /* Emulate the popcntb (Population Count Bytes) instruction. */
724 if ((instword & INST_POPCNTB_MASK) == INST_POPCNTB) {
725 return emulate_popcntb_inst(regs, instword);
726 }
727
14cf11af
PM		 728 return -EINVAL;
729}
730
73c9ceab 731int is_valid_bugaddr(unsigned long addr)
14cf11af 732{
73c9ceab 733 return is_kernel_addr(addr);
14cf11af
PM		 734}
735
8dad3f92 736void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 737{
738 unsigned int reason = get_reason(regs);
739 extern int do_mathemu(struct pt_regs *regs);
740
aa42c69c
KP		 741 /* We can now get here via a FP Unavailable exception if the core
742 * has no FPU, in that case no reason flags will be set */
8dad3f92 743#ifdef CONFIG_MATH_EMULATION
14cf11af
PM		 744 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
745 * but there seems to be a hardware bug on the 405GP (RevD)
746 * that means ESR is sometimes set incorrectly - either to
747 * ESR_DST (!?) or 0. In the process of chasing this with the
748 * hardware people - not sure if it can happen on any illegal
749 * instruction or only on FP instructions, whether there is a
750 * pattern to occurences etc. -dgibson 31/Mar/2003 */
751 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
752 emulate_single_step(regs);
753 return;
754 }
8dad3f92 755#endif /* CONFIG_MATH_EMULATION */
14cf11af 756
dc1c1ca3
SR		 757 if (reason & REASON_FP) {
758 /* IEEE FP exception */
759 parse_fpe(regs);
8dad3f92
PM		 760 return;
761 }
762 if (reason & REASON_TRAP) {
14cf11af 763 /* trap exception */
dc1c1ca3
SR		 764 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
765 == NOTIFY_STOP)
766 return;
14cf11af
PM		 767 if (debugger_bpt(regs))
768 return;
73c9ceab
JF		 769
770 if (!(regs->msr & MSR_PR) && /* not user-mode */
771 report_bug(regs->nip) == BUG_TRAP_TYPE_WARN) {
14cf11af
PM		 772 regs->nip += 4;
773 return;
774 }
8dad3f92
PM		 775 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
776 return;
777 }
778
cd8a5673
PM		 779 local_irq_enable();
780
8dad3f92
PM		 781 /* Try to emulate it if we should. */
782 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 783 switch (emulate_instruction(regs)) {
784 case 0:
785 regs->nip += 4;
786 emulate_single_step(regs);
8dad3f92 787 return;
14cf11af
PM		 788 case -EFAULT:
789 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 790 return;
14cf11af
PM		 791 }
792 }
8dad3f92
PM		 793
794 if (reason & REASON_PRIVILEGED)
795 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
796 else
797 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 798}
799
dc1c1ca3 800void alignment_exception(struct pt_regs *regs)
14cf11af 801{
4393c4f6 802 int sig, code, fixed = 0;
14cf11af 803
e9370ae1
PM		 804 /* we don't implement logging of alignment exceptions */
805 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
806 fixed = fix_alignment(regs);
14cf11af
PM		 807
808 if (fixed == 1) {
809 regs->nip += 4; /* skip over emulated instruction */
810 emulate_single_step(regs);
811 return;
812 }
813
dc1c1ca3 814 /* Operand address was bad */
14cf11af 815 if (fixed == -EFAULT) {
4393c4f6
BH		 816 sig = SIGSEGV;
817 code = SEGV_ACCERR;
818 } else {
819 sig = SIGBUS;
820 code = BUS_ADRALN;
14cf11af 821 }
4393c4f6
BH		 822 if (user_mode(regs))
823 _exception(sig, regs, code, regs->dar);
824 else
825 bad_page_fault(regs, regs->dar, sig);
14cf11af
PM		 826}
827
828void StackOverflow(struct pt_regs *regs)
829{
830 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
831 current, regs->gpr[1]);
832 debugger(regs);
833 show_regs(regs);
834 panic("kernel stack overflow");
835}
836
837void nonrecoverable_exception(struct pt_regs *regs)
838{
839 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
840 regs->nip, regs->msr);
841 debugger(regs);
842 die("nonrecoverable exception", regs, SIGKILL);
843}
844
845void trace_syscall(struct pt_regs *regs)
846{
847 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
848 current, current->pid, regs->nip, regs->link, regs->gpr[0],
849 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
850}
dc1c1ca3 851
dc1c1ca3
SR		 852void kernel_fp_unavailable_exception(struct pt_regs *regs)
853{
854 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
855 "%lx at %lx\n", regs->trap, regs->nip);
856 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
857}
dc1c1ca3
SR		 858
859void altivec_unavailable_exception(struct pt_regs *regs)
860{
dc1c1ca3
SR		 861 if (user_mode(regs)) {
862 /* A user program has executed an altivec instruction,
863 but this kernel doesn't support altivec. */
864 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
865 return;
866 }
6c4841c2 867
dc1c1ca3
SR		 868 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
869 "%lx at %lx\n", regs->trap, regs->nip);
870 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 871}
872
dc1c1ca3
SR		 873void performance_monitor_exception(struct pt_regs *regs)
874{
875 perf_irq(regs);
876}
dc1c1ca3 877
8dad3f92 878#ifdef CONFIG_8xx
14cf11af
PM		 879void SoftwareEmulation(struct pt_regs *regs)
880{
881 extern int do_mathemu(struct pt_regs *);
882 extern int Soft_emulate_8xx(struct pt_regs *);
883 int errcode;
884
885 CHECK_FULL_REGS(regs);
886
887 if (!user_mode(regs)) {
888 debugger(regs);
889 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
890 }
891
892#ifdef CONFIG_MATH_EMULATION
893 errcode = do_mathemu(regs);
894#else
895 errcode = Soft_emulate_8xx(regs);
896#endif
897 if (errcode) {
898 if (errcode > 0)
899 _exception(SIGFPE, regs, 0, 0);
900 else if (errcode == -EFAULT)
901 _exception(SIGSEGV, regs, 0, 0);
902 else
903 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
904 } else
905 emulate_single_step(regs);
906}
8dad3f92 907#endif /* CONFIG_8xx */
14cf11af
PM		 908
909#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
910
911void DebugException(struct pt_regs *regs, unsigned long debug_status)
912{
913 if (debug_status & DBSR_IC) { /* instruction completion */
914 regs->msr &= ~MSR_DE;
915 if (user_mode(regs)) {
916 current->thread.dbcr0 &= ~DBCR0_IC;
917 } else {
918 /* Disable instruction completion */
919 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
920 /* Clear the instruction completion event */
921 mtspr(SPRN_DBSR, DBSR_IC);
922 if (debugger_sstep(regs))
923 return;
924 }
925 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
926 }
927}
928#endif /* CONFIG_4xx || CONFIG_BOOKE */
929
930#if !defined(CONFIG_TAU_INT)
931void TAUException(struct pt_regs *regs)
932{
933 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
934 regs->nip, regs->msr, regs->trap, print_tainted());
935}
936#endif /* CONFIG_INT_TAU */
14cf11af
PM		 937
938#ifdef CONFIG_ALTIVEC
dc1c1ca3 939void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 940{
941 int err;
942
14cf11af
PM		 943 if (!user_mode(regs)) {
944 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
945 " at %lx\n", regs->nip);
8dad3f92 946 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 947 }
948
dc1c1ca3 949 flush_altivec_to_thread(current);
dc1c1ca3 950
14cf11af
PM		 951 err = emulate_altivec(regs);
952 if (err == 0) {
953 regs->nip += 4; /* skip emulated instruction */
954 emulate_single_step(regs);
955 return;
956 }
957
958 if (err == -EFAULT) {
959 /* got an error reading the instruction */
960 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
961 } else {
962 /* didn't recognize the instruction */
963 /* XXX quick hack for now: set the non-Java bit in the VSCR */
964 if (printk_ratelimit())
965 printk(KERN_ERR "Unrecognized altivec instruction "
966 "in %s at %lx\n", current->comm, regs->nip);
967 current->thread.vscr.u[3] |= 0x10000;
968 }
969}
970#endif /* CONFIG_ALTIVEC */
971
14cf11af
PM		 972#ifdef CONFIG_FSL_BOOKE
973void CacheLockingException(struct pt_regs *regs, unsigned long address,
974 unsigned long error_code)
975{
976 /* We treat cache locking instructions from the user
977 * as priv ops, in the future we could try to do
978 * something smarter
979 */
980 if (error_code & (ESR_DLK|ESR_ILK))
981 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
982 return;
983}
984#endif /* CONFIG_FSL_BOOKE */
985
986#ifdef CONFIG_SPE
987void SPEFloatingPointException(struct pt_regs *regs)
988{
989 unsigned long spefscr;
990 int fpexc_mode;
991 int code = 0;
992
993 spefscr = current->thread.spefscr;
994 fpexc_mode = current->thread.fpexc_mode;
995
996 /* Hardware does not neccessarily set sticky
997 * underflow/overflow/invalid flags */
998 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
999 code = FPE_FLTOVF;
1000 spefscr |= SPEFSCR_FOVFS;
1001 }
1002 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1003 code = FPE_FLTUND;
1004 spefscr |= SPEFSCR_FUNFS;
1005 }
1006 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1007 code = FPE_FLTDIV;
1008 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1009 code = FPE_FLTINV;
1010 spefscr |= SPEFSCR_FINVS;
1011 }
1012 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1013 code = FPE_FLTRES;
1014
1015 current->thread.spefscr = spefscr;
1016
1017 _exception(SIGFPE, regs, code, regs->nip);
1018 return;
1019}
1020#endif
1021
dc1c1ca3
SR		 1022/*
1023 * We enter here if we get an unrecoverable exception, that is, one
1024 * that happened at a point where the RI (recoverable interrupt) bit
1025 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1026 * we therefore lost state by taking this exception.
1027 */
1028void unrecoverable_exception(struct pt_regs *regs)
1029{
1030 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1031 regs->trap, regs->nip);
1032 die("Unrecoverable exception", regs, SIGABRT);
1033}
dc1c1ca3 1034
14cf11af
PM		 1035#ifdef CONFIG_BOOKE_WDT
1036/*
1037 * Default handler for a Watchdog exception,
1038 * spins until a reboot occurs
1039 */
1040void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1041{
1042 /* Generic WatchdogHandler, implement your own */
1043 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1044 return;
1045}
1046
1047void WatchdogException(struct pt_regs *regs)
1048{
1049 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1050 WatchdogHandler(regs);
1051}
1052#endif
dc1c1ca3 1053
dc1c1ca3
SR		 1054/*
1055 * We enter here if we discover during exception entry that we are
1056 * running in supervisor mode with a userspace value in the stack pointer.
1057 */
1058void kernel_bad_stack(struct pt_regs *regs)
1059{
1060 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1061 regs->gpr[1], regs->nip);
1062 die("Bad kernel stack pointer", regs, SIGABRT);
1063}
14cf11af
PM		 1064
1065void __init trap_init(void)
1066{
1067}
kernel source for telekom puls (alcatel/mediatek)