Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af PM |
25 | #include <linux/slab.h> |
26 | #include <linux/user.h> | |
27 | #include <linux/a.out.h> | |
28 | #include <linux/interrupt.h> | |
14cf11af PM |
29 | #include <linux/init.h> |
30 | #include <linux/module.h> | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
cc532915 | 34 | #include <linux/kexec.h> |
14cf11af | 35 | |
86417780 | 36 | #include <asm/kdebug.h> |
14cf11af PM |
37 | #include <asm/pgtable.h> |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/system.h> | |
40 | #include <asm/io.h> | |
86417780 PM |
41 | #include <asm/machdep.h> |
42 | #include <asm/rtas.h> | |
f7f6f4fe | 43 | #include <asm/pmc.h> |
dc1c1ca3 | 44 | #ifdef CONFIG_PPC32 |
14cf11af | 45 | #include <asm/reg.h> |
86417780 | 46 | #endif |
14cf11af PM |
47 | #ifdef CONFIG_PMAC_BACKLIGHT |
48 | #include <asm/backlight.h> | |
49 | #endif | |
dc1c1ca3 | 50 | #ifdef CONFIG_PPC64 |
86417780 | 51 | #include <asm/firmware.h> |
dc1c1ca3 | 52 | #include <asm/processor.h> |
dc1c1ca3 SR |
53 | #endif |
54 | ||
86417780 PM |
55 | #ifdef CONFIG_PPC64 /* XXX */ |
56 | #define _IO_BASE pci_io_base | |
57 | #endif | |
58 | ||
14cf11af PM |
59 | #ifdef CONFIG_DEBUGGER |
60 | int (*__debugger)(struct pt_regs *regs); | |
61 | int (*__debugger_ipi)(struct pt_regs *regs); | |
62 | int (*__debugger_bpt)(struct pt_regs *regs); | |
63 | int (*__debugger_sstep)(struct pt_regs *regs); | |
64 | int (*__debugger_iabr_match)(struct pt_regs *regs); | |
65 | int (*__debugger_dabr_match)(struct pt_regs *regs); | |
66 | int (*__debugger_fault_handler)(struct pt_regs *regs); | |
67 | ||
68 | EXPORT_SYMBOL(__debugger); | |
69 | EXPORT_SYMBOL(__debugger_ipi); | |
70 | EXPORT_SYMBOL(__debugger_bpt); | |
71 | EXPORT_SYMBOL(__debugger_sstep); | |
72 | EXPORT_SYMBOL(__debugger_iabr_match); | |
73 | EXPORT_SYMBOL(__debugger_dabr_match); | |
74 | EXPORT_SYMBOL(__debugger_fault_handler); | |
75 | #endif | |
76 | ||
77 | struct notifier_block *powerpc_die_chain; | |
78 | static DEFINE_SPINLOCK(die_notifier_lock); | |
79 | ||
80 | int register_die_notifier(struct notifier_block *nb) | |
81 | { | |
82 | int err = 0; | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&die_notifier_lock, flags); | |
86 | err = notifier_chain_register(&powerpc_die_chain, nb); | |
87 | spin_unlock_irqrestore(&die_notifier_lock, flags); | |
88 | return err; | |
89 | } | |
90 | ||
91 | /* | |
92 | * Trap & Exception support | |
93 | */ | |
94 | ||
95 | static DEFINE_SPINLOCK(die_lock); | |
96 | ||
97 | int die(const char *str, struct pt_regs *regs, long err) | |
98 | { | |
cc532915 | 99 | static int die_counter, crash_dump_start = 0; |
14cf11af PM |
100 | int nl = 0; |
101 | ||
102 | if (debugger(regs)) | |
103 | return 1; | |
104 | ||
105 | console_verbose(); | |
106 | spin_lock_irq(&die_lock); | |
107 | bust_spinlocks(1); | |
8dad3f92 | 108 | #ifdef CONFIG_PMAC_BACKLIGHT |
14cf11af PM |
109 | if (_machine == _MACH_Pmac) { |
110 | set_backlight_enable(1); | |
111 | set_backlight_level(BACKLIGHT_MAX); | |
112 | } | |
113 | #endif | |
114 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
115 | #ifdef CONFIG_PREEMPT | |
116 | printk("PREEMPT "); | |
117 | nl = 1; | |
118 | #endif | |
119 | #ifdef CONFIG_SMP | |
120 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
121 | nl = 1; | |
122 | #endif | |
123 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
124 | printk("DEBUG_PAGEALLOC "); | |
125 | nl = 1; | |
126 | #endif | |
127 | #ifdef CONFIG_NUMA | |
128 | printk("NUMA "); | |
129 | nl = 1; | |
130 | #endif | |
131 | #ifdef CONFIG_PPC64 | |
799d6046 | 132 | switch (_machine) { |
14cf11af PM |
133 | case PLATFORM_PSERIES: |
134 | printk("PSERIES "); | |
135 | nl = 1; | |
136 | break; | |
137 | case PLATFORM_PSERIES_LPAR: | |
138 | printk("PSERIES LPAR "); | |
139 | nl = 1; | |
140 | break; | |
141 | case PLATFORM_ISERIES_LPAR: | |
142 | printk("ISERIES LPAR "); | |
143 | nl = 1; | |
144 | break; | |
145 | case PLATFORM_POWERMAC: | |
146 | printk("POWERMAC "); | |
147 | nl = 1; | |
148 | break; | |
f3f66f59 AB |
149 | case PLATFORM_CELL: |
150 | printk("CELL "); | |
14cf11af PM |
151 | nl = 1; |
152 | break; | |
153 | } | |
154 | #endif | |
155 | if (nl) | |
156 | printk("\n"); | |
157 | print_modules(); | |
158 | show_regs(regs); | |
159 | bust_spinlocks(0); | |
cc532915 ME |
160 | |
161 | if (!crash_dump_start && kexec_should_crash(current)) { | |
162 | crash_dump_start = 1; | |
163 | spin_unlock_irq(&die_lock); | |
164 | crash_kexec(regs); | |
165 | /* NOTREACHED */ | |
166 | } | |
14cf11af | 167 | spin_unlock_irq(&die_lock); |
cc532915 ME |
168 | if (crash_dump_start) |
169 | /* | |
170 | * Only for soft-reset: Other CPUs will be responded to an IPI | |
171 | * sent by first kexec CPU. | |
172 | */ | |
173 | for(;;) | |
174 | ; | |
14cf11af PM |
175 | |
176 | if (in_interrupt()) | |
177 | panic("Fatal exception in interrupt"); | |
178 | ||
179 | if (panic_on_oops) { | |
dc1c1ca3 SR |
180 | #ifdef CONFIG_PPC64 |
181 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
182 | ssleep(5); | |
183 | #endif | |
14cf11af PM |
184 | panic("Fatal exception"); |
185 | } | |
186 | do_exit(err); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
192 | { | |
193 | siginfo_t info; | |
194 | ||
195 | if (!user_mode(regs)) { | |
196 | if (die("Exception in kernel mode", regs, signr)) | |
197 | return; | |
198 | } | |
199 | ||
200 | memset(&info, 0, sizeof(info)); | |
201 | info.si_signo = signr; | |
202 | info.si_code = code; | |
203 | info.si_addr = (void __user *) addr; | |
204 | force_sig_info(signr, &info, current); | |
205 | ||
206 | /* | |
207 | * Init gets no signals that it doesn't have a handler for. | |
208 | * That's all very well, but if it has caused a synchronous | |
209 | * exception and we ignore the resulting signal, it will just | |
210 | * generate the same exception over and over again and we get | |
211 | * nowhere. Better to kill it and let the kernel panic. | |
212 | */ | |
213 | if (current->pid == 1) { | |
214 | __sighandler_t handler; | |
215 | ||
216 | spin_lock_irq(¤t->sighand->siglock); | |
217 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
218 | spin_unlock_irq(¤t->sighand->siglock); | |
219 | if (handler == SIG_DFL) { | |
220 | /* init has generated a synchronous exception | |
221 | and it doesn't have a handler for the signal */ | |
222 | printk(KERN_CRIT "init has generated signal %d " | |
223 | "but has no handler for it\n", signr); | |
224 | do_exit(signr); | |
225 | } | |
226 | } | |
227 | } | |
228 | ||
229 | #ifdef CONFIG_PPC64 | |
230 | void system_reset_exception(struct pt_regs *regs) | |
231 | { | |
232 | /* See if any machine dependent calls */ | |
c902be71 AB |
233 | if (ppc_md.system_reset_exception) { |
234 | if (ppc_md.system_reset_exception(regs)) | |
235 | return; | |
236 | } | |
14cf11af | 237 | |
8dad3f92 | 238 | die("System Reset", regs, SIGABRT); |
14cf11af PM |
239 | |
240 | /* Must die if the interrupt is not recoverable */ | |
241 | if (!(regs->msr & MSR_RI)) | |
242 | panic("Unrecoverable System Reset"); | |
243 | ||
244 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
245 | } | |
246 | #endif | |
247 | ||
248 | /* | |
249 | * I/O accesses can cause machine checks on powermacs. | |
250 | * Check if the NIP corresponds to the address of a sync | |
251 | * instruction for which there is an entry in the exception | |
252 | * table. | |
253 | * Note that the 601 only takes a machine check on TEA | |
254 | * (transfer error ack) signal assertion, and does not | |
255 | * set any of the top 16 bits of SRR1. | |
256 | * -- paulus. | |
257 | */ | |
258 | static inline int check_io_access(struct pt_regs *regs) | |
259 | { | |
260 | #ifdef CONFIG_PPC_PMAC | |
261 | unsigned long msr = regs->msr; | |
262 | const struct exception_table_entry *entry; | |
263 | unsigned int *nip = (unsigned int *)regs->nip; | |
264 | ||
265 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
266 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
267 | /* | |
268 | * Check that it's a sync instruction, or somewhere | |
269 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
270 | * As the address is in the exception table | |
271 | * we should be able to read the instr there. | |
272 | * For the debug message, we look at the preceding | |
273 | * load or store. | |
274 | */ | |
275 | if (*nip == 0x60000000) /* nop */ | |
276 | nip -= 2; | |
277 | else if (*nip == 0x4c00012c) /* isync */ | |
278 | --nip; | |
279 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
280 | /* sync or twi */ | |
281 | unsigned int rb; | |
282 | ||
283 | --nip; | |
284 | rb = (*nip >> 11) & 0x1f; | |
285 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
286 | (*nip & 0x100)? "OUT to": "IN from", | |
287 | regs->gpr[rb] - _IO_BASE, nip); | |
288 | regs->msr |= MSR_RI; | |
289 | regs->nip = entry->fixup; | |
290 | return 1; | |
291 | } | |
292 | } | |
293 | #endif /* CONFIG_PPC_PMAC */ | |
294 | return 0; | |
295 | } | |
296 | ||
297 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
298 | /* On 4xx, the reason for the machine check or program exception | |
299 | is in the ESR. */ | |
300 | #define get_reason(regs) ((regs)->dsisr) | |
301 | #ifndef CONFIG_FSL_BOOKE | |
302 | #define get_mc_reason(regs) ((regs)->dsisr) | |
303 | #else | |
304 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | |
305 | #endif | |
306 | #define REASON_FP ESR_FP | |
307 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
308 | #define REASON_PRIVILEGED ESR_PPR | |
309 | #define REASON_TRAP ESR_PTR | |
310 | ||
311 | /* single-step stuff */ | |
312 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
313 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
314 | ||
315 | #else | |
316 | /* On non-4xx, the reason for the machine check or program | |
317 | exception is in the MSR. */ | |
318 | #define get_reason(regs) ((regs)->msr) | |
319 | #define get_mc_reason(regs) ((regs)->msr) | |
320 | #define REASON_FP 0x100000 | |
321 | #define REASON_ILLEGAL 0x80000 | |
322 | #define REASON_PRIVILEGED 0x40000 | |
323 | #define REASON_TRAP 0x20000 | |
324 | ||
325 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
326 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
327 | #endif | |
328 | ||
329 | /* | |
330 | * This is "fall-back" implementation for configurations | |
331 | * which don't provide platform-specific machine check info | |
332 | */ | |
333 | void __attribute__ ((weak)) | |
334 | platform_machine_check(struct pt_regs *regs) | |
335 | { | |
336 | } | |
337 | ||
dc1c1ca3 | 338 | void machine_check_exception(struct pt_regs *regs) |
14cf11af PM |
339 | { |
340 | #ifdef CONFIG_PPC64 | |
341 | int recover = 0; | |
342 | ||
343 | /* See if any machine dependent calls */ | |
344 | if (ppc_md.machine_check_exception) | |
345 | recover = ppc_md.machine_check_exception(regs); | |
346 | ||
347 | if (recover) | |
348 | return; | |
349 | #else | |
350 | unsigned long reason = get_mc_reason(regs); | |
351 | ||
352 | if (user_mode(regs)) { | |
353 | regs->msr |= MSR_RI; | |
354 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
355 | return; | |
356 | } | |
357 | ||
358 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
359 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
360 | bad_page_fault(regs, regs->dar, SIGBUS); | |
361 | return; | |
362 | #endif | |
363 | ||
364 | if (debugger_fault_handler(regs)) { | |
365 | regs->msr |= MSR_RI; | |
366 | return; | |
367 | } | |
368 | ||
369 | if (check_io_access(regs)) | |
370 | return; | |
371 | ||
372 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) | |
373 | if (reason & ESR_IMCP) { | |
374 | printk("Instruction"); | |
375 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
376 | } else | |
377 | printk("Data"); | |
378 | printk(" machine check in kernel mode.\n"); | |
379 | #elif defined(CONFIG_440A) | |
380 | printk("Machine check in kernel mode.\n"); | |
381 | if (reason & ESR_IMCP){ | |
382 | printk("Instruction Synchronous Machine Check exception\n"); | |
383 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
384 | } | |
385 | else { | |
386 | u32 mcsr = mfspr(SPRN_MCSR); | |
387 | if (mcsr & MCSR_IB) | |
388 | printk("Instruction Read PLB Error\n"); | |
389 | if (mcsr & MCSR_DRB) | |
390 | printk("Data Read PLB Error\n"); | |
391 | if (mcsr & MCSR_DWB) | |
392 | printk("Data Write PLB Error\n"); | |
393 | if (mcsr & MCSR_TLBP) | |
394 | printk("TLB Parity Error\n"); | |
395 | if (mcsr & MCSR_ICP){ | |
396 | flush_instruction_cache(); | |
397 | printk("I-Cache Parity Error\n"); | |
398 | } | |
399 | if (mcsr & MCSR_DCSP) | |
400 | printk("D-Cache Search Parity Error\n"); | |
401 | if (mcsr & MCSR_DCFP) | |
402 | printk("D-Cache Flush Parity Error\n"); | |
403 | if (mcsr & MCSR_IMPE) | |
404 | printk("Machine Check exception is imprecise\n"); | |
405 | ||
406 | /* Clear MCSR */ | |
407 | mtspr(SPRN_MCSR, mcsr); | |
408 | } | |
409 | #elif defined (CONFIG_E500) | |
410 | printk("Machine check in kernel mode.\n"); | |
411 | printk("Caused by (from MCSR=%lx): ", reason); | |
412 | ||
413 | if (reason & MCSR_MCP) | |
414 | printk("Machine Check Signal\n"); | |
415 | if (reason & MCSR_ICPERR) | |
416 | printk("Instruction Cache Parity Error\n"); | |
417 | if (reason & MCSR_DCP_PERR) | |
418 | printk("Data Cache Push Parity Error\n"); | |
419 | if (reason & MCSR_DCPERR) | |
420 | printk("Data Cache Parity Error\n"); | |
421 | if (reason & MCSR_GL_CI) | |
422 | printk("Guarded Load or Cache-Inhibited stwcx.\n"); | |
423 | if (reason & MCSR_BUS_IAERR) | |
424 | printk("Bus - Instruction Address Error\n"); | |
425 | if (reason & MCSR_BUS_RAERR) | |
426 | printk("Bus - Read Address Error\n"); | |
427 | if (reason & MCSR_BUS_WAERR) | |
428 | printk("Bus - Write Address Error\n"); | |
429 | if (reason & MCSR_BUS_IBERR) | |
430 | printk("Bus - Instruction Data Error\n"); | |
431 | if (reason & MCSR_BUS_RBERR) | |
432 | printk("Bus - Read Data Bus Error\n"); | |
433 | if (reason & MCSR_BUS_WBERR) | |
434 | printk("Bus - Read Data Bus Error\n"); | |
435 | if (reason & MCSR_BUS_IPERR) | |
436 | printk("Bus - Instruction Parity Error\n"); | |
437 | if (reason & MCSR_BUS_RPERR) | |
438 | printk("Bus - Read Parity Error\n"); | |
439 | #elif defined (CONFIG_E200) | |
440 | printk("Machine check in kernel mode.\n"); | |
441 | printk("Caused by (from MCSR=%lx): ", reason); | |
442 | ||
443 | if (reason & MCSR_MCP) | |
444 | printk("Machine Check Signal\n"); | |
445 | if (reason & MCSR_CP_PERR) | |
446 | printk("Cache Push Parity Error\n"); | |
447 | if (reason & MCSR_CPERR) | |
448 | printk("Cache Parity Error\n"); | |
449 | if (reason & MCSR_EXCP_ERR) | |
450 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
451 | if (reason & MCSR_BUS_IRERR) | |
452 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
453 | if (reason & MCSR_BUS_DRERR) | |
454 | printk("Bus - Read Bus Error on data load\n"); | |
455 | if (reason & MCSR_BUS_WRERR) | |
456 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
457 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | |
458 | printk("Machine check in kernel mode.\n"); | |
459 | printk("Caused by (from SRR1=%lx): ", reason); | |
460 | switch (reason & 0x601F0000) { | |
461 | case 0x80000: | |
462 | printk("Machine check signal\n"); | |
463 | break; | |
464 | case 0: /* for 601 */ | |
465 | case 0x40000: | |
466 | case 0x140000: /* 7450 MSS error and TEA */ | |
467 | printk("Transfer error ack signal\n"); | |
468 | break; | |
469 | case 0x20000: | |
470 | printk("Data parity error signal\n"); | |
471 | break; | |
472 | case 0x10000: | |
473 | printk("Address parity error signal\n"); | |
474 | break; | |
475 | case 0x20000000: | |
476 | printk("L1 Data Cache error\n"); | |
477 | break; | |
478 | case 0x40000000: | |
479 | printk("L1 Instruction Cache error\n"); | |
480 | break; | |
481 | case 0x00100000: | |
482 | printk("L2 data cache parity error\n"); | |
483 | break; | |
484 | default: | |
485 | printk("Unknown values in msr\n"); | |
486 | } | |
487 | #endif /* CONFIG_4xx */ | |
488 | ||
489 | /* | |
490 | * Optional platform-provided routine to print out | |
491 | * additional info, e.g. bus error registers. | |
492 | */ | |
493 | platform_machine_check(regs); | |
86417780 | 494 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
495 | |
496 | if (debugger_fault_handler(regs)) | |
497 | return; | |
8dad3f92 | 498 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
499 | |
500 | /* Must die if the interrupt is not recoverable */ | |
501 | if (!(regs->msr & MSR_RI)) | |
502 | panic("Unrecoverable Machine check"); | |
503 | } | |
504 | ||
505 | void SMIException(struct pt_regs *regs) | |
506 | { | |
507 | die("System Management Interrupt", regs, SIGABRT); | |
508 | } | |
509 | ||
dc1c1ca3 | 510 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
511 | { |
512 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
513 | regs->nip, regs->msr, regs->trap); | |
514 | ||
515 | _exception(SIGTRAP, regs, 0, 0); | |
516 | } | |
517 | ||
dc1c1ca3 | 518 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
519 | { |
520 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
521 | 5, SIGTRAP) == NOTIFY_STOP) | |
522 | return; | |
523 | if (debugger_iabr_match(regs)) | |
524 | return; | |
525 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
526 | } | |
527 | ||
528 | void RunModeException(struct pt_regs *regs) | |
529 | { | |
530 | _exception(SIGTRAP, regs, 0, 0); | |
531 | } | |
532 | ||
8dad3f92 | 533 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
534 | { |
535 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
536 | ||
537 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
538 | 5, SIGTRAP) == NOTIFY_STOP) | |
539 | return; | |
540 | if (debugger_sstep(regs)) | |
541 | return; | |
542 | ||
543 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
544 | } | |
545 | ||
546 | /* | |
547 | * After we have successfully emulated an instruction, we have to | |
548 | * check if the instruction was being single-stepped, and if so, | |
549 | * pretend we got a single-step exception. This was pointed out | |
550 | * by Kumar Gala. -- paulus | |
551 | */ | |
8dad3f92 | 552 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
553 | { |
554 | if (single_stepping(regs)) { | |
555 | clear_single_step(regs); | |
556 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
557 | } | |
558 | } | |
559 | ||
dc1c1ca3 SR |
560 | static void parse_fpe(struct pt_regs *regs) |
561 | { | |
562 | int code = 0; | |
563 | unsigned long fpscr; | |
564 | ||
dc1c1ca3 | 565 | flush_fp_to_thread(current); |
dc1c1ca3 | 566 | |
25c8a78b | 567 | fpscr = current->thread.fpscr.val; |
dc1c1ca3 SR |
568 | |
569 | /* Invalid operation */ | |
570 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
571 | code = FPE_FLTINV; | |
572 | ||
573 | /* Overflow */ | |
574 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
575 | code = FPE_FLTOVF; | |
576 | ||
577 | /* Underflow */ | |
578 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
579 | code = FPE_FLTUND; | |
580 | ||
581 | /* Divide by zero */ | |
582 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
583 | code = FPE_FLTDIV; | |
584 | ||
585 | /* Inexact result */ | |
586 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
587 | code = FPE_FLTRES; | |
588 | ||
589 | _exception(SIGFPE, regs, code, regs->nip); | |
590 | } | |
591 | ||
592 | /* | |
593 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
594 | * provide the PVR to user applications using the mfspr rd, PVR. |
595 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
596 | * memory access caused an access fault. Return zero on success. | |
597 | * | |
598 | * There are a couple of ways to do this, either "decode" the instruction | |
599 | * or directly match lots of bits. In this case, matching lots of | |
600 | * bits is faster and easier. | |
86417780 | 601 | * |
14cf11af PM |
602 | */ |
603 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
604 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
605 | ||
606 | #define INST_DCBA 0x7c0005ec | |
607 | #define INST_DCBA_MASK 0x7c0007fe | |
608 | ||
609 | #define INST_MCRXR 0x7c000400 | |
610 | #define INST_MCRXR_MASK 0x7c0007fe | |
611 | ||
612 | #define INST_STRING 0x7c00042a | |
613 | #define INST_STRING_MASK 0x7c0007fe | |
614 | #define INST_STRING_GEN_MASK 0x7c00067e | |
615 | #define INST_LSWI 0x7c0004aa | |
616 | #define INST_LSWX 0x7c00042a | |
617 | #define INST_STSWI 0x7c0005aa | |
618 | #define INST_STSWX 0x7c00052a | |
619 | ||
620 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) | |
621 | { | |
622 | u8 rT = (instword >> 21) & 0x1f; | |
623 | u8 rA = (instword >> 16) & 0x1f; | |
624 | u8 NB_RB = (instword >> 11) & 0x1f; | |
625 | u32 num_bytes; | |
626 | unsigned long EA; | |
627 | int pos = 0; | |
628 | ||
629 | /* Early out if we are an invalid form of lswx */ | |
630 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
631 | if ((rT == rA) || (rT == NB_RB)) | |
632 | return -EINVAL; | |
633 | ||
634 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
635 | ||
636 | switch (instword & INST_STRING_MASK) { | |
637 | case INST_LSWX: | |
638 | case INST_STSWX: | |
639 | EA += NB_RB; | |
640 | num_bytes = regs->xer & 0x7f; | |
641 | break; | |
642 | case INST_LSWI: | |
643 | case INST_STSWI: | |
644 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
645 | break; | |
646 | default: | |
647 | return -EINVAL; | |
648 | } | |
649 | ||
650 | while (num_bytes != 0) | |
651 | { | |
652 | u8 val; | |
653 | u32 shift = 8 * (3 - (pos & 0x3)); | |
654 | ||
655 | switch ((instword & INST_STRING_MASK)) { | |
656 | case INST_LSWX: | |
657 | case INST_LSWI: | |
658 | if (get_user(val, (u8 __user *)EA)) | |
659 | return -EFAULT; | |
660 | /* first time updating this reg, | |
661 | * zero it out */ | |
662 | if (pos == 0) | |
663 | regs->gpr[rT] = 0; | |
664 | regs->gpr[rT] |= val << shift; | |
665 | break; | |
666 | case INST_STSWI: | |
667 | case INST_STSWX: | |
668 | val = regs->gpr[rT] >> shift; | |
669 | if (put_user(val, (u8 __user *)EA)) | |
670 | return -EFAULT; | |
671 | break; | |
672 | } | |
673 | /* move EA to next address */ | |
674 | EA += 1; | |
675 | num_bytes--; | |
676 | ||
677 | /* manage our position within the register */ | |
678 | if (++pos == 4) { | |
679 | pos = 0; | |
680 | if (++rT == 32) | |
681 | rT = 0; | |
682 | } | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static int emulate_instruction(struct pt_regs *regs) | |
689 | { | |
690 | u32 instword; | |
691 | u32 rd; | |
692 | ||
693 | if (!user_mode(regs)) | |
694 | return -EINVAL; | |
695 | CHECK_FULL_REGS(regs); | |
696 | ||
697 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
698 | return -EFAULT; | |
699 | ||
700 | /* Emulate the mfspr rD, PVR. */ | |
701 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
702 | rd = (instword >> 21) & 0x1f; | |
703 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
704 | return 0; | |
705 | } | |
706 | ||
707 | /* Emulating the dcba insn is just a no-op. */ | |
8dad3f92 | 708 | if ((instword & INST_DCBA_MASK) == INST_DCBA) |
14cf11af PM |
709 | return 0; |
710 | ||
711 | /* Emulate the mcrxr insn. */ | |
712 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
86417780 | 713 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
714 | unsigned long msk = 0xf0000000UL >> shift; |
715 | ||
716 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
717 | regs->xer &= ~0xf0000000UL; | |
718 | return 0; | |
719 | } | |
720 | ||
721 | /* Emulate load/store string insn. */ | |
722 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
723 | return emulate_string_inst(regs, instword); | |
724 | ||
725 | return -EINVAL; | |
726 | } | |
727 | ||
728 | /* | |
729 | * Look through the list of trap instructions that are used for BUG(), | |
730 | * BUG_ON() and WARN_ON() and see if we hit one. At this point we know | |
731 | * that the exception was caused by a trap instruction of some kind. | |
732 | * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 | |
733 | * otherwise. | |
734 | */ | |
735 | extern struct bug_entry __start___bug_table[], __stop___bug_table[]; | |
736 | ||
737 | #ifndef CONFIG_MODULES | |
738 | #define module_find_bug(x) NULL | |
739 | #endif | |
740 | ||
741 | struct bug_entry *find_bug(unsigned long bugaddr) | |
742 | { | |
743 | struct bug_entry *bug; | |
744 | ||
745 | for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) | |
746 | if (bugaddr == bug->bug_addr) | |
747 | return bug; | |
748 | return module_find_bug(bugaddr); | |
749 | } | |
750 | ||
dc1c1ca3 | 751 | static int check_bug_trap(struct pt_regs *regs) |
14cf11af PM |
752 | { |
753 | struct bug_entry *bug; | |
754 | unsigned long addr; | |
755 | ||
756 | if (regs->msr & MSR_PR) | |
757 | return 0; /* not in kernel */ | |
758 | addr = regs->nip; /* address of trap instruction */ | |
759 | if (addr < PAGE_OFFSET) | |
760 | return 0; | |
761 | bug = find_bug(regs->nip); | |
762 | if (bug == NULL) | |
763 | return 0; | |
764 | if (bug->line & BUG_WARNING_TRAP) { | |
765 | /* this is a WARN_ON rather than BUG/BUG_ON */ | |
104dd65f | 766 | printk(KERN_ERR "Badness in %s at %s:%ld\n", |
14cf11af PM |
767 | bug->function, bug->file, |
768 | bug->line & ~BUG_WARNING_TRAP); | |
769 | dump_stack(); | |
770 | return 1; | |
771 | } | |
104dd65f | 772 | printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n", |
14cf11af PM |
773 | bug->function, bug->file, bug->line); |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
8dad3f92 | 778 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
779 | { |
780 | unsigned int reason = get_reason(regs); | |
781 | extern int do_mathemu(struct pt_regs *regs); | |
782 | ||
8dad3f92 | 783 | #ifdef CONFIG_MATH_EMULATION |
14cf11af PM |
784 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
785 | * but there seems to be a hardware bug on the 405GP (RevD) | |
786 | * that means ESR is sometimes set incorrectly - either to | |
787 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
788 | * hardware people - not sure if it can happen on any illegal | |
789 | * instruction or only on FP instructions, whether there is a | |
790 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
791 | if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { | |
792 | emulate_single_step(regs); | |
793 | return; | |
794 | } | |
8dad3f92 | 795 | #endif /* CONFIG_MATH_EMULATION */ |
14cf11af | 796 | |
dc1c1ca3 SR |
797 | if (reason & REASON_FP) { |
798 | /* IEEE FP exception */ | |
799 | parse_fpe(regs); | |
8dad3f92 PM |
800 | return; |
801 | } | |
802 | if (reason & REASON_TRAP) { | |
14cf11af | 803 | /* trap exception */ |
dc1c1ca3 SR |
804 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
805 | == NOTIFY_STOP) | |
806 | return; | |
14cf11af PM |
807 | if (debugger_bpt(regs)) |
808 | return; | |
809 | if (check_bug_trap(regs)) { | |
810 | regs->nip += 4; | |
811 | return; | |
812 | } | |
8dad3f92 PM |
813 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
814 | return; | |
815 | } | |
816 | ||
cd8a5673 PM |
817 | local_irq_enable(); |
818 | ||
8dad3f92 PM |
819 | /* Try to emulate it if we should. */ |
820 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
821 | switch (emulate_instruction(regs)) { |
822 | case 0: | |
823 | regs->nip += 4; | |
824 | emulate_single_step(regs); | |
8dad3f92 | 825 | return; |
14cf11af PM |
826 | case -EFAULT: |
827 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 828 | return; |
14cf11af PM |
829 | } |
830 | } | |
8dad3f92 PM |
831 | |
832 | if (reason & REASON_PRIVILEGED) | |
833 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
834 | else | |
835 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
836 | } |
837 | ||
dc1c1ca3 | 838 | void alignment_exception(struct pt_regs *regs) |
14cf11af PM |
839 | { |
840 | int fixed; | |
841 | ||
842 | fixed = fix_alignment(regs); | |
843 | ||
844 | if (fixed == 1) { | |
845 | regs->nip += 4; /* skip over emulated instruction */ | |
846 | emulate_single_step(regs); | |
847 | return; | |
848 | } | |
849 | ||
dc1c1ca3 | 850 | /* Operand address was bad */ |
14cf11af PM |
851 | if (fixed == -EFAULT) { |
852 | if (user_mode(regs)) | |
8dad3f92 | 853 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); |
14cf11af PM |
854 | else |
855 | /* Search exception table */ | |
856 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
857 | return; | |
858 | } | |
8dad3f92 | 859 | _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); |
14cf11af PM |
860 | } |
861 | ||
862 | void StackOverflow(struct pt_regs *regs) | |
863 | { | |
864 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
865 | current, regs->gpr[1]); | |
866 | debugger(regs); | |
867 | show_regs(regs); | |
868 | panic("kernel stack overflow"); | |
869 | } | |
870 | ||
871 | void nonrecoverable_exception(struct pt_regs *regs) | |
872 | { | |
873 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
874 | regs->nip, regs->msr); | |
875 | debugger(regs); | |
876 | die("nonrecoverable exception", regs, SIGKILL); | |
877 | } | |
878 | ||
879 | void trace_syscall(struct pt_regs *regs) | |
880 | { | |
881 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
882 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
883 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
884 | } | |
dc1c1ca3 | 885 | |
dc1c1ca3 SR |
886 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
887 | { | |
888 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
889 | "%lx at %lx\n", regs->trap, regs->nip); | |
890 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
891 | } | |
dc1c1ca3 SR |
892 | |
893 | void altivec_unavailable_exception(struct pt_regs *regs) | |
894 | { | |
8dad3f92 | 895 | #if !defined(CONFIG_ALTIVEC) |
dc1c1ca3 SR |
896 | if (user_mode(regs)) { |
897 | /* A user program has executed an altivec instruction, | |
898 | but this kernel doesn't support altivec. */ | |
899 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
900 | return; | |
901 | } | |
902 | #endif | |
dc1c1ca3 SR |
903 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
904 | "%lx at %lx\n", regs->trap, regs->nip); | |
905 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
906 | } |
907 | ||
dc1c1ca3 SR |
908 | void performance_monitor_exception(struct pt_regs *regs) |
909 | { | |
910 | perf_irq(regs); | |
911 | } | |
dc1c1ca3 | 912 | |
8dad3f92 | 913 | #ifdef CONFIG_8xx |
14cf11af PM |
914 | void SoftwareEmulation(struct pt_regs *regs) |
915 | { | |
916 | extern int do_mathemu(struct pt_regs *); | |
917 | extern int Soft_emulate_8xx(struct pt_regs *); | |
918 | int errcode; | |
919 | ||
920 | CHECK_FULL_REGS(regs); | |
921 | ||
922 | if (!user_mode(regs)) { | |
923 | debugger(regs); | |
924 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
925 | } | |
926 | ||
927 | #ifdef CONFIG_MATH_EMULATION | |
928 | errcode = do_mathemu(regs); | |
929 | #else | |
930 | errcode = Soft_emulate_8xx(regs); | |
931 | #endif | |
932 | if (errcode) { | |
933 | if (errcode > 0) | |
934 | _exception(SIGFPE, regs, 0, 0); | |
935 | else if (errcode == -EFAULT) | |
936 | _exception(SIGSEGV, regs, 0, 0); | |
937 | else | |
938 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
939 | } else | |
940 | emulate_single_step(regs); | |
941 | } | |
8dad3f92 | 942 | #endif /* CONFIG_8xx */ |
14cf11af PM |
943 | |
944 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
945 | ||
946 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
947 | { | |
948 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
949 | regs->msr &= ~MSR_DE; | |
950 | if (user_mode(regs)) { | |
951 | current->thread.dbcr0 &= ~DBCR0_IC; | |
952 | } else { | |
953 | /* Disable instruction completion */ | |
954 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
955 | /* Clear the instruction completion event */ | |
956 | mtspr(SPRN_DBSR, DBSR_IC); | |
957 | if (debugger_sstep(regs)) | |
958 | return; | |
959 | } | |
960 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
961 | } | |
962 | } | |
963 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
964 | ||
965 | #if !defined(CONFIG_TAU_INT) | |
966 | void TAUException(struct pt_regs *regs) | |
967 | { | |
968 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
969 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
970 | } | |
971 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
972 | |
973 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 974 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
975 | { |
976 | int err; | |
977 | ||
14cf11af PM |
978 | if (!user_mode(regs)) { |
979 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
980 | " at %lx\n", regs->nip); | |
8dad3f92 | 981 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
982 | } |
983 | ||
dc1c1ca3 | 984 | flush_altivec_to_thread(current); |
dc1c1ca3 | 985 | |
14cf11af PM |
986 | err = emulate_altivec(regs); |
987 | if (err == 0) { | |
988 | regs->nip += 4; /* skip emulated instruction */ | |
989 | emulate_single_step(regs); | |
990 | return; | |
991 | } | |
992 | ||
993 | if (err == -EFAULT) { | |
994 | /* got an error reading the instruction */ | |
995 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
996 | } else { | |
997 | /* didn't recognize the instruction */ | |
998 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
999 | if (printk_ratelimit()) | |
1000 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1001 | "in %s at %lx\n", current->comm, regs->nip); | |
1002 | current->thread.vscr.u[3] |= 0x10000; | |
1003 | } | |
1004 | } | |
1005 | #endif /* CONFIG_ALTIVEC */ | |
1006 | ||
14cf11af PM |
1007 | #ifdef CONFIG_FSL_BOOKE |
1008 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1009 | unsigned long error_code) | |
1010 | { | |
1011 | /* We treat cache locking instructions from the user | |
1012 | * as priv ops, in the future we could try to do | |
1013 | * something smarter | |
1014 | */ | |
1015 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1016 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1017 | return; | |
1018 | } | |
1019 | #endif /* CONFIG_FSL_BOOKE */ | |
1020 | ||
1021 | #ifdef CONFIG_SPE | |
1022 | void SPEFloatingPointException(struct pt_regs *regs) | |
1023 | { | |
1024 | unsigned long spefscr; | |
1025 | int fpexc_mode; | |
1026 | int code = 0; | |
1027 | ||
1028 | spefscr = current->thread.spefscr; | |
1029 | fpexc_mode = current->thread.fpexc_mode; | |
1030 | ||
1031 | /* Hardware does not neccessarily set sticky | |
1032 | * underflow/overflow/invalid flags */ | |
1033 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
1034 | code = FPE_FLTOVF; | |
1035 | spefscr |= SPEFSCR_FOVFS; | |
1036 | } | |
1037 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1038 | code = FPE_FLTUND; | |
1039 | spefscr |= SPEFSCR_FUNFS; | |
1040 | } | |
1041 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1042 | code = FPE_FLTDIV; | |
1043 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1044 | code = FPE_FLTINV; | |
1045 | spefscr |= SPEFSCR_FINVS; | |
1046 | } | |
1047 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1048 | code = FPE_FLTRES; | |
1049 | ||
1050 | current->thread.spefscr = spefscr; | |
1051 | ||
1052 | _exception(SIGFPE, regs, code, regs->nip); | |
1053 | return; | |
1054 | } | |
1055 | #endif | |
1056 | ||
dc1c1ca3 SR |
1057 | /* |
1058 | * We enter here if we get an unrecoverable exception, that is, one | |
1059 | * that happened at a point where the RI (recoverable interrupt) bit | |
1060 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1061 | * we therefore lost state by taking this exception. | |
1062 | */ | |
1063 | void unrecoverable_exception(struct pt_regs *regs) | |
1064 | { | |
1065 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1066 | regs->trap, regs->nip); | |
1067 | die("Unrecoverable exception", regs, SIGABRT); | |
1068 | } | |
dc1c1ca3 | 1069 | |
14cf11af PM |
1070 | #ifdef CONFIG_BOOKE_WDT |
1071 | /* | |
1072 | * Default handler for a Watchdog exception, | |
1073 | * spins until a reboot occurs | |
1074 | */ | |
1075 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1076 | { | |
1077 | /* Generic WatchdogHandler, implement your own */ | |
1078 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1079 | return; | |
1080 | } | |
1081 | ||
1082 | void WatchdogException(struct pt_regs *regs) | |
1083 | { | |
1084 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1085 | WatchdogHandler(regs); | |
1086 | } | |
1087 | #endif | |
dc1c1ca3 | 1088 | |
dc1c1ca3 SR |
1089 | /* |
1090 | * We enter here if we discover during exception entry that we are | |
1091 | * running in supervisor mode with a userspace value in the stack pointer. | |
1092 | */ | |
1093 | void kernel_bad_stack(struct pt_regs *regs) | |
1094 | { | |
1095 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1096 | regs->gpr[1], regs->nip); | |
1097 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1098 | } | |
14cf11af PM |
1099 | |
1100 | void __init trap_init(void) | |
1101 | { | |
1102 | } |