Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af | 25 | #include <linux/user.h> |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
76462232 | 37 | #include <linux/ratelimit.h> |
14cf11af | 38 | |
80947e7c | 39 | #include <asm/emulated_ops.h> |
14cf11af PM |
40 | #include <asm/pgtable.h> |
41 | #include <asm/uaccess.h> | |
14cf11af | 42 | #include <asm/io.h> |
86417780 PM |
43 | #include <asm/machdep.h> |
44 | #include <asm/rtas.h> | |
f7f6f4fe | 45 | #include <asm/pmc.h> |
dc1c1ca3 | 46 | #ifdef CONFIG_PPC32 |
14cf11af | 47 | #include <asm/reg.h> |
86417780 | 48 | #endif |
14cf11af PM |
49 | #ifdef CONFIG_PMAC_BACKLIGHT |
50 | #include <asm/backlight.h> | |
51 | #endif | |
dc1c1ca3 | 52 | #ifdef CONFIG_PPC64 |
86417780 | 53 | #include <asm/firmware.h> |
dc1c1ca3 | 54 | #include <asm/processor.h> |
dc1c1ca3 | 55 | #endif |
c0ce7d08 | 56 | #include <asm/kexec.h> |
16c57b36 | 57 | #include <asm/ppc-opcode.h> |
cce1f106 | 58 | #include <asm/rio.h> |
ebaeb5ae | 59 | #include <asm/fadump.h> |
ae3a197e DH |
60 | #include <asm/switch_to.h> |
61 | #include <asm/debug.h> | |
dc1c1ca3 | 62 | |
7dbb922c | 63 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
64 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
65 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
67 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
68 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
69 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
70 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
71 | |
72 | EXPORT_SYMBOL(__debugger); | |
73 | EXPORT_SYMBOL(__debugger_ipi); | |
74 | EXPORT_SYMBOL(__debugger_bpt); | |
75 | EXPORT_SYMBOL(__debugger_sstep); | |
76 | EXPORT_SYMBOL(__debugger_iabr_match); | |
77 | EXPORT_SYMBOL(__debugger_dabr_match); | |
78 | EXPORT_SYMBOL(__debugger_fault_handler); | |
79 | #endif | |
80 | ||
14cf11af PM |
81 | /* |
82 | * Trap & Exception support | |
83 | */ | |
84 | ||
6031d9d9 | 85 | #ifdef CONFIG_PMAC_BACKLIGHT |
86 | static void pmac_backlight_unblank(void) | |
87 | { | |
88 | mutex_lock(&pmac_backlight_mutex); | |
89 | if (pmac_backlight) { | |
90 | struct backlight_properties *props; | |
91 | ||
92 | props = &pmac_backlight->props; | |
93 | props->brightness = props->max_brightness; | |
94 | props->power = FB_BLANK_UNBLANK; | |
95 | backlight_update_status(pmac_backlight); | |
96 | } | |
97 | mutex_unlock(&pmac_backlight_mutex); | |
98 | } | |
99 | #else | |
100 | static inline void pmac_backlight_unblank(void) { } | |
101 | #endif | |
102 | ||
760ca4dc AB |
103 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
104 | static int die_owner = -1; | |
105 | static unsigned int die_nest_count; | |
106 | static int die_counter; | |
107 | ||
108 | static unsigned __kprobes long oops_begin(struct pt_regs *regs) | |
14cf11af | 109 | { |
760ca4dc | 110 | int cpu; |
34c2a14f | 111 | unsigned long flags; |
14cf11af PM |
112 | |
113 | if (debugger(regs)) | |
114 | return 1; | |
115 | ||
293e4688 | 116 | oops_enter(); |
117 | ||
760ca4dc AB |
118 | /* racy, but better than risking deadlock. */ |
119 | raw_local_irq_save(flags); | |
120 | cpu = smp_processor_id(); | |
121 | if (!arch_spin_trylock(&die_lock)) { | |
122 | if (cpu == die_owner) | |
123 | /* nested oops. should stop eventually */; | |
124 | else | |
125 | arch_spin_lock(&die_lock); | |
34c2a14f | 126 | } |
760ca4dc AB |
127 | die_nest_count++; |
128 | die_owner = cpu; | |
129 | console_verbose(); | |
130 | bust_spinlocks(1); | |
131 | if (machine_is(powermac)) | |
132 | pmac_backlight_unblank(); | |
133 | return flags; | |
134 | } | |
e8222502 | 135 | |
760ca4dc AB |
136 | static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, |
137 | int signr) | |
138 | { | |
14cf11af | 139 | bust_spinlocks(0); |
760ca4dc | 140 | die_owner = -1; |
bcdcd8e7 | 141 | add_taint(TAINT_DIE); |
760ca4dc | 142 | die_nest_count--; |
58154c8c AB |
143 | oops_exit(); |
144 | printk("\n"); | |
760ca4dc AB |
145 | if (!die_nest_count) |
146 | /* Nest count reaches zero, release the lock. */ | |
147 | arch_spin_unlock(&die_lock); | |
148 | raw_local_irq_restore(flags); | |
cc532915 | 149 | |
ebaeb5ae MS |
150 | crash_fadump(regs, "die oops"); |
151 | ||
9b00ac06 AB |
152 | /* |
153 | * A system reset (0x100) is a request to dump, so we always send | |
154 | * it through the crashdump code. | |
155 | */ | |
156 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 157 | crash_kexec(regs); |
9b00ac06 AB |
158 | |
159 | /* | |
160 | * We aren't the primary crash CPU. We need to send it | |
161 | * to a holding pattern to avoid it ending up in the panic | |
162 | * code. | |
163 | */ | |
164 | crash_kexec_secondary(regs); | |
165 | } | |
14cf11af | 166 | |
760ca4dc AB |
167 | if (!signr) |
168 | return; | |
169 | ||
58154c8c AB |
170 | /* |
171 | * While our oops output is serialised by a spinlock, output | |
172 | * from panic() called below can race and corrupt it. If we | |
173 | * know we are going to panic, delay for 1 second so we have a | |
174 | * chance to get clean backtraces from all CPUs that are oopsing. | |
175 | */ | |
176 | if (in_interrupt() || panic_on_oops || !current->pid || | |
177 | is_global_init(current)) { | |
178 | mdelay(MSEC_PER_SEC); | |
179 | } | |
180 | ||
14cf11af PM |
181 | if (in_interrupt()) |
182 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 183 | if (panic_on_oops) |
012c437d | 184 | panic("Fatal exception"); |
760ca4dc AB |
185 | do_exit(signr); |
186 | } | |
cea6a4ba | 187 | |
760ca4dc AB |
188 | static int __kprobes __die(const char *str, struct pt_regs *regs, long err) |
189 | { | |
190 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
191 | #ifdef CONFIG_PREEMPT | |
192 | printk("PREEMPT "); | |
193 | #endif | |
194 | #ifdef CONFIG_SMP | |
195 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
196 | #endif | |
197 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
198 | printk("DEBUG_PAGEALLOC "); | |
199 | #endif | |
200 | #ifdef CONFIG_NUMA | |
201 | printk("NUMA "); | |
202 | #endif | |
203 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); | |
204 | ||
205 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
206 | return 1; | |
207 | ||
208 | print_modules(); | |
209 | show_regs(regs); | |
14cf11af PM |
210 | |
211 | return 0; | |
212 | } | |
213 | ||
760ca4dc AB |
214 | void die(const char *str, struct pt_regs *regs, long err) |
215 | { | |
216 | unsigned long flags = oops_begin(regs); | |
217 | ||
218 | if (__die(str, regs, err)) | |
219 | err = 0; | |
220 | oops_end(flags, regs, err); | |
221 | } | |
222 | ||
25baa35b ON |
223 | void user_single_step_siginfo(struct task_struct *tsk, |
224 | struct pt_regs *regs, siginfo_t *info) | |
225 | { | |
226 | memset(info, 0, sizeof(*info)); | |
227 | info->si_signo = SIGTRAP; | |
228 | info->si_code = TRAP_TRACE; | |
229 | info->si_addr = (void __user *)regs->nip; | |
230 | } | |
231 | ||
14cf11af PM |
232 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
233 | { | |
234 | siginfo_t info; | |
d0c3d534 OJ |
235 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
236 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
237 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
238 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
239 | |
240 | if (!user_mode(regs)) { | |
760ca4dc AB |
241 | die("Exception in kernel mode", regs, signr); |
242 | return; | |
243 | } | |
244 | ||
245 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
246 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
247 | current->comm, current->pid, signr, | |
248 | addr, regs->nip, regs->link, code); | |
249 | } | |
14cf11af | 250 | |
a3512b2d | 251 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
252 | local_irq_enable(); |
253 | ||
14cf11af PM |
254 | memset(&info, 0, sizeof(info)); |
255 | info.si_signo = signr; | |
256 | info.si_code = code; | |
257 | info.si_addr = (void __user *) addr; | |
258 | force_sig_info(signr, &info, current); | |
14cf11af PM |
259 | } |
260 | ||
261 | #ifdef CONFIG_PPC64 | |
262 | void system_reset_exception(struct pt_regs *regs) | |
263 | { | |
264 | /* See if any machine dependent calls */ | |
c902be71 AB |
265 | if (ppc_md.system_reset_exception) { |
266 | if (ppc_md.system_reset_exception(regs)) | |
267 | return; | |
268 | } | |
14cf11af | 269 | |
8dad3f92 | 270 | die("System Reset", regs, SIGABRT); |
14cf11af PM |
271 | |
272 | /* Must die if the interrupt is not recoverable */ | |
273 | if (!(regs->msr & MSR_RI)) | |
274 | panic("Unrecoverable System Reset"); | |
275 | ||
276 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
277 | } | |
278 | #endif | |
279 | ||
280 | /* | |
281 | * I/O accesses can cause machine checks on powermacs. | |
282 | * Check if the NIP corresponds to the address of a sync | |
283 | * instruction for which there is an entry in the exception | |
284 | * table. | |
285 | * Note that the 601 only takes a machine check on TEA | |
286 | * (transfer error ack) signal assertion, and does not | |
287 | * set any of the top 16 bits of SRR1. | |
288 | * -- paulus. | |
289 | */ | |
290 | static inline int check_io_access(struct pt_regs *regs) | |
291 | { | |
68a64357 | 292 | #ifdef CONFIG_PPC32 |
14cf11af PM |
293 | unsigned long msr = regs->msr; |
294 | const struct exception_table_entry *entry; | |
295 | unsigned int *nip = (unsigned int *)regs->nip; | |
296 | ||
297 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
298 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
299 | /* | |
300 | * Check that it's a sync instruction, or somewhere | |
301 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
302 | * As the address is in the exception table | |
303 | * we should be able to read the instr there. | |
304 | * For the debug message, we look at the preceding | |
305 | * load or store. | |
306 | */ | |
307 | if (*nip == 0x60000000) /* nop */ | |
308 | nip -= 2; | |
309 | else if (*nip == 0x4c00012c) /* isync */ | |
310 | --nip; | |
311 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
312 | /* sync or twi */ | |
313 | unsigned int rb; | |
314 | ||
315 | --nip; | |
316 | rb = (*nip >> 11) & 0x1f; | |
317 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
318 | (*nip & 0x100)? "OUT to": "IN from", | |
319 | regs->gpr[rb] - _IO_BASE, nip); | |
320 | regs->msr |= MSR_RI; | |
321 | regs->nip = entry->fixup; | |
322 | return 1; | |
323 | } | |
324 | } | |
68a64357 | 325 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
326 | return 0; |
327 | } | |
328 | ||
172ae2e7 | 329 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
330 | /* On 4xx, the reason for the machine check or program exception |
331 | is in the ESR. */ | |
332 | #define get_reason(regs) ((regs)->dsisr) | |
333 | #ifndef CONFIG_FSL_BOOKE | |
334 | #define get_mc_reason(regs) ((regs)->dsisr) | |
335 | #else | |
fe04b112 | 336 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
337 | #endif |
338 | #define REASON_FP ESR_FP | |
339 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
340 | #define REASON_PRIVILEGED ESR_PPR | |
341 | #define REASON_TRAP ESR_PTR | |
342 | ||
343 | /* single-step stuff */ | |
344 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
345 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
346 | ||
347 | #else | |
348 | /* On non-4xx, the reason for the machine check or program | |
349 | exception is in the MSR. */ | |
350 | #define get_reason(regs) ((regs)->msr) | |
351 | #define get_mc_reason(regs) ((regs)->msr) | |
352 | #define REASON_FP 0x100000 | |
353 | #define REASON_ILLEGAL 0x80000 | |
354 | #define REASON_PRIVILEGED 0x40000 | |
355 | #define REASON_TRAP 0x20000 | |
356 | ||
357 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
358 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
359 | #endif | |
360 | ||
47c0bd1a BH |
361 | #if defined(CONFIG_4xx) |
362 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 363 | { |
1a6a4ffe | 364 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 365 | |
14cf11af PM |
366 | if (reason & ESR_IMCP) { |
367 | printk("Instruction"); | |
368 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
369 | } else | |
370 | printk("Data"); | |
371 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
372 | |
373 | return 0; | |
374 | } | |
375 | ||
376 | int machine_check_440A(struct pt_regs *regs) | |
377 | { | |
378 | unsigned long reason = get_mc_reason(regs); | |
379 | ||
14cf11af PM |
380 | printk("Machine check in kernel mode.\n"); |
381 | if (reason & ESR_IMCP){ | |
382 | printk("Instruction Synchronous Machine Check exception\n"); | |
383 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
384 | } | |
385 | else { | |
386 | u32 mcsr = mfspr(SPRN_MCSR); | |
387 | if (mcsr & MCSR_IB) | |
388 | printk("Instruction Read PLB Error\n"); | |
389 | if (mcsr & MCSR_DRB) | |
390 | printk("Data Read PLB Error\n"); | |
391 | if (mcsr & MCSR_DWB) | |
392 | printk("Data Write PLB Error\n"); | |
393 | if (mcsr & MCSR_TLBP) | |
394 | printk("TLB Parity Error\n"); | |
395 | if (mcsr & MCSR_ICP){ | |
396 | flush_instruction_cache(); | |
397 | printk("I-Cache Parity Error\n"); | |
398 | } | |
399 | if (mcsr & MCSR_DCSP) | |
400 | printk("D-Cache Search Parity Error\n"); | |
401 | if (mcsr & MCSR_DCFP) | |
402 | printk("D-Cache Flush Parity Error\n"); | |
403 | if (mcsr & MCSR_IMPE) | |
404 | printk("Machine Check exception is imprecise\n"); | |
405 | ||
406 | /* Clear MCSR */ | |
407 | mtspr(SPRN_MCSR, mcsr); | |
408 | } | |
47c0bd1a BH |
409 | return 0; |
410 | } | |
fc5e7097 DK |
411 | |
412 | int machine_check_47x(struct pt_regs *regs) | |
413 | { | |
414 | unsigned long reason = get_mc_reason(regs); | |
415 | u32 mcsr; | |
416 | ||
417 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
418 | if (reason & ESR_IMCP) { | |
419 | printk(KERN_ERR | |
420 | "Instruction Synchronous Machine Check exception\n"); | |
421 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
422 | return 0; | |
423 | } | |
424 | mcsr = mfspr(SPRN_MCSR); | |
425 | if (mcsr & MCSR_IB) | |
426 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
427 | if (mcsr & MCSR_DRB) | |
428 | printk(KERN_ERR "Data Read PLB Error\n"); | |
429 | if (mcsr & MCSR_DWB) | |
430 | printk(KERN_ERR "Data Write PLB Error\n"); | |
431 | if (mcsr & MCSR_TLBP) | |
432 | printk(KERN_ERR "TLB Parity Error\n"); | |
433 | if (mcsr & MCSR_ICP) { | |
434 | flush_instruction_cache(); | |
435 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
436 | } | |
437 | if (mcsr & MCSR_DCSP) | |
438 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
439 | if (mcsr & PPC47x_MCSR_GPR) | |
440 | printk(KERN_ERR "GPR Parity Error\n"); | |
441 | if (mcsr & PPC47x_MCSR_FPR) | |
442 | printk(KERN_ERR "FPR Parity Error\n"); | |
443 | if (mcsr & PPC47x_MCSR_IPR) | |
444 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
445 | ||
446 | /* Clear MCSR */ | |
447 | mtspr(SPRN_MCSR, mcsr); | |
448 | ||
449 | return 0; | |
450 | } | |
47c0bd1a | 451 | #elif defined(CONFIG_E500) |
fe04b112 SW |
452 | int machine_check_e500mc(struct pt_regs *regs) |
453 | { | |
454 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
455 | unsigned long reason = mcsr; | |
456 | int recoverable = 1; | |
457 | ||
82a9a480 | 458 | if (reason & MCSR_LD) { |
cce1f106 SX |
459 | recoverable = fsl_rio_mcheck_exception(regs); |
460 | if (recoverable == 1) | |
461 | goto silent_out; | |
462 | } | |
463 | ||
fe04b112 SW |
464 | printk("Machine check in kernel mode.\n"); |
465 | printk("Caused by (from MCSR=%lx): ", reason); | |
466 | ||
467 | if (reason & MCSR_MCP) | |
468 | printk("Machine Check Signal\n"); | |
469 | ||
470 | if (reason & MCSR_ICPERR) { | |
471 | printk("Instruction Cache Parity Error\n"); | |
472 | ||
473 | /* | |
474 | * This is recoverable by invalidating the i-cache. | |
475 | */ | |
476 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
477 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
478 | ; | |
479 | ||
480 | /* | |
481 | * This will generally be accompanied by an instruction | |
482 | * fetch error report -- only treat MCSR_IF as fatal | |
483 | * if it wasn't due to an L1 parity error. | |
484 | */ | |
485 | reason &= ~MCSR_IF; | |
486 | } | |
487 | ||
488 | if (reason & MCSR_DCPERR_MC) { | |
489 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
490 | |
491 | /* | |
492 | * In write shadow mode we auto-recover from the error, but it | |
493 | * may still get logged and cause a machine check. We should | |
494 | * only treat the non-write shadow case as non-recoverable. | |
495 | */ | |
496 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
497 | recoverable = 0; | |
fe04b112 SW |
498 | } |
499 | ||
500 | if (reason & MCSR_L2MMU_MHIT) { | |
501 | printk("Hit on multiple TLB entries\n"); | |
502 | recoverable = 0; | |
503 | } | |
504 | ||
505 | if (reason & MCSR_NMI) | |
506 | printk("Non-maskable interrupt\n"); | |
507 | ||
508 | if (reason & MCSR_IF) { | |
509 | printk("Instruction Fetch Error Report\n"); | |
510 | recoverable = 0; | |
511 | } | |
512 | ||
513 | if (reason & MCSR_LD) { | |
514 | printk("Load Error Report\n"); | |
515 | recoverable = 0; | |
516 | } | |
517 | ||
518 | if (reason & MCSR_ST) { | |
519 | printk("Store Error Report\n"); | |
520 | recoverable = 0; | |
521 | } | |
522 | ||
523 | if (reason & MCSR_LDG) { | |
524 | printk("Guarded Load Error Report\n"); | |
525 | recoverable = 0; | |
526 | } | |
527 | ||
528 | if (reason & MCSR_TLBSYNC) | |
529 | printk("Simultaneous tlbsync operations\n"); | |
530 | ||
531 | if (reason & MCSR_BSL2_ERR) { | |
532 | printk("Level 2 Cache Error\n"); | |
533 | recoverable = 0; | |
534 | } | |
535 | ||
536 | if (reason & MCSR_MAV) { | |
537 | u64 addr; | |
538 | ||
539 | addr = mfspr(SPRN_MCAR); | |
540 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
541 | ||
542 | printk("Machine Check %s Address: %#llx\n", | |
543 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
544 | } | |
545 | ||
cce1f106 | 546 | silent_out: |
fe04b112 SW |
547 | mtspr(SPRN_MCSR, mcsr); |
548 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
549 | } | |
550 | ||
47c0bd1a BH |
551 | int machine_check_e500(struct pt_regs *regs) |
552 | { | |
553 | unsigned long reason = get_mc_reason(regs); | |
554 | ||
cce1f106 SX |
555 | if (reason & MCSR_BUS_RBERR) { |
556 | if (fsl_rio_mcheck_exception(regs)) | |
557 | return 1; | |
558 | } | |
559 | ||
14cf11af PM |
560 | printk("Machine check in kernel mode.\n"); |
561 | printk("Caused by (from MCSR=%lx): ", reason); | |
562 | ||
563 | if (reason & MCSR_MCP) | |
564 | printk("Machine Check Signal\n"); | |
565 | if (reason & MCSR_ICPERR) | |
566 | printk("Instruction Cache Parity Error\n"); | |
567 | if (reason & MCSR_DCP_PERR) | |
568 | printk("Data Cache Push Parity Error\n"); | |
569 | if (reason & MCSR_DCPERR) | |
570 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
571 | if (reason & MCSR_BUS_IAERR) |
572 | printk("Bus - Instruction Address Error\n"); | |
573 | if (reason & MCSR_BUS_RAERR) | |
574 | printk("Bus - Read Address Error\n"); | |
575 | if (reason & MCSR_BUS_WAERR) | |
576 | printk("Bus - Write Address Error\n"); | |
577 | if (reason & MCSR_BUS_IBERR) | |
578 | printk("Bus - Instruction Data Error\n"); | |
579 | if (reason & MCSR_BUS_RBERR) | |
580 | printk("Bus - Read Data Bus Error\n"); | |
581 | if (reason & MCSR_BUS_WBERR) | |
582 | printk("Bus - Read Data Bus Error\n"); | |
583 | if (reason & MCSR_BUS_IPERR) | |
584 | printk("Bus - Instruction Parity Error\n"); | |
585 | if (reason & MCSR_BUS_RPERR) | |
586 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
587 | |
588 | return 0; | |
589 | } | |
4490c06b KG |
590 | |
591 | int machine_check_generic(struct pt_regs *regs) | |
592 | { | |
593 | return 0; | |
594 | } | |
47c0bd1a BH |
595 | #elif defined(CONFIG_E200) |
596 | int machine_check_e200(struct pt_regs *regs) | |
597 | { | |
598 | unsigned long reason = get_mc_reason(regs); | |
599 | ||
14cf11af PM |
600 | printk("Machine check in kernel mode.\n"); |
601 | printk("Caused by (from MCSR=%lx): ", reason); | |
602 | ||
603 | if (reason & MCSR_MCP) | |
604 | printk("Machine Check Signal\n"); | |
605 | if (reason & MCSR_CP_PERR) | |
606 | printk("Cache Push Parity Error\n"); | |
607 | if (reason & MCSR_CPERR) | |
608 | printk("Cache Parity Error\n"); | |
609 | if (reason & MCSR_EXCP_ERR) | |
610 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
611 | if (reason & MCSR_BUS_IRERR) | |
612 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
613 | if (reason & MCSR_BUS_DRERR) | |
614 | printk("Bus - Read Bus Error on data load\n"); | |
615 | if (reason & MCSR_BUS_WRERR) | |
616 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
617 | |
618 | return 0; | |
619 | } | |
620 | #else | |
621 | int machine_check_generic(struct pt_regs *regs) | |
622 | { | |
623 | unsigned long reason = get_mc_reason(regs); | |
624 | ||
14cf11af PM |
625 | printk("Machine check in kernel mode.\n"); |
626 | printk("Caused by (from SRR1=%lx): ", reason); | |
627 | switch (reason & 0x601F0000) { | |
628 | case 0x80000: | |
629 | printk("Machine check signal\n"); | |
630 | break; | |
631 | case 0: /* for 601 */ | |
632 | case 0x40000: | |
633 | case 0x140000: /* 7450 MSS error and TEA */ | |
634 | printk("Transfer error ack signal\n"); | |
635 | break; | |
636 | case 0x20000: | |
637 | printk("Data parity error signal\n"); | |
638 | break; | |
639 | case 0x10000: | |
640 | printk("Address parity error signal\n"); | |
641 | break; | |
642 | case 0x20000000: | |
643 | printk("L1 Data Cache error\n"); | |
644 | break; | |
645 | case 0x40000000: | |
646 | printk("L1 Instruction Cache error\n"); | |
647 | break; | |
648 | case 0x00100000: | |
649 | printk("L2 data cache parity error\n"); | |
650 | break; | |
651 | default: | |
652 | printk("Unknown values in msr\n"); | |
653 | } | |
75918a4b OJ |
654 | return 0; |
655 | } | |
47c0bd1a | 656 | #endif /* everything else */ |
75918a4b OJ |
657 | |
658 | void machine_check_exception(struct pt_regs *regs) | |
659 | { | |
660 | int recover = 0; | |
661 | ||
89713ed1 AB |
662 | __get_cpu_var(irq_stat).mce_exceptions++; |
663 | ||
47c0bd1a BH |
664 | /* See if any machine dependent calls. In theory, we would want |
665 | * to call the CPU first, and call the ppc_md. one if the CPU | |
666 | * one returns a positive number. However there is existing code | |
667 | * that assumes the board gets a first chance, so let's keep it | |
668 | * that way for now and fix things later. --BenH. | |
669 | */ | |
75918a4b OJ |
670 | if (ppc_md.machine_check_exception) |
671 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
672 | else if (cur_cpu_spec->machine_check) |
673 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 674 | |
47c0bd1a | 675 | if (recover > 0) |
75918a4b OJ |
676 | return; |
677 | ||
75918a4b | 678 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
47c0bd1a BH |
679 | /* the qspan pci read routines can cause machine checks -- Cort |
680 | * | |
681 | * yuck !!! that totally needs to go away ! There are better ways | |
682 | * to deal with that than having a wart in the mcheck handler. | |
683 | * -- BenH | |
684 | */ | |
75918a4b OJ |
685 | bad_page_fault(regs, regs->dar, SIGBUS); |
686 | return; | |
687 | #endif | |
688 | ||
a443506b | 689 | if (debugger_fault_handler(regs)) |
75918a4b | 690 | return; |
75918a4b OJ |
691 | |
692 | if (check_io_access(regs)) | |
693 | return; | |
694 | ||
8dad3f92 | 695 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
696 | |
697 | /* Must die if the interrupt is not recoverable */ | |
698 | if (!(regs->msr & MSR_RI)) | |
699 | panic("Unrecoverable Machine check"); | |
700 | } | |
701 | ||
702 | void SMIException(struct pt_regs *regs) | |
703 | { | |
704 | die("System Management Interrupt", regs, SIGABRT); | |
705 | } | |
706 | ||
dc1c1ca3 | 707 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
708 | { |
709 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
710 | regs->nip, regs->msr, regs->trap); | |
711 | ||
712 | _exception(SIGTRAP, regs, 0, 0); | |
713 | } | |
714 | ||
dc1c1ca3 | 715 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
716 | { |
717 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
718 | 5, SIGTRAP) == NOTIFY_STOP) | |
719 | return; | |
720 | if (debugger_iabr_match(regs)) | |
721 | return; | |
722 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
723 | } | |
724 | ||
725 | void RunModeException(struct pt_regs *regs) | |
726 | { | |
727 | _exception(SIGTRAP, regs, 0, 0); | |
728 | } | |
729 | ||
8dad3f92 | 730 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af | 731 | { |
2538c2d0 | 732 | clear_single_step(regs); |
14cf11af PM |
733 | |
734 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
735 | 5, SIGTRAP) == NOTIFY_STOP) | |
736 | return; | |
737 | if (debugger_sstep(regs)) | |
738 | return; | |
739 | ||
740 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
741 | } | |
742 | ||
743 | /* | |
744 | * After we have successfully emulated an instruction, we have to | |
745 | * check if the instruction was being single-stepped, and if so, | |
746 | * pretend we got a single-step exception. This was pointed out | |
747 | * by Kumar Gala. -- paulus | |
748 | */ | |
8dad3f92 | 749 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 750 | { |
2538c2d0 P |
751 | if (single_stepping(regs)) |
752 | single_step_exception(regs); | |
14cf11af PM |
753 | } |
754 | ||
5fad293b | 755 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 756 | { |
5fad293b | 757 | int ret = 0; |
dc1c1ca3 SR |
758 | |
759 | /* Invalid operation */ | |
760 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 761 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
762 | |
763 | /* Overflow */ | |
764 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 765 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
766 | |
767 | /* Underflow */ | |
768 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 769 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
770 | |
771 | /* Divide by zero */ | |
772 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 773 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
774 | |
775 | /* Inexact result */ | |
776 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
777 | ret = FPE_FLTRES; |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
782 | static void parse_fpe(struct pt_regs *regs) | |
783 | { | |
784 | int code = 0; | |
785 | ||
786 | flush_fp_to_thread(current); | |
787 | ||
788 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
789 | |
790 | _exception(SIGFPE, regs, code, regs->nip); | |
791 | } | |
792 | ||
793 | /* | |
794 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
795 | * provide the PVR to user applications using the mfspr rd, PVR. |
796 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
797 | * memory access caused an access fault. Return zero on success. | |
798 | * | |
799 | * There are a couple of ways to do this, either "decode" the instruction | |
800 | * or directly match lots of bits. In this case, matching lots of | |
801 | * bits is faster and easier. | |
86417780 | 802 | * |
14cf11af | 803 | */ |
14cf11af PM |
804 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
805 | { | |
806 | u8 rT = (instword >> 21) & 0x1f; | |
807 | u8 rA = (instword >> 16) & 0x1f; | |
808 | u8 NB_RB = (instword >> 11) & 0x1f; | |
809 | u32 num_bytes; | |
810 | unsigned long EA; | |
811 | int pos = 0; | |
812 | ||
813 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 814 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
815 | if ((rT == rA) || (rT == NB_RB)) |
816 | return -EINVAL; | |
817 | ||
818 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
819 | ||
16c57b36 KG |
820 | switch (instword & PPC_INST_STRING_MASK) { |
821 | case PPC_INST_LSWX: | |
822 | case PPC_INST_STSWX: | |
14cf11af PM |
823 | EA += NB_RB; |
824 | num_bytes = regs->xer & 0x7f; | |
825 | break; | |
16c57b36 KG |
826 | case PPC_INST_LSWI: |
827 | case PPC_INST_STSWI: | |
14cf11af PM |
828 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
829 | break; | |
830 | default: | |
831 | return -EINVAL; | |
832 | } | |
833 | ||
834 | while (num_bytes != 0) | |
835 | { | |
836 | u8 val; | |
837 | u32 shift = 8 * (3 - (pos & 0x3)); | |
838 | ||
16c57b36 KG |
839 | switch ((instword & PPC_INST_STRING_MASK)) { |
840 | case PPC_INST_LSWX: | |
841 | case PPC_INST_LSWI: | |
14cf11af PM |
842 | if (get_user(val, (u8 __user *)EA)) |
843 | return -EFAULT; | |
844 | /* first time updating this reg, | |
845 | * zero it out */ | |
846 | if (pos == 0) | |
847 | regs->gpr[rT] = 0; | |
848 | regs->gpr[rT] |= val << shift; | |
849 | break; | |
16c57b36 KG |
850 | case PPC_INST_STSWI: |
851 | case PPC_INST_STSWX: | |
14cf11af PM |
852 | val = regs->gpr[rT] >> shift; |
853 | if (put_user(val, (u8 __user *)EA)) | |
854 | return -EFAULT; | |
855 | break; | |
856 | } | |
857 | /* move EA to next address */ | |
858 | EA += 1; | |
859 | num_bytes--; | |
860 | ||
861 | /* manage our position within the register */ | |
862 | if (++pos == 4) { | |
863 | pos = 0; | |
864 | if (++rT == 32) | |
865 | rT = 0; | |
866 | } | |
867 | } | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
c3412dcb WS |
872 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
873 | { | |
874 | u32 ra,rs; | |
875 | unsigned long tmp; | |
876 | ||
877 | ra = (instword >> 16) & 0x1f; | |
878 | rs = (instword >> 21) & 0x1f; | |
879 | ||
880 | tmp = regs->gpr[rs]; | |
881 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
882 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
883 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
884 | regs->gpr[ra] = tmp; | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
c1469f13 KG |
889 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
890 | { | |
891 | u8 rT = (instword >> 21) & 0x1f; | |
892 | u8 rA = (instword >> 16) & 0x1f; | |
893 | u8 rB = (instword >> 11) & 0x1f; | |
894 | u8 BC = (instword >> 6) & 0x1f; | |
895 | u8 bit; | |
896 | unsigned long tmp; | |
897 | ||
898 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
899 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
900 | ||
901 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
14cf11af PM |
906 | static int emulate_instruction(struct pt_regs *regs) |
907 | { | |
908 | u32 instword; | |
909 | u32 rd; | |
910 | ||
fab5db97 | 911 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
912 | return -EINVAL; |
913 | CHECK_FULL_REGS(regs); | |
914 | ||
915 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
916 | return -EFAULT; | |
917 | ||
918 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 919 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 920 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
921 | rd = (instword >> 21) & 0x1f; |
922 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
923 | return 0; | |
924 | } | |
925 | ||
926 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 927 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 928 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 929 | return 0; |
80947e7c | 930 | } |
14cf11af PM |
931 | |
932 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 933 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 934 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
935 | unsigned long msk = 0xf0000000UL >> shift; |
936 | ||
eecff81d | 937 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
938 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
939 | regs->xer &= ~0xf0000000UL; | |
940 | return 0; | |
941 | } | |
942 | ||
943 | /* Emulate load/store string insn. */ | |
80947e7c | 944 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 945 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 946 | return emulate_string_inst(regs, instword); |
80947e7c | 947 | } |
14cf11af | 948 | |
c3412dcb | 949 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 950 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 951 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
952 | return emulate_popcntb_inst(regs, instword); |
953 | } | |
954 | ||
c1469f13 | 955 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 956 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 957 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
958 | return emulate_isel(regs, instword); |
959 | } | |
960 | ||
efcac658 AK |
961 | #ifdef CONFIG_PPC64 |
962 | /* Emulate the mfspr rD, DSCR. */ | |
963 | if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && | |
964 | cpu_has_feature(CPU_FTR_DSCR)) { | |
965 | PPC_WARN_EMULATED(mfdscr, regs); | |
966 | rd = (instword >> 21) & 0x1f; | |
967 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
968 | return 0; | |
969 | } | |
970 | /* Emulate the mtspr DSCR, rD. */ | |
971 | if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && | |
972 | cpu_has_feature(CPU_FTR_DSCR)) { | |
973 | PPC_WARN_EMULATED(mtdscr, regs); | |
974 | rd = (instword >> 21) & 0x1f; | |
975 | mtspr(SPRN_DSCR, regs->gpr[rd]); | |
976 | current->thread.dscr_inherit = 1; | |
977 | return 0; | |
978 | } | |
979 | #endif | |
980 | ||
14cf11af PM |
981 | return -EINVAL; |
982 | } | |
983 | ||
73c9ceab | 984 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 985 | { |
73c9ceab | 986 | return is_kernel_addr(addr); |
14cf11af PM |
987 | } |
988 | ||
8dad3f92 | 989 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
990 | { |
991 | unsigned int reason = get_reason(regs); | |
992 | extern int do_mathemu(struct pt_regs *regs); | |
993 | ||
aa42c69c | 994 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 995 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 996 | |
dc1c1ca3 SR |
997 | if (reason & REASON_FP) { |
998 | /* IEEE FP exception */ | |
999 | parse_fpe(regs); | |
8dad3f92 PM |
1000 | return; |
1001 | } | |
1002 | if (reason & REASON_TRAP) { | |
ba797b28 JW |
1003 | /* Debugger is first in line to stop recursive faults in |
1004 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1005 | if (debugger_bpt(regs)) | |
1006 | return; | |
1007 | ||
14cf11af | 1008 | /* trap exception */ |
dc1c1ca3 SR |
1009 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1010 | == NOTIFY_STOP) | |
1011 | return; | |
73c9ceab JF |
1012 | |
1013 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 1014 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
1015 | regs->nip += 4; |
1016 | return; | |
1017 | } | |
8dad3f92 PM |
1018 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
1019 | return; | |
1020 | } | |
1021 | ||
a3512b2d BH |
1022 | /* We restore the interrupt state now */ |
1023 | if (!arch_irq_disabled_regs(regs)) | |
1024 | local_irq_enable(); | |
cd8a5673 | 1025 | |
04903a30 KG |
1026 | #ifdef CONFIG_MATH_EMULATION |
1027 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
1028 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1029 | * that means ESR is sometimes set incorrectly - either to | |
1030 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1031 | * hardware people - not sure if it can happen on any illegal | |
1032 | * instruction or only on FP instructions, whether there is a | |
25985edc | 1033 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
5fad293b KG |
1034 | switch (do_mathemu(regs)) { |
1035 | case 0: | |
04903a30 KG |
1036 | emulate_single_step(regs); |
1037 | return; | |
5fad293b KG |
1038 | case 1: { |
1039 | int code = 0; | |
1040 | code = __parse_fpscr(current->thread.fpscr.val); | |
1041 | _exception(SIGFPE, regs, code, regs->nip); | |
1042 | return; | |
1043 | } | |
1044 | case -EFAULT: | |
1045 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1046 | return; | |
04903a30 | 1047 | } |
5fad293b | 1048 | /* fall through on any other errors */ |
04903a30 KG |
1049 | #endif /* CONFIG_MATH_EMULATION */ |
1050 | ||
8dad3f92 PM |
1051 | /* Try to emulate it if we should. */ |
1052 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1053 | switch (emulate_instruction(regs)) { |
1054 | case 0: | |
1055 | regs->nip += 4; | |
1056 | emulate_single_step(regs); | |
8dad3f92 | 1057 | return; |
14cf11af PM |
1058 | case -EFAULT: |
1059 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 1060 | return; |
14cf11af PM |
1061 | } |
1062 | } | |
8dad3f92 PM |
1063 | |
1064 | if (reason & REASON_PRIVILEGED) | |
1065 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1066 | else | |
1067 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
1068 | } |
1069 | ||
dc1c1ca3 | 1070 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1071 | { |
4393c4f6 | 1072 | int sig, code, fixed = 0; |
14cf11af | 1073 | |
a3512b2d BH |
1074 | /* We restore the interrupt state now */ |
1075 | if (!arch_irq_disabled_regs(regs)) | |
1076 | local_irq_enable(); | |
1077 | ||
e9370ae1 PM |
1078 | /* we don't implement logging of alignment exceptions */ |
1079 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1080 | fixed = fix_alignment(regs); | |
14cf11af PM |
1081 | |
1082 | if (fixed == 1) { | |
1083 | regs->nip += 4; /* skip over emulated instruction */ | |
1084 | emulate_single_step(regs); | |
1085 | return; | |
1086 | } | |
1087 | ||
dc1c1ca3 | 1088 | /* Operand address was bad */ |
14cf11af | 1089 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1090 | sig = SIGSEGV; |
1091 | code = SEGV_ACCERR; | |
1092 | } else { | |
1093 | sig = SIGBUS; | |
1094 | code = BUS_ADRALN; | |
14cf11af | 1095 | } |
4393c4f6 BH |
1096 | if (user_mode(regs)) |
1097 | _exception(sig, regs, code, regs->dar); | |
1098 | else | |
1099 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
1100 | } |
1101 | ||
1102 | void StackOverflow(struct pt_regs *regs) | |
1103 | { | |
1104 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1105 | current, regs->gpr[1]); | |
1106 | debugger(regs); | |
1107 | show_regs(regs); | |
1108 | panic("kernel stack overflow"); | |
1109 | } | |
1110 | ||
1111 | void nonrecoverable_exception(struct pt_regs *regs) | |
1112 | { | |
1113 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1114 | regs->nip, regs->msr); | |
1115 | debugger(regs); | |
1116 | die("nonrecoverable exception", regs, SIGKILL); | |
1117 | } | |
1118 | ||
1119 | void trace_syscall(struct pt_regs *regs) | |
1120 | { | |
1121 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 1122 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
1123 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
1124 | } | |
dc1c1ca3 | 1125 | |
dc1c1ca3 SR |
1126 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1127 | { | |
1128 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
1129 | "%lx at %lx\n", regs->trap, regs->nip); | |
1130 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
1131 | } | |
dc1c1ca3 SR |
1132 | |
1133 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1134 | { | |
dc1c1ca3 SR |
1135 | if (user_mode(regs)) { |
1136 | /* A user program has executed an altivec instruction, | |
1137 | but this kernel doesn't support altivec. */ | |
1138 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1139 | return; | |
1140 | } | |
6c4841c2 | 1141 | |
dc1c1ca3 SR |
1142 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1143 | "%lx at %lx\n", regs->trap, regs->nip); | |
1144 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
1145 | } |
1146 | ||
ce48b210 MN |
1147 | void vsx_unavailable_exception(struct pt_regs *regs) |
1148 | { | |
1149 | if (user_mode(regs)) { | |
1150 | /* A user program has executed an vsx instruction, | |
1151 | but this kernel doesn't support vsx. */ | |
1152 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1153 | return; | |
1154 | } | |
1155 | ||
1156 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1157 | "%lx at %lx\n", regs->trap, regs->nip); | |
1158 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1159 | } | |
1160 | ||
dc1c1ca3 SR |
1161 | void performance_monitor_exception(struct pt_regs *regs) |
1162 | { | |
89713ed1 AB |
1163 | __get_cpu_var(irq_stat).pmu_irqs++; |
1164 | ||
dc1c1ca3 SR |
1165 | perf_irq(regs); |
1166 | } | |
dc1c1ca3 | 1167 | |
8dad3f92 | 1168 | #ifdef CONFIG_8xx |
14cf11af PM |
1169 | void SoftwareEmulation(struct pt_regs *regs) |
1170 | { | |
1171 | extern int do_mathemu(struct pt_regs *); | |
1172 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 1173 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1174 | int errcode; |
5dd57a13 | 1175 | #endif |
14cf11af PM |
1176 | |
1177 | CHECK_FULL_REGS(regs); | |
1178 | ||
1179 | if (!user_mode(regs)) { | |
1180 | debugger(regs); | |
1181 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
1182 | } | |
1183 | ||
1184 | #ifdef CONFIG_MATH_EMULATION | |
1185 | errcode = do_mathemu(regs); | |
80947e7c | 1186 | if (errcode >= 0) |
eecff81d | 1187 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
1188 | |
1189 | switch (errcode) { | |
1190 | case 0: | |
1191 | emulate_single_step(regs); | |
1192 | return; | |
1193 | case 1: { | |
1194 | int code = 0; | |
1195 | code = __parse_fpscr(current->thread.fpscr.val); | |
1196 | _exception(SIGFPE, regs, code, regs->nip); | |
1197 | return; | |
1198 | } | |
1199 | case -EFAULT: | |
1200 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1201 | return; | |
1202 | default: | |
1203 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1204 | return; | |
1205 | } | |
1206 | ||
5dd57a13 | 1207 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1208 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1209 | if (errcode >= 0) |
eecff81d | 1210 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1211 | |
5fad293b KG |
1212 | switch (errcode) { |
1213 | case 0: | |
14cf11af | 1214 | emulate_single_step(regs); |
5fad293b KG |
1215 | return; |
1216 | case 1: | |
1217 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1218 | return; | |
1219 | case -EFAULT: | |
1220 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1221 | return; | |
1222 | } | |
5dd57a13 SW |
1223 | #else |
1224 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1225 | #endif |
14cf11af | 1226 | } |
8dad3f92 | 1227 | #endif /* CONFIG_8xx */ |
14cf11af | 1228 | |
172ae2e7 | 1229 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1230 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1231 | { | |
1232 | int changed = 0; | |
1233 | /* | |
1234 | * Determine the cause of the debug event, clear the | |
1235 | * event flags and send a trap to the handler. Torez | |
1236 | */ | |
1237 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1238 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1239 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1240 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1241 | #endif | |
1242 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1243 | 5); | |
1244 | changed |= 0x01; | |
1245 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1246 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1247 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1248 | 6); | |
1249 | changed |= 0x01; | |
1250 | } else if (debug_status & DBSR_IAC1) { | |
1251 | current->thread.dbcr0 &= ~DBCR0_IAC1; | |
1252 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | |
1253 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1254 | 1); | |
1255 | changed |= 0x01; | |
1256 | } else if (debug_status & DBSR_IAC2) { | |
1257 | current->thread.dbcr0 &= ~DBCR0_IAC2; | |
1258 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | |
1259 | 2); | |
1260 | changed |= 0x01; | |
1261 | } else if (debug_status & DBSR_IAC3) { | |
1262 | current->thread.dbcr0 &= ~DBCR0_IAC3; | |
1263 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | |
1264 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1265 | 3); | |
1266 | changed |= 0x01; | |
1267 | } else if (debug_status & DBSR_IAC4) { | |
1268 | current->thread.dbcr0 &= ~DBCR0_IAC4; | |
1269 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | |
1270 | 4); | |
1271 | changed |= 0x01; | |
1272 | } | |
1273 | /* | |
1274 | * At the point this routine was called, the MSR(DE) was turned off. | |
1275 | * Check all other debug flags and see if that bit needs to be turned | |
1276 | * back on or not. | |
1277 | */ | |
1278 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | |
1279 | regs->msr |= MSR_DE; | |
1280 | else | |
1281 | /* Make sure the IDM flag is off */ | |
1282 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1283 | ||
1284 | if (changed & 0x01) | |
1285 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | |
1286 | } | |
14cf11af | 1287 | |
f8279621 | 1288 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1289 | { |
3bffb652 DK |
1290 | current->thread.dbsr = debug_status; |
1291 | ||
ec097c84 RM |
1292 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1293 | * on server, it stops on the target of the branch. In order to simulate | |
1294 | * the server behaviour, we thus restart right away with a single step | |
1295 | * instead of stopping here when hitting a BT | |
1296 | */ | |
1297 | if (debug_status & DBSR_BT) { | |
1298 | regs->msr &= ~MSR_DE; | |
1299 | ||
1300 | /* Disable BT */ | |
1301 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1302 | /* Clear the BT event */ | |
1303 | mtspr(SPRN_DBSR, DBSR_BT); | |
1304 | ||
1305 | /* Do the single step trick only when coming from userspace */ | |
1306 | if (user_mode(regs)) { | |
1307 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1308 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1309 | regs->msr |= MSR_DE; | |
1310 | return; | |
1311 | } | |
1312 | ||
1313 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1314 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1315 | return; | |
1316 | } | |
1317 | if (debugger_sstep(regs)) | |
1318 | return; | |
1319 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1320 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1321 | |
1322 | /* Disable instruction completion */ | |
1323 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1324 | /* Clear the instruction completion event */ | |
1325 | mtspr(SPRN_DBSR, DBSR_IC); | |
1326 | ||
1327 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1328 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1329 | return; | |
1330 | } | |
1331 | ||
1332 | if (debugger_sstep(regs)) | |
1333 | return; | |
1334 | ||
d6a61bfc | 1335 | if (user_mode(regs)) { |
3bffb652 | 1336 | current->thread.dbcr0 &= ~DBCR0_IC; |
3bffb652 DK |
1337 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, |
1338 | current->thread.dbcr1)) | |
1339 | regs->msr |= MSR_DE; | |
1340 | else | |
1341 | /* Make sure the IDM bit is off */ | |
1342 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
d6a61bfc | 1343 | } |
3bffb652 DK |
1344 | |
1345 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1346 | } else | |
1347 | handle_debug(regs, debug_status); | |
14cf11af | 1348 | } |
172ae2e7 | 1349 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1350 | |
1351 | #if !defined(CONFIG_TAU_INT) | |
1352 | void TAUException(struct pt_regs *regs) | |
1353 | { | |
1354 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1355 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1356 | } | |
1357 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1358 | |
1359 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1360 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1361 | { |
1362 | int err; | |
1363 | ||
14cf11af PM |
1364 | if (!user_mode(regs)) { |
1365 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1366 | " at %lx\n", regs->nip); | |
8dad3f92 | 1367 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1368 | } |
1369 | ||
dc1c1ca3 | 1370 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1371 | |
eecff81d | 1372 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1373 | err = emulate_altivec(regs); |
1374 | if (err == 0) { | |
1375 | regs->nip += 4; /* skip emulated instruction */ | |
1376 | emulate_single_step(regs); | |
1377 | return; | |
1378 | } | |
1379 | ||
1380 | if (err == -EFAULT) { | |
1381 | /* got an error reading the instruction */ | |
1382 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1383 | } else { | |
1384 | /* didn't recognize the instruction */ | |
1385 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1386 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1387 | "in %s at %lx\n", current->comm, regs->nip); | |
14cf11af PM |
1388 | current->thread.vscr.u[3] |= 0x10000; |
1389 | } | |
1390 | } | |
1391 | #endif /* CONFIG_ALTIVEC */ | |
1392 | ||
ce48b210 MN |
1393 | #ifdef CONFIG_VSX |
1394 | void vsx_assist_exception(struct pt_regs *regs) | |
1395 | { | |
1396 | if (!user_mode(regs)) { | |
1397 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1398 | " at %lx\n", regs->nip); | |
1399 | die("Kernel VSX assist exception", regs, SIGILL); | |
1400 | } | |
1401 | ||
1402 | flush_vsx_to_thread(current); | |
1403 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1404 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1405 | } | |
1406 | #endif /* CONFIG_VSX */ | |
1407 | ||
14cf11af PM |
1408 | #ifdef CONFIG_FSL_BOOKE |
1409 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1410 | unsigned long error_code) | |
1411 | { | |
1412 | /* We treat cache locking instructions from the user | |
1413 | * as priv ops, in the future we could try to do | |
1414 | * something smarter | |
1415 | */ | |
1416 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1417 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1418 | return; | |
1419 | } | |
1420 | #endif /* CONFIG_FSL_BOOKE */ | |
1421 | ||
1422 | #ifdef CONFIG_SPE | |
1423 | void SPEFloatingPointException(struct pt_regs *regs) | |
1424 | { | |
6a800f36 | 1425 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1426 | unsigned long spefscr; |
1427 | int fpexc_mode; | |
1428 | int code = 0; | |
6a800f36 LY |
1429 | int err; |
1430 | ||
685659ee | 1431 | flush_spe_to_thread(current); |
14cf11af PM |
1432 | |
1433 | spefscr = current->thread.spefscr; | |
1434 | fpexc_mode = current->thread.fpexc_mode; | |
1435 | ||
14cf11af PM |
1436 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1437 | code = FPE_FLTOVF; | |
14cf11af PM |
1438 | } |
1439 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1440 | code = FPE_FLTUND; | |
14cf11af PM |
1441 | } |
1442 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1443 | code = FPE_FLTDIV; | |
1444 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1445 | code = FPE_FLTINV; | |
14cf11af PM |
1446 | } |
1447 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1448 | code = FPE_FLTRES; | |
1449 | ||
6a800f36 LY |
1450 | err = do_spe_mathemu(regs); |
1451 | if (err == 0) { | |
1452 | regs->nip += 4; /* skip emulated instruction */ | |
1453 | emulate_single_step(regs); | |
1454 | return; | |
1455 | } | |
1456 | ||
1457 | if (err == -EFAULT) { | |
1458 | /* got an error reading the instruction */ | |
1459 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1460 | } else if (err == -EINVAL) { | |
1461 | /* didn't recognize the instruction */ | |
1462 | printk(KERN_ERR "unrecognized spe instruction " | |
1463 | "in %s at %lx\n", current->comm, regs->nip); | |
1464 | } else { | |
1465 | _exception(SIGFPE, regs, code, regs->nip); | |
1466 | } | |
14cf11af | 1467 | |
14cf11af PM |
1468 | return; |
1469 | } | |
6a800f36 LY |
1470 | |
1471 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1472 | { | |
1473 | extern int speround_handler(struct pt_regs *regs); | |
1474 | int err; | |
1475 | ||
1476 | preempt_disable(); | |
1477 | if (regs->msr & MSR_SPE) | |
1478 | giveup_spe(current); | |
1479 | preempt_enable(); | |
1480 | ||
1481 | regs->nip -= 4; | |
1482 | err = speround_handler(regs); | |
1483 | if (err == 0) { | |
1484 | regs->nip += 4; /* skip emulated instruction */ | |
1485 | emulate_single_step(regs); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | if (err == -EFAULT) { | |
1490 | /* got an error reading the instruction */ | |
1491 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1492 | } else if (err == -EINVAL) { | |
1493 | /* didn't recognize the instruction */ | |
1494 | printk(KERN_ERR "unrecognized spe instruction " | |
1495 | "in %s at %lx\n", current->comm, regs->nip); | |
1496 | } else { | |
1497 | _exception(SIGFPE, regs, 0, regs->nip); | |
1498 | return; | |
1499 | } | |
1500 | } | |
14cf11af PM |
1501 | #endif |
1502 | ||
dc1c1ca3 SR |
1503 | /* |
1504 | * We enter here if we get an unrecoverable exception, that is, one | |
1505 | * that happened at a point where the RI (recoverable interrupt) bit | |
1506 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1507 | * we therefore lost state by taking this exception. | |
1508 | */ | |
1509 | void unrecoverable_exception(struct pt_regs *regs) | |
1510 | { | |
1511 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1512 | regs->trap, regs->nip); | |
1513 | die("Unrecoverable exception", regs, SIGABRT); | |
1514 | } | |
dc1c1ca3 | 1515 | |
14cf11af PM |
1516 | #ifdef CONFIG_BOOKE_WDT |
1517 | /* | |
1518 | * Default handler for a Watchdog exception, | |
1519 | * spins until a reboot occurs | |
1520 | */ | |
1521 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1522 | { | |
1523 | /* Generic WatchdogHandler, implement your own */ | |
1524 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1525 | return; | |
1526 | } | |
1527 | ||
1528 | void WatchdogException(struct pt_regs *regs) | |
1529 | { | |
1530 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1531 | WatchdogHandler(regs); | |
1532 | } | |
1533 | #endif | |
dc1c1ca3 | 1534 | |
dc1c1ca3 SR |
1535 | /* |
1536 | * We enter here if we discover during exception entry that we are | |
1537 | * running in supervisor mode with a userspace value in the stack pointer. | |
1538 | */ | |
1539 | void kernel_bad_stack(struct pt_regs *regs) | |
1540 | { | |
1541 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1542 | regs->gpr[1], regs->nip); | |
1543 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1544 | } | |
14cf11af PM |
1545 | |
1546 | void __init trap_init(void) | |
1547 | { | |
1548 | } | |
80947e7c GU |
1549 | |
1550 | ||
1551 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1552 | ||
1553 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1554 | ||
1555 | struct ppc_emulated ppc_emulated = { | |
1556 | #ifdef CONFIG_ALTIVEC | |
1557 | WARN_EMULATED_SETUP(altivec), | |
1558 | #endif | |
1559 | WARN_EMULATED_SETUP(dcba), | |
1560 | WARN_EMULATED_SETUP(dcbz), | |
1561 | WARN_EMULATED_SETUP(fp_pair), | |
1562 | WARN_EMULATED_SETUP(isel), | |
1563 | WARN_EMULATED_SETUP(mcrxr), | |
1564 | WARN_EMULATED_SETUP(mfpvr), | |
1565 | WARN_EMULATED_SETUP(multiple), | |
1566 | WARN_EMULATED_SETUP(popcntb), | |
1567 | WARN_EMULATED_SETUP(spe), | |
1568 | WARN_EMULATED_SETUP(string), | |
1569 | WARN_EMULATED_SETUP(unaligned), | |
1570 | #ifdef CONFIG_MATH_EMULATION | |
1571 | WARN_EMULATED_SETUP(math), | |
1572 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1573 | WARN_EMULATED_SETUP(8xx), | |
1574 | #endif | |
1575 | #ifdef CONFIG_VSX | |
1576 | WARN_EMULATED_SETUP(vsx), | |
1577 | #endif | |
efcac658 AK |
1578 | #ifdef CONFIG_PPC64 |
1579 | WARN_EMULATED_SETUP(mfdscr), | |
1580 | WARN_EMULATED_SETUP(mtdscr), | |
1581 | #endif | |
80947e7c GU |
1582 | }; |
1583 | ||
1584 | u32 ppc_warn_emulated; | |
1585 | ||
1586 | void ppc_warn_emulated_print(const char *type) | |
1587 | { | |
76462232 CD |
1588 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
1589 | type); | |
80947e7c GU |
1590 | } |
1591 | ||
1592 | static int __init ppc_warn_emulated_init(void) | |
1593 | { | |
1594 | struct dentry *dir, *d; | |
1595 | unsigned int i; | |
1596 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1597 | ||
1598 | if (!powerpc_debugfs_root) | |
1599 | return -ENODEV; | |
1600 | ||
1601 | dir = debugfs_create_dir("emulated_instructions", | |
1602 | powerpc_debugfs_root); | |
1603 | if (!dir) | |
1604 | return -ENOMEM; | |
1605 | ||
1606 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1607 | &ppc_warn_emulated); | |
1608 | if (!d) | |
1609 | goto fail; | |
1610 | ||
1611 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1612 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1613 | (u32 *)&entries[i].val.counter); | |
1614 | if (!d) | |
1615 | goto fail; | |
1616 | } | |
1617 | ||
1618 | return 0; | |
1619 | ||
1620 | fail: | |
1621 | debugfs_remove_recursive(dir); | |
1622 | return -ENOMEM; | |
1623 | } | |
1624 | ||
1625 | device_initcall(ppc_warn_emulated_init); | |
1626 | ||
1627 | #endif /* CONFIG_PPC_EMULATED_STATS */ |