convert 'memory' sysdev_class to a regular subsystem
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / sysfs.c
CommitLineData
8a25a2fd 1#include <linux/device.h>
1da177e4
LT
2#include <linux/cpu.h>
3#include <linux/smp.h>
4#include <linux/percpu.h>
5#include <linux/init.h>
6#include <linux/sched.h>
4b16f8e2 7#include <linux/export.h>
1da177e4
LT
8#include <linux/nodemask.h>
9#include <linux/cpumask.h>
10#include <linux/notifier.h>
11
12#include <asm/current.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
1ababe11 15#include <asm/firmware.h>
1da177e4
LT
16#include <asm/hvcall.h>
17#include <asm/prom.h>
1da177e4 18#include <asm/machdep.h>
2249ca9d 19#include <asm/smp.h>
a6dbf93a 20#include <asm/pmc.h>
1da177e4 21
93197a36
NL
22#include "cacheinfo.h"
23
b950bdd0
BH
24#ifdef CONFIG_PPC64
25#include <asm/paca.h>
26#include <asm/lppaca.h>
27#endif
28
1da177e4
LT
29static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
b950bdd0
BH
31/*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35#ifdef CONFIG_PPC64
1da177e4 36
0ddd3e7d 37/* Time in microseconds we delay before sleeping in the idle loop */
b878dc00 38DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
1da177e4 39
8a25a2fd
KS
40static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
4a0b2b4d 42 const char *buf,
1da177e4
LT
43 size_t count)
44{
8a25a2fd 45 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 46 ssize_t ret;
b878dc00 47 long snooze;
1da177e4 48
b878dc00 49 ret = sscanf(buf, "%ld", &snooze);
1da177e4
LT
50 if (ret != 1)
51 return -EINVAL;
52
8a25a2fd 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
1da177e4
LT
54
55 return count;
56}
57
8a25a2fd
KS
58static ssize_t show_smt_snooze_delay(struct device *dev,
59 struct device_attribute *attr,
4a0b2b4d 60 char *buf)
1da177e4 61{
8a25a2fd 62 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 63
8a25a2fd 64 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
1da177e4
LT
65}
66
8a25a2fd 67static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
1da177e4
LT
68 store_smt_snooze_delay);
69
1da177e4
LT
70static int __init setup_smt_snooze_delay(char *str)
71{
72 unsigned int cpu;
b878dc00 73 long snooze;
1da177e4
LT
74
75 if (!cpu_has_feature(CPU_FTR_SMT))
76 return 1;
77
b878dc00
AB
78 snooze = simple_strtol(str, NULL, 10);
79 for_each_possible_cpu(cpu)
80 per_cpu(smt_snooze_delay, cpu) = snooze;
1da177e4
LT
81
82 return 1;
83}
84__setup("smt-snooze-delay=", setup_smt_snooze_delay);
85
b950bdd0 86#endif /* CONFIG_PPC64 */
180a3362 87
1da177e4
LT
88/*
89 * Enabling PMCs will slow partition context switch times so we only do
90 * it the first time we write to the PMCs.
91 */
92
93static DEFINE_PER_CPU(char, pmcs_enabled);
94
b950bdd0 95void ppc_enable_pmcs(void)
1da177e4 96{
a6dbf93a
PM
97 ppc_set_pmu_inuse(1);
98
1da177e4
LT
99 /* Only need to enable them once */
100 if (__get_cpu_var(pmcs_enabled))
101 return;
102
103 __get_cpu_var(pmcs_enabled) = 1;
104
180a3362
ME
105 if (ppc_md.enable_pmcs)
106 ppc_md.enable_pmcs();
1da177e4 107}
b950bdd0 108EXPORT_SYMBOL(ppc_enable_pmcs);
1da177e4 109
1da177e4 110#define SYSFS_PMCSETUP(NAME, ADDRESS) \
9a371934 111static void read_##NAME(void *val) \
1da177e4 112{ \
ec78c8ac 113 *(unsigned long *)val = mfspr(ADDRESS); \
1da177e4 114} \
ec78c8ac 115static void write_##NAME(void *val) \
1da177e4 116{ \
b950bdd0 117 ppc_enable_pmcs(); \
9a371934 118 mtspr(ADDRESS, *(unsigned long *)val); \
1da177e4 119} \
8a25a2fd
KS
120static ssize_t show_##NAME(struct device *dev, \
121 struct device_attribute *attr, \
4a0b2b4d 122 char *buf) \
1da177e4 123{ \
8a25a2fd 124 struct cpu *cpu = container_of(dev, struct cpu, dev); \
9a371934 125 unsigned long val; \
8a25a2fd 126 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
1da177e4
LT
127 return sprintf(buf, "%lx\n", val); \
128} \
3ff6eecc 129static ssize_t __used \
8a25a2fd 130 store_##NAME(struct device *dev, struct device_attribute *attr, \
4a0b2b4d 131 const char *buf, size_t count) \
1da177e4 132{ \
8a25a2fd 133 struct cpu *cpu = container_of(dev, struct cpu, dev); \
1da177e4
LT
134 unsigned long val; \
135 int ret = sscanf(buf, "%lx", &val); \
136 if (ret != 1) \
137 return -EINVAL; \
8a25a2fd 138 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
1da177e4
LT
139 return count; \
140}
141
6529c13d
OJ
142
143/* Let's define all possible registers, we'll only hook up the ones
144 * that are implemented on the current processor
145 */
146
33a7f122 147#if defined(CONFIG_PPC64)
b950bdd0
BH
148#define HAS_PPC_PMC_CLASSIC 1
149#define HAS_PPC_PMC_IBM 1
150#define HAS_PPC_PMC_PA6T 1
33a7f122 151#elif defined(CONFIG_6xx)
b950bdd0
BH
152#define HAS_PPC_PMC_CLASSIC 1
153#define HAS_PPC_PMC_IBM 1
154#define HAS_PPC_PMC_G4 1
155#endif
156
157
158#ifdef HAS_PPC_PMC_CLASSIC
1da177e4
LT
159SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
160SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
1da177e4
LT
161SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
162SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
163SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
164SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
165SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
166SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
b950bdd0
BH
167
168#ifdef HAS_PPC_PMC_G4
169SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
170#endif
171
172#ifdef CONFIG_PPC64
1da177e4
LT
173SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
174SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
b950bdd0
BH
175
176SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
1da177e4 177SYSFS_PMCSETUP(purr, SPRN_PURR);
f050982a 178SYSFS_PMCSETUP(spurr, SPRN_SPURR);
4c198557 179SYSFS_PMCSETUP(dscr, SPRN_DSCR);
1da177e4 180
8a25a2fd
KS
181static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
182static DEVICE_ATTR(spurr, 0600, show_spurr, NULL);
183static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
184static DEVICE_ATTR(purr, 0600, show_purr, store_purr);
efcac658
AK
185
186unsigned long dscr_default = 0;
187EXPORT_SYMBOL(dscr_default);
188
8a25a2fd
KS
189static ssize_t show_dscr_default(struct device *dev,
190 struct device_attribute *attr, char *buf)
efcac658
AK
191{
192 return sprintf(buf, "%lx\n", dscr_default);
193}
194
8a25a2fd
KS
195static ssize_t __used store_dscr_default(struct device *dev,
196 struct device_attribute *attr, const char *buf,
efcac658
AK
197 size_t count)
198{
199 unsigned long val;
200 int ret = 0;
201
202 ret = sscanf(buf, "%lx", &val);
203 if (ret != 1)
204 return -EINVAL;
205 dscr_default = val;
206
207 return count;
208}
209
8a25a2fd 210static DEVICE_ATTR(dscr_default, 0600,
efcac658
AK
211 show_dscr_default, store_dscr_default);
212
213static void sysfs_create_dscr_default(void)
214{
215 int err = 0;
216 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 217 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
efcac658 218}
b950bdd0
BH
219#endif /* CONFIG_PPC64 */
220
221#ifdef HAS_PPC_PMC_PA6T
25fc530e
OJ
222SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
223SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
224SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
225SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
226SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
227SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
2e1957fd
OJ
228#ifdef CONFIG_DEBUG_KERNEL
229SYSFS_PMCSETUP(hid0, SPRN_HID0);
230SYSFS_PMCSETUP(hid1, SPRN_HID1);
231SYSFS_PMCSETUP(hid4, SPRN_HID4);
232SYSFS_PMCSETUP(hid5, SPRN_HID5);
233SYSFS_PMCSETUP(ima0, SPRN_PA6T_IMA0);
234SYSFS_PMCSETUP(ima1, SPRN_PA6T_IMA1);
235SYSFS_PMCSETUP(ima2, SPRN_PA6T_IMA2);
236SYSFS_PMCSETUP(ima3, SPRN_PA6T_IMA3);
237SYSFS_PMCSETUP(ima4, SPRN_PA6T_IMA4);
238SYSFS_PMCSETUP(ima5, SPRN_PA6T_IMA5);
239SYSFS_PMCSETUP(ima6, SPRN_PA6T_IMA6);
240SYSFS_PMCSETUP(ima7, SPRN_PA6T_IMA7);
241SYSFS_PMCSETUP(ima8, SPRN_PA6T_IMA8);
242SYSFS_PMCSETUP(ima9, SPRN_PA6T_IMA9);
243SYSFS_PMCSETUP(imaat, SPRN_PA6T_IMAAT);
244SYSFS_PMCSETUP(btcr, SPRN_PA6T_BTCR);
245SYSFS_PMCSETUP(pccr, SPRN_PA6T_PCCR);
246SYSFS_PMCSETUP(rpccr, SPRN_PA6T_RPCCR);
247SYSFS_PMCSETUP(der, SPRN_PA6T_DER);
248SYSFS_PMCSETUP(mer, SPRN_PA6T_MER);
249SYSFS_PMCSETUP(ber, SPRN_PA6T_BER);
250SYSFS_PMCSETUP(ier, SPRN_PA6T_IER);
251SYSFS_PMCSETUP(sier, SPRN_PA6T_SIER);
252SYSFS_PMCSETUP(siar, SPRN_PA6T_SIAR);
253SYSFS_PMCSETUP(tsr0, SPRN_PA6T_TSR0);
254SYSFS_PMCSETUP(tsr1, SPRN_PA6T_TSR1);
255SYSFS_PMCSETUP(tsr2, SPRN_PA6T_TSR2);
256SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3);
257#endif /* CONFIG_DEBUG_KERNEL */
b950bdd0 258#endif /* HAS_PPC_PMC_PA6T */
6529c13d 259
b950bdd0 260#ifdef HAS_PPC_PMC_IBM
8a25a2fd
KS
261static struct device_attribute ibm_common_attrs[] = {
262 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
263 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
6529c13d 264};
b950bdd0
BH
265#endif /* HAS_PPC_PMC_G4 */
266
267#ifdef HAS_PPC_PMC_G4
8a25a2fd
KS
268static struct device_attribute g4_common_attrs[] = {
269 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
270 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
271 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
b950bdd0
BH
272};
273#endif /* HAS_PPC_PMC_G4 */
6529c13d 274
8a25a2fd
KS
275static struct device_attribute classic_pmc_attrs[] = {
276 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
277 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
278 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
279 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
280 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
281 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
b950bdd0 282#ifdef CONFIG_PPC64
8a25a2fd
KS
283 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
284 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
b950bdd0 285#endif
6529c13d
OJ
286};
287
b950bdd0 288#ifdef HAS_PPC_PMC_PA6T
8a25a2fd
KS
289static struct device_attribute pa6t_attrs[] = {
290 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
291 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
292 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
293 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
294 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
295 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
296 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
297 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
2e1957fd 298#ifdef CONFIG_DEBUG_KERNEL
8a25a2fd
KS
299 __ATTR(hid0, 0600, show_hid0, store_hid0),
300 __ATTR(hid1, 0600, show_hid1, store_hid1),
301 __ATTR(hid4, 0600, show_hid4, store_hid4),
302 __ATTR(hid5, 0600, show_hid5, store_hid5),
303 __ATTR(ima0, 0600, show_ima0, store_ima0),
304 __ATTR(ima1, 0600, show_ima1, store_ima1),
305 __ATTR(ima2, 0600, show_ima2, store_ima2),
306 __ATTR(ima3, 0600, show_ima3, store_ima3),
307 __ATTR(ima4, 0600, show_ima4, store_ima4),
308 __ATTR(ima5, 0600, show_ima5, store_ima5),
309 __ATTR(ima6, 0600, show_ima6, store_ima6),
310 __ATTR(ima7, 0600, show_ima7, store_ima7),
311 __ATTR(ima8, 0600, show_ima8, store_ima8),
312 __ATTR(ima9, 0600, show_ima9, store_ima9),
313 __ATTR(imaat, 0600, show_imaat, store_imaat),
314 __ATTR(btcr, 0600, show_btcr, store_btcr),
315 __ATTR(pccr, 0600, show_pccr, store_pccr),
316 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
317 __ATTR(der, 0600, show_der, store_der),
318 __ATTR(mer, 0600, show_mer, store_mer),
319 __ATTR(ber, 0600, show_ber, store_ber),
320 __ATTR(ier, 0600, show_ier, store_ier),
321 __ATTR(sier, 0600, show_sier, store_sier),
322 __ATTR(siar, 0600, show_siar, store_siar),
323 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
324 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
325 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
326 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
2e1957fd 327#endif /* CONFIG_DEBUG_KERNEL */
6529c13d 328};
b950bdd0
BH
329#endif /* HAS_PPC_PMC_PA6T */
330#endif /* HAS_PPC_PMC_CLASSIC */
6529c13d 331
9ba1984e 332static void __cpuinit register_cpu_online(unsigned int cpu)
1da177e4
LT
333{
334 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS
335 struct device *s = &c->dev;
336 struct device_attribute *attrs, *pmc_attrs;
6529c13d 337 int i, nattrs;
1da177e4 338
b950bdd0 339#ifdef CONFIG_PPC64
ad5cb17f
SR
340 if (!firmware_has_feature(FW_FEATURE_ISERIES) &&
341 cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 342 device_create_file(s, &dev_attr_smt_snooze_delay);
b950bdd0 343#endif
1da177e4
LT
344
345 /* PMC stuff */
6529c13d 346 switch (cur_cpu_spec->pmc_type) {
b950bdd0 347#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ
348 case PPC_PMC_IBM:
349 attrs = ibm_common_attrs;
8a25a2fd 350 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0 351 pmc_attrs = classic_pmc_attrs;
6529c13d 352 break;
b950bdd0
BH
353#endif /* HAS_PPC_PMC_IBM */
354#ifdef HAS_PPC_PMC_G4
355 case PPC_PMC_G4:
356 attrs = g4_common_attrs;
8a25a2fd 357 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH
358 pmc_attrs = classic_pmc_attrs;
359 break;
360#endif /* HAS_PPC_PMC_G4 */
361#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ
362 case PPC_PMC_PA6T:
363 /* PA Semi starts counting at PMC0 */
364 attrs = pa6t_attrs;
8a25a2fd 365 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ
366 pmc_attrs = NULL;
367 break;
b950bdd0 368#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ
369 default:
370 attrs = NULL;
371 nattrs = 0;
372 pmc_attrs = NULL;
373 }
374
375 for (i = 0; i < nattrs; i++)
8a25a2fd 376 device_create_file(s, &attrs[i]);
1da177e4 377
6529c13d
OJ
378 if (pmc_attrs)
379 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 380 device_create_file(s, &pmc_attrs[i]);
1da177e4 381
b950bdd0 382#ifdef CONFIG_PPC64
1da177e4 383 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 384 device_create_file(s, &dev_attr_mmcra);
1da177e4 385
afd05423 386 if (cpu_has_feature(CPU_FTR_PURR))
8a25a2fd 387 device_create_file(s, &dev_attr_purr);
4c198557 388
f050982a 389 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 390 device_create_file(s, &dev_attr_spurr);
f050982a 391
4c198557 392 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 393 device_create_file(s, &dev_attr_dscr);
b950bdd0 394#endif /* CONFIG_PPC64 */
124c27d3 395
93197a36 396 cacheinfo_cpu_online(cpu);
1da177e4
LT
397}
398
399#ifdef CONFIG_HOTPLUG_CPU
400static void unregister_cpu_online(unsigned int cpu)
401{
402 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS
403 struct device *s = &c->dev;
404 struct device_attribute *attrs, *pmc_attrs;
6529c13d 405 int i, nattrs;
1da177e4 406
72486f1f 407 BUG_ON(!c->hotpluggable);
1da177e4 408
a1e0eb10 409#ifdef CONFIG_PPC64
ad5cb17f
SR
410 if (!firmware_has_feature(FW_FEATURE_ISERIES) &&
411 cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 412 device_remove_file(s, &dev_attr_smt_snooze_delay);
a1e0eb10 413#endif
1da177e4
LT
414
415 /* PMC stuff */
6529c13d 416 switch (cur_cpu_spec->pmc_type) {
b950bdd0 417#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ
418 case PPC_PMC_IBM:
419 attrs = ibm_common_attrs;
8a25a2fd 420 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH
421 pmc_attrs = classic_pmc_attrs;
422 break;
423#endif /* HAS_PPC_PMC_IBM */
424#ifdef HAS_PPC_PMC_G4
425 case PPC_PMC_G4:
426 attrs = g4_common_attrs;
8a25a2fd 427 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0 428 pmc_attrs = classic_pmc_attrs;
6529c13d 429 break;
b950bdd0
BH
430#endif /* HAS_PPC_PMC_G4 */
431#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ
432 case PPC_PMC_PA6T:
433 /* PA Semi starts counting at PMC0 */
434 attrs = pa6t_attrs;
8a25a2fd 435 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ
436 pmc_attrs = NULL;
437 break;
b950bdd0 438#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ
439 default:
440 attrs = NULL;
441 nattrs = 0;
442 pmc_attrs = NULL;
443 }
1da177e4 444
6529c13d 445 for (i = 0; i < nattrs; i++)
8a25a2fd 446 device_remove_file(s, &attrs[i]);
6529c13d
OJ
447
448 if (pmc_attrs)
449 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 450 device_remove_file(s, &pmc_attrs[i]);
1da177e4 451
b950bdd0 452#ifdef CONFIG_PPC64
1da177e4 453 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 454 device_remove_file(s, &dev_attr_mmcra);
1da177e4 455
afd05423 456 if (cpu_has_feature(CPU_FTR_PURR))
8a25a2fd 457 device_remove_file(s, &dev_attr_purr);
4c198557 458
f050982a 459 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 460 device_remove_file(s, &dev_attr_spurr);
f050982a 461
4c198557 462 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 463 device_remove_file(s, &dev_attr_dscr);
b950bdd0 464#endif /* CONFIG_PPC64 */
124c27d3 465
93197a36 466 cacheinfo_cpu_offline(cpu);
1da177e4 467}
12633e80
NF
468
469#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
470ssize_t arch_cpu_probe(const char *buf, size_t count)
471{
472 if (ppc_md.cpu_probe)
473 return ppc_md.cpu_probe(buf, count);
474
475 return -EINVAL;
476}
477
478ssize_t arch_cpu_release(const char *buf, size_t count)
479{
480 if (ppc_md.cpu_release)
481 return ppc_md.cpu_release(buf, count);
482
483 return -EINVAL;
484}
485#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
486
1da177e4
LT
487#endif /* CONFIG_HOTPLUG_CPU */
488
8c78f307 489static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
1da177e4
LT
490 unsigned long action, void *hcpu)
491{
492 unsigned int cpu = (unsigned int)(long)hcpu;
493
494 switch (action) {
495 case CPU_ONLINE:
8bb78442 496 case CPU_ONLINE_FROZEN:
1da177e4
LT
497 register_cpu_online(cpu);
498 break;
499#ifdef CONFIG_HOTPLUG_CPU
500 case CPU_DEAD:
8bb78442 501 case CPU_DEAD_FROZEN:
1da177e4
LT
502 unregister_cpu_online(cpu);
503 break;
504#endif
505 }
506 return NOTIFY_OK;
507}
508
8c78f307 509static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
1da177e4
LT
510 .notifier_call = sysfs_cpu_notify,
511};
512
0344c6c5
CK
513static DEFINE_MUTEX(cpu_mutex);
514
8a25a2fd 515int cpu_add_dev_attr(struct device_attribute *attr)
0344c6c5
CK
516{
517 int cpu;
518
519 mutex_lock(&cpu_mutex);
520
521 for_each_possible_cpu(cpu) {
8a25a2fd 522 device_create_file(get_cpu_device(cpu), attr);
0344c6c5
CK
523 }
524
525 mutex_unlock(&cpu_mutex);
526 return 0;
527}
8a25a2fd 528EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
0344c6c5 529
8a25a2fd 530int cpu_add_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK
531{
532 int cpu;
8a25a2fd 533 struct device *dev;
6bcc4c01 534 int ret;
0344c6c5
CK
535
536 mutex_lock(&cpu_mutex);
537
538 for_each_possible_cpu(cpu) {
8a25a2fd
KS
539 dev = get_cpu_device(cpu);
540 ret = sysfs_create_group(&dev->kobj, attrs);
6bcc4c01 541 WARN_ON(ret != 0);
0344c6c5
CK
542 }
543
544 mutex_unlock(&cpu_mutex);
545 return 0;
546}
8a25a2fd 547EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
0344c6c5
CK
548
549
8a25a2fd 550void cpu_remove_dev_attr(struct device_attribute *attr)
0344c6c5
CK
551{
552 int cpu;
553
554 mutex_lock(&cpu_mutex);
555
556 for_each_possible_cpu(cpu) {
8a25a2fd 557 device_remove_file(get_cpu_device(cpu), attr);
0344c6c5
CK
558 }
559
560 mutex_unlock(&cpu_mutex);
561}
8a25a2fd 562EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
0344c6c5 563
8a25a2fd 564void cpu_remove_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK
565{
566 int cpu;
8a25a2fd 567 struct device *dev;
0344c6c5
CK
568
569 mutex_lock(&cpu_mutex);
570
571 for_each_possible_cpu(cpu) {
8a25a2fd
KS
572 dev = get_cpu_device(cpu);
573 sysfs_remove_group(&dev->kobj, attrs);
0344c6c5
CK
574 }
575
576 mutex_unlock(&cpu_mutex);
577}
8a25a2fd 578EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
0344c6c5
CK
579
580
1da177e4
LT
581/* NUMA stuff */
582
583#ifdef CONFIG_NUMA
1da177e4
LT
584static void register_nodes(void)
585{
586 int i;
587
0fc44159
YG
588 for (i = 0; i < MAX_NUMNODES; i++)
589 register_one_node(i);
1da177e4 590}
953039c8 591
8a25a2fd 592int sysfs_add_device_to_node(struct device *dev, int nid)
953039c8
JK
593{
594 struct node *node = &node_devices[nid];
10fbcf4c 595 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
953039c8
JK
596 kobject_name(&dev->kobj));
597}
12654f77 598EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
953039c8 599
8a25a2fd 600void sysfs_remove_device_from_node(struct device *dev, int nid)
953039c8
JK
601{
602 struct node *node = &node_devices[nid];
10fbcf4c 603 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
953039c8 604}
12654f77 605EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
953039c8 606
1da177e4
LT
607#else
608static void register_nodes(void)
609{
610 return;
611}
953039c8 612
1da177e4
LT
613#endif
614
615/* Only valid if CPU is present. */
8a25a2fd
KS
616static ssize_t show_physical_id(struct device *dev,
617 struct device_attribute *attr, char *buf)
1da177e4 618{
8a25a2fd 619 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 620
8a25a2fd 621 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1da177e4 622}
8a25a2fd 623static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1da177e4
LT
624
625static int __init topology_init(void)
626{
627 int cpu;
1da177e4
LT
628
629 register_nodes();
1da177e4
LT
630 register_cpu_notifier(&sysfs_cpu_nb);
631
0e551954 632 for_each_possible_cpu(cpu) {
1da177e4
LT
633 struct cpu *c = &per_cpu(cpu_devices, cpu);
634
1da177e4
LT
635 /*
636 * For now, we just see if the system supports making
637 * the RTAS calls for CPU hotplug. But, there may be a
638 * more comprehensive way to do this for an individual
639 * CPU. For instance, the boot cpu might never be valid
640 * for hotplugging.
641 */
72486f1f
SS
642 if (ppc_md.cpu_die)
643 c->hotpluggable = 1;
1da177e4 644
72486f1f 645 if (cpu_online(cpu) || c->hotpluggable) {
76b67ed9 646 register_cpu(c, cpu);
1da177e4 647
8a25a2fd 648 device_create_file(&c->dev, &dev_attr_physical_id);
1da177e4
LT
649 }
650
651 if (cpu_online(cpu))
652 register_cpu_online(cpu);
653 }
efcac658
AK
654#ifdef CONFIG_PPC64
655 sysfs_create_dscr_default();
656#endif /* CONFIG_PPC64 */
1da177e4
LT
657
658 return 0;
659}
e9e77ce8 660subsys_initcall(topology_init);