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Merge tag 'v3.10.107' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / sysfs.c
CommitLineData
8a25a2fd 1#include <linux/device.h>
1da177e4
LT		 2#include <linux/cpu.h>
3#include <linux/smp.h>
4#include <linux/percpu.h>
5#include <linux/init.h>
6#include <linux/sched.h>
4b16f8e2 7#include <linux/export.h>
1da177e4
LT		 8#include <linux/nodemask.h>
9#include <linux/cpumask.h>
10#include <linux/notifier.h>
11
12#include <asm/current.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
15#include <asm/hvcall.h>
16#include <asm/prom.h>
1da177e4 17#include <asm/machdep.h>
2249ca9d 18#include <asm/smp.h>
a6dbf93a 19#include <asm/pmc.h>
4d358e9e 20#include <asm/firmware.h>
1da177e4 21
93197a36
NL		 22#include "cacheinfo.h"
23
b950bdd0
BH		 24#ifdef CONFIG_PPC64
25#include <asm/paca.h>
26#include <asm/lppaca.h>
27#endif
28
1da177e4
LT		 29static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
b950bdd0
BH		 31/*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35#ifdef CONFIG_PPC64
1da177e4 36
0ddd3e7d 37/* Time in microseconds we delay before sleeping in the idle loop */
b878dc00 38DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
1da177e4 39
8a25a2fd
KS		 40static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
4a0b2b4d 42 const char *buf,
1da177e4
LT		 43 size_t count)
44{
8a25a2fd 45 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 46 ssize_t ret;
b878dc00 47 long snooze;
1da177e4 48
b878dc00 49 ret = sscanf(buf, "%ld", &snooze);
1da177e4
LT		 50 if (ret != 1)
51 return -EINVAL;
52
8a25a2fd 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
8ea959a1 54 update_smt_snooze_delay(cpu->dev.id, snooze);
1da177e4
LT		 55
56 return count;
57}
58
8a25a2fd
KS		 59static ssize_t show_smt_snooze_delay(struct device *dev,
60 struct device_attribute *attr,
4a0b2b4d 61 char *buf)
1da177e4 62{
8a25a2fd 63 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 64
8a25a2fd 65 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
1da177e4
LT		 66}
67
8a25a2fd 68static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
1da177e4
LT		 69 store_smt_snooze_delay);
70
1da177e4
LT		 71static int __init setup_smt_snooze_delay(char *str)
72{
73 unsigned int cpu;
b878dc00 74 long snooze;
1da177e4
LT		 75
76 if (!cpu_has_feature(CPU_FTR_SMT))
77 return 1;
78
b878dc00
AB		 79 snooze = simple_strtol(str, NULL, 10);
80 for_each_possible_cpu(cpu)
81 per_cpu(smt_snooze_delay, cpu) = snooze;
1da177e4
LT		 82
83 return 1;
84}
85__setup("smt-snooze-delay=", setup_smt_snooze_delay);
86
b950bdd0 87#endif /* CONFIG_PPC64 */
180a3362 88
1da177e4
LT		 89/*
90 * Enabling PMCs will slow partition context switch times so we only do
91 * it the first time we write to the PMCs.
92 */
93
94static DEFINE_PER_CPU(char, pmcs_enabled);
95
b950bdd0 96void ppc_enable_pmcs(void)
1da177e4 97{
a6dbf93a
PM		 98 ppc_set_pmu_inuse(1);
99
1da177e4
LT		 100 /* Only need to enable them once */
101 if (__get_cpu_var(pmcs_enabled))
102 return;
103
104 __get_cpu_var(pmcs_enabled) = 1;
105
180a3362
ME		 106 if (ppc_md.enable_pmcs)
107 ppc_md.enable_pmcs();
1da177e4 108}
b950bdd0 109EXPORT_SYMBOL(ppc_enable_pmcs);
1da177e4 110
1da177e4 111#define SYSFS_PMCSETUP(NAME, ADDRESS) \
9a371934 112static void read_##NAME(void *val) \
1da177e4 113{ \
ec78c8ac 114 *(unsigned long *)val = mfspr(ADDRESS); \
1da177e4 115} \
ec78c8ac 116static void write_##NAME(void *val) \
1da177e4 117{ \
b950bdd0 118 ppc_enable_pmcs(); \
9a371934 119 mtspr(ADDRESS, *(unsigned long *)val); \
1da177e4 120} \
8a25a2fd
KS		 121static ssize_t show_##NAME(struct device *dev, \
122 struct device_attribute *attr, \
4a0b2b4d 123 char *buf) \
1da177e4 124{ \
8a25a2fd 125 struct cpu *cpu = container_of(dev, struct cpu, dev); \
9a371934 126 unsigned long val; \
8a25a2fd 127 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
1da177e4
LT		 128 return sprintf(buf, "%lx\n", val); \
129} \
3ff6eecc 130static ssize_t __used \
8a25a2fd 131 store_##NAME(struct device *dev, struct device_attribute *attr, \
4a0b2b4d 132 const char *buf, size_t count) \
1da177e4 133{ \
8a25a2fd 134 struct cpu *cpu = container_of(dev, struct cpu, dev); \
1da177e4
LT		 135 unsigned long val; \
136 int ret = sscanf(buf, "%lx", &val); \
137 if (ret != 1) \
138 return -EINVAL; \
8a25a2fd 139 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
1da177e4
LT		 140 return count; \
141}
142
6529c13d
OJ		 143
144/* Let's define all possible registers, we'll only hook up the ones
145 * that are implemented on the current processor
146 */
147
33a7f122 148#if defined(CONFIG_PPC64)
b950bdd0
BH		 149#define HAS_PPC_PMC_CLASSIC 1
150#define HAS_PPC_PMC_IBM 1
151#define HAS_PPC_PMC_PA6T 1
33a7f122 152#elif defined(CONFIG_6xx)
b950bdd0
BH		 153#define HAS_PPC_PMC_CLASSIC 1
154#define HAS_PPC_PMC_IBM 1
155#define HAS_PPC_PMC_G4 1
156#endif
157
158
159#ifdef HAS_PPC_PMC_CLASSIC
1da177e4
LT		 160SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
161SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
1da177e4
LT		 162SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
163SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
164SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
165SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
166SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
167SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
b950bdd0
BH		 168
169#ifdef HAS_PPC_PMC_G4
170SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
171#endif
172
173#ifdef CONFIG_PPC64
1da177e4
LT		 174SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
175SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
b950bdd0
BH		 176
177SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
1da177e4 178SYSFS_PMCSETUP(purr, SPRN_PURR);
f050982a 179SYSFS_PMCSETUP(spurr, SPRN_SPURR);
4c198557 180SYSFS_PMCSETUP(dscr, SPRN_DSCR);
595fe914 181SYSFS_PMCSETUP(pir, SPRN_PIR);
1da177e4 182
4d358e9e
MS		 183/*
184 Lets only enable read for phyp resources and
185 enable write when needed with a separate function.
186 Lets be conservative and default to pseries.
187*/
8a25a2fd 188static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
d5dae721 189static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
8a25a2fd 190static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
4d358e9e 191static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
7affca35 192static DEVICE_ATTR(pir, 0400, show_pir, NULL);
efcac658
AK		 193
194unsigned long dscr_default = 0;
195EXPORT_SYMBOL(dscr_default);
196
4d358e9e
MS		 197static void add_write_permission_dev_attr(struct device_attribute *attr)
198{
199 attr->attr.mode |= 0200;
200}
201
8a25a2fd
KS		 202static ssize_t show_dscr_default(struct device *dev,
203 struct device_attribute *attr, char *buf)
efcac658
AK		 204{
205 return sprintf(buf, "%lx\n", dscr_default);
206}
207
1b6ca2a6
AB		 208static void update_dscr(void *dummy)
209{
00ca0de0
AB		 210 if (!current->thread.dscr_inherit) {
211 current->thread.dscr = dscr_default;
1b6ca2a6 212 mtspr(SPRN_DSCR, dscr_default);
00ca0de0 213 }
1b6ca2a6
AB		 214}
215
8a25a2fd
KS		 216static ssize_t __used store_dscr_default(struct device *dev,
217 struct device_attribute *attr, const char *buf,
efcac658
AK		 218 size_t count)
219{
220 unsigned long val;
221 int ret = 0;
222
223 ret = sscanf(buf, "%lx", &val);
224 if (ret != 1)
225 return -EINVAL;
226 dscr_default = val;
227
1b6ca2a6
AB		 228 on_each_cpu(update_dscr, NULL, 1);
229
efcac658
AK		 230 return count;
231}
232
8a25a2fd 233static DEVICE_ATTR(dscr_default, 0600,
efcac658
AK		 234 show_dscr_default, store_dscr_default);
235
236static void sysfs_create_dscr_default(void)
237{
238 int err = 0;
239 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 240 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
efcac658 241}
b950bdd0
BH		 242#endif /* CONFIG_PPC64 */
243
244#ifdef HAS_PPC_PMC_PA6T
25fc530e
OJ		 245SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
246SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
247SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
248SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
249SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
250SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
2e1957fd
OJ		 251#ifdef CONFIG_DEBUG_KERNEL
252SYSFS_PMCSETUP(hid0, SPRN_HID0);
253SYSFS_PMCSETUP(hid1, SPRN_HID1);
254SYSFS_PMCSETUP(hid4, SPRN_HID4);
255SYSFS_PMCSETUP(hid5, SPRN_HID5);
256SYSFS_PMCSETUP(ima0, SPRN_PA6T_IMA0);
257SYSFS_PMCSETUP(ima1, SPRN_PA6T_IMA1);
258SYSFS_PMCSETUP(ima2, SPRN_PA6T_IMA2);
259SYSFS_PMCSETUP(ima3, SPRN_PA6T_IMA3);
260SYSFS_PMCSETUP(ima4, SPRN_PA6T_IMA4);
261SYSFS_PMCSETUP(ima5, SPRN_PA6T_IMA5);
262SYSFS_PMCSETUP(ima6, SPRN_PA6T_IMA6);
263SYSFS_PMCSETUP(ima7, SPRN_PA6T_IMA7);
264SYSFS_PMCSETUP(ima8, SPRN_PA6T_IMA8);
265SYSFS_PMCSETUP(ima9, SPRN_PA6T_IMA9);
266SYSFS_PMCSETUP(imaat, SPRN_PA6T_IMAAT);
267SYSFS_PMCSETUP(btcr, SPRN_PA6T_BTCR);
268SYSFS_PMCSETUP(pccr, SPRN_PA6T_PCCR);
269SYSFS_PMCSETUP(rpccr, SPRN_PA6T_RPCCR);
270SYSFS_PMCSETUP(der, SPRN_PA6T_DER);
271SYSFS_PMCSETUP(mer, SPRN_PA6T_MER);
272SYSFS_PMCSETUP(ber, SPRN_PA6T_BER);
273SYSFS_PMCSETUP(ier, SPRN_PA6T_IER);
274SYSFS_PMCSETUP(sier, SPRN_PA6T_SIER);
275SYSFS_PMCSETUP(siar, SPRN_PA6T_SIAR);
276SYSFS_PMCSETUP(tsr0, SPRN_PA6T_TSR0);
277SYSFS_PMCSETUP(tsr1, SPRN_PA6T_TSR1);
278SYSFS_PMCSETUP(tsr2, SPRN_PA6T_TSR2);
279SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3);
280#endif /* CONFIG_DEBUG_KERNEL */
b950bdd0 281#endif /* HAS_PPC_PMC_PA6T */
6529c13d 282
b950bdd0 283#ifdef HAS_PPC_PMC_IBM
8a25a2fd
KS		 284static struct device_attribute ibm_common_attrs[] = {
285 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
286 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
6529c13d 287};
b950bdd0
BH		 288#endif /* HAS_PPC_PMC_G4 */
289
290#ifdef HAS_PPC_PMC_G4
8a25a2fd
KS		 291static struct device_attribute g4_common_attrs[] = {
292 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
293 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
294 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
b950bdd0
BH		 295};
296#endif /* HAS_PPC_PMC_G4 */
6529c13d 297
8a25a2fd
KS		 298static struct device_attribute classic_pmc_attrs[] = {
299 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
300 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
301 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
302 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
303 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
304 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
b950bdd0 305#ifdef CONFIG_PPC64
8a25a2fd
KS		 306 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
307 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
b950bdd0 308#endif
6529c13d
OJ		 309};
310
b950bdd0 311#ifdef HAS_PPC_PMC_PA6T
8a25a2fd
KS		 312static struct device_attribute pa6t_attrs[] = {
313 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
314 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
315 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
316 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
317 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
318 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
319 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
320 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
2e1957fd 321#ifdef CONFIG_DEBUG_KERNEL
8a25a2fd
KS		 322 __ATTR(hid0, 0600, show_hid0, store_hid0),
323 __ATTR(hid1, 0600, show_hid1, store_hid1),
324 __ATTR(hid4, 0600, show_hid4, store_hid4),
325 __ATTR(hid5, 0600, show_hid5, store_hid5),
326 __ATTR(ima0, 0600, show_ima0, store_ima0),
327 __ATTR(ima1, 0600, show_ima1, store_ima1),
328 __ATTR(ima2, 0600, show_ima2, store_ima2),
329 __ATTR(ima3, 0600, show_ima3, store_ima3),
330 __ATTR(ima4, 0600, show_ima4, store_ima4),
331 __ATTR(ima5, 0600, show_ima5, store_ima5),
332 __ATTR(ima6, 0600, show_ima6, store_ima6),
333 __ATTR(ima7, 0600, show_ima7, store_ima7),
334 __ATTR(ima8, 0600, show_ima8, store_ima8),
335 __ATTR(ima9, 0600, show_ima9, store_ima9),
336 __ATTR(imaat, 0600, show_imaat, store_imaat),
337 __ATTR(btcr, 0600, show_btcr, store_btcr),
338 __ATTR(pccr, 0600, show_pccr, store_pccr),
339 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
340 __ATTR(der, 0600, show_der, store_der),
341 __ATTR(mer, 0600, show_mer, store_mer),
342 __ATTR(ber, 0600, show_ber, store_ber),
343 __ATTR(ier, 0600, show_ier, store_ier),
344 __ATTR(sier, 0600, show_sier, store_sier),
345 __ATTR(siar, 0600, show_siar, store_siar),
346 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
347 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
348 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
349 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
2e1957fd 350#endif /* CONFIG_DEBUG_KERNEL */
6529c13d 351};
b950bdd0
BH		 352#endif /* HAS_PPC_PMC_PA6T */
353#endif /* HAS_PPC_PMC_CLASSIC */
6529c13d 354
9ba1984e 355static void __cpuinit register_cpu_online(unsigned int cpu)
1da177e4
LT		 356{
357 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 358 struct device *s = &c->dev;
359 struct device_attribute *attrs, *pmc_attrs;
6529c13d 360 int i, nattrs;
1da177e4 361
b950bdd0 362#ifdef CONFIG_PPC64
f5339277 363 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 364 device_create_file(s, &dev_attr_smt_snooze_delay);
b950bdd0 365#endif
1da177e4
LT		 366
367 /* PMC stuff */
6529c13d 368 switch (cur_cpu_spec->pmc_type) {
b950bdd0 369#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 370 case PPC_PMC_IBM:
371 attrs = ibm_common_attrs;
8a25a2fd 372 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0 373 pmc_attrs = classic_pmc_attrs;
6529c13d 374 break;
b950bdd0
BH		 375#endif /* HAS_PPC_PMC_IBM */
376#ifdef HAS_PPC_PMC_G4
377 case PPC_PMC_G4:
378 attrs = g4_common_attrs;
8a25a2fd 379 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 380 pmc_attrs = classic_pmc_attrs;
381 break;
382#endif /* HAS_PPC_PMC_G4 */
383#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 384 case PPC_PMC_PA6T:
385 /* PA Semi starts counting at PMC0 */
386 attrs = pa6t_attrs;
8a25a2fd 387 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 388 pmc_attrs = NULL;
389 break;
b950bdd0 390#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 391 default:
392 attrs = NULL;
393 nattrs = 0;
394 pmc_attrs = NULL;
395 }
396
397 for (i = 0; i < nattrs; i++)
8a25a2fd 398 device_create_file(s, &attrs[i]);
1da177e4 399
6529c13d
OJ		 400 if (pmc_attrs)
401 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 402 device_create_file(s, &pmc_attrs[i]);
1da177e4 403
b950bdd0 404#ifdef CONFIG_PPC64
1da177e4 405 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 406 device_create_file(s, &dev_attr_mmcra);
1da177e4 407
4d358e9e
MS		 408 if (cpu_has_feature(CPU_FTR_PURR)) {
409 if (!firmware_has_feature(FW_FEATURE_LPAR))
410 add_write_permission_dev_attr(&dev_attr_purr);
8a25a2fd 411 device_create_file(s, &dev_attr_purr);
4d358e9e 412 }
4c198557 413
f050982a 414 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 415 device_create_file(s, &dev_attr_spurr);
f050982a 416
4c198557 417 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 418 device_create_file(s, &dev_attr_dscr);
595fe914
AM		 419
420 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 421 device_create_file(s, &dev_attr_pir);
b950bdd0 422#endif /* CONFIG_PPC64 */
124c27d3 423
93197a36 424 cacheinfo_cpu_online(cpu);
1da177e4
LT		 425}
426
427#ifdef CONFIG_HOTPLUG_CPU
428static void unregister_cpu_online(unsigned int cpu)
429{
430 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 431 struct device *s = &c->dev;
432 struct device_attribute *attrs, *pmc_attrs;
6529c13d 433 int i, nattrs;
1da177e4 434
72486f1f 435 BUG_ON(!c->hotpluggable);
1da177e4 436
a1e0eb10 437#ifdef CONFIG_PPC64
f5339277 438 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 439 device_remove_file(s, &dev_attr_smt_snooze_delay);
a1e0eb10 440#endif
1da177e4
LT		 441
442 /* PMC stuff */
6529c13d 443 switch (cur_cpu_spec->pmc_type) {
b950bdd0 444#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 445 case PPC_PMC_IBM:
446 attrs = ibm_common_attrs;
8a25a2fd 447 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 448 pmc_attrs = classic_pmc_attrs;
449 break;
450#endif /* HAS_PPC_PMC_IBM */
451#ifdef HAS_PPC_PMC_G4
452 case PPC_PMC_G4:
453 attrs = g4_common_attrs;
8a25a2fd 454 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0 455 pmc_attrs = classic_pmc_attrs;
6529c13d 456 break;
b950bdd0
BH		 457#endif /* HAS_PPC_PMC_G4 */
458#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 459 case PPC_PMC_PA6T:
460 /* PA Semi starts counting at PMC0 */
461 attrs = pa6t_attrs;
8a25a2fd 462 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 463 pmc_attrs = NULL;
464 break;
b950bdd0 465#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 466 default:
467 attrs = NULL;
468 nattrs = 0;
469 pmc_attrs = NULL;
470 }
1da177e4 471
6529c13d 472 for (i = 0; i < nattrs; i++)
8a25a2fd 473 device_remove_file(s, &attrs[i]);
6529c13d
OJ		 474
475 if (pmc_attrs)
476 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 477 device_remove_file(s, &pmc_attrs[i]);
1da177e4 478
b950bdd0 479#ifdef CONFIG_PPC64
1da177e4 480 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 481 device_remove_file(s, &dev_attr_mmcra);
1da177e4 482
afd05423 483 if (cpu_has_feature(CPU_FTR_PURR))
8a25a2fd 484 device_remove_file(s, &dev_attr_purr);
4c198557 485
f050982a 486 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 487 device_remove_file(s, &dev_attr_spurr);
f050982a 488
4c198557 489 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 490 device_remove_file(s, &dev_attr_dscr);
595fe914
AM		 491
492 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 493 device_remove_file(s, &dev_attr_pir);
b950bdd0 494#endif /* CONFIG_PPC64 */
124c27d3 495
93197a36 496 cacheinfo_cpu_offline(cpu);
1da177e4 497}
12633e80
NF		 498
499#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
500ssize_t arch_cpu_probe(const char *buf, size_t count)
501{
502 if (ppc_md.cpu_probe)
503 return ppc_md.cpu_probe(buf, count);
504
505 return -EINVAL;
506}
507
508ssize_t arch_cpu_release(const char *buf, size_t count)
509{
510 if (ppc_md.cpu_release)
511 return ppc_md.cpu_release(buf, count);
512
513 return -EINVAL;
514}
515#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
516
1da177e4
LT		 517#endif /* CONFIG_HOTPLUG_CPU */
518
8c78f307 519static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
1da177e4
LT		 520 unsigned long action, void *hcpu)
521{
522 unsigned int cpu = (unsigned int)(long)hcpu;
523
524 switch (action) {
525 case CPU_ONLINE:
8bb78442 526 case CPU_ONLINE_FROZEN:
1da177e4
LT		 527 register_cpu_online(cpu);
528 break;
529#ifdef CONFIG_HOTPLUG_CPU
530 case CPU_DEAD:
8bb78442 531 case CPU_DEAD_FROZEN:
1da177e4
LT		 532 unregister_cpu_online(cpu);
533 break;
534#endif
535 }
536 return NOTIFY_OK;
537}
538
8c78f307 539static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
1da177e4
LT		 540 .notifier_call = sysfs_cpu_notify,
541};
542
0344c6c5
CK		 543static DEFINE_MUTEX(cpu_mutex);
544
8a25a2fd 545int cpu_add_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 546{
547 int cpu;
548
549 mutex_lock(&cpu_mutex);
550
551 for_each_possible_cpu(cpu) {
8a25a2fd 552 device_create_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 553 }
554
555 mutex_unlock(&cpu_mutex);
556 return 0;
557}
8a25a2fd 558EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
0344c6c5 559
8a25a2fd 560int cpu_add_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 561{
562 int cpu;
8a25a2fd 563 struct device *dev;
6bcc4c01 564 int ret;
0344c6c5
CK		 565
566 mutex_lock(&cpu_mutex);
567
568 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 569 dev = get_cpu_device(cpu);
570 ret = sysfs_create_group(&dev->kobj, attrs);
6bcc4c01 571 WARN_ON(ret != 0);
0344c6c5
CK		 572 }
573
574 mutex_unlock(&cpu_mutex);
575 return 0;
576}
8a25a2fd 577EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
0344c6c5
CK		 578
579
8a25a2fd 580void cpu_remove_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 581{
582 int cpu;
583
584 mutex_lock(&cpu_mutex);
585
586 for_each_possible_cpu(cpu) {
8a25a2fd 587 device_remove_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 588 }
589
590 mutex_unlock(&cpu_mutex);
591}
8a25a2fd 592EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
0344c6c5 593
8a25a2fd 594void cpu_remove_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 595{
596 int cpu;
8a25a2fd 597 struct device *dev;
0344c6c5
CK		 598
599 mutex_lock(&cpu_mutex);
600
601 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 602 dev = get_cpu_device(cpu);
603 sysfs_remove_group(&dev->kobj, attrs);
0344c6c5
CK		 604 }
605
606 mutex_unlock(&cpu_mutex);
607}
8a25a2fd 608EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
0344c6c5
CK		 609
610
1da177e4
LT		 611/* NUMA stuff */
612
613#ifdef CONFIG_NUMA
1da177e4
LT		 614static void register_nodes(void)
615{
616 int i;
617
0fc44159
YG		 618 for (i = 0; i < MAX_NUMNODES; i++)
619 register_one_node(i);
1da177e4 620}
953039c8 621
8a25a2fd 622int sysfs_add_device_to_node(struct device *dev, int nid)
953039c8 623{
8732794b 624 struct node *node = node_devices[nid];
10fbcf4c 625 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
953039c8
JK		 626 kobject_name(&dev->kobj));
627}
12654f77 628EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
953039c8 629
8a25a2fd 630void sysfs_remove_device_from_node(struct device *dev, int nid)
953039c8 631{
8732794b 632 struct node *node = node_devices[nid];
10fbcf4c 633 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
953039c8 634}
12654f77 635EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
953039c8 636
1da177e4
LT		 637#else
638static void register_nodes(void)
639{
640 return;
641}
953039c8 642
1da177e4
LT		 643#endif
644
645/* Only valid if CPU is present. */
8a25a2fd
KS		 646static ssize_t show_physical_id(struct device *dev,
647 struct device_attribute *attr, char *buf)
1da177e4 648{
8a25a2fd 649 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 650
8a25a2fd 651 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1da177e4 652}
8a25a2fd 653static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1da177e4
LT		 654
655static int __init topology_init(void)
656{
657 int cpu;
1da177e4
LT		 658
659 register_nodes();
1da177e4
LT		 660 register_cpu_notifier(&sysfs_cpu_nb);
661
0e551954 662 for_each_possible_cpu(cpu) {
1da177e4
LT		 663 struct cpu *c = &per_cpu(cpu_devices, cpu);
664
1da177e4
LT		 665 /*
666 * For now, we just see if the system supports making
667 * the RTAS calls for CPU hotplug. But, there may be a
668 * more comprehensive way to do this for an individual
669 * CPU. For instance, the boot cpu might never be valid
670 * for hotplugging.
671 */
72486f1f
SS		 672 if (ppc_md.cpu_die)
673 c->hotpluggable = 1;
1da177e4 674
72486f1f 675 if (cpu_online(cpu) || c->hotpluggable) {
76b67ed9 676 register_cpu(c, cpu);
1da177e4 677
8a25a2fd 678 device_create_file(&c->dev, &dev_attr_physical_id);
1da177e4
LT		 679 }
680
681 if (cpu_online(cpu))
682 register_cpu_online(cpu);
683 }
efcac658
AK		 684#ifdef CONFIG_PPC64
685 sysfs_create_dscr_default();
686#endif /* CONFIG_PPC64 */
1da177e4
LT		 687
688 return 0;
689}
e9e77ce8 690subsys_initcall(topology_init);
kernel source for telekom puls (alcatel/mediatek)