Commit | Line | Data |
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9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c PM |
13 | #include <linux/tty.h> |
14 | #include <linux/bootmem.h> | |
15 | #include <linux/seq_file.h> | |
16 | #include <linux/root_dev.h> | |
17 | #include <linux/cpu.h> | |
18 | #include <linux/console.h> | |
85218827 | 19 | #include <linux/lmb.h> |
9b6b563c | 20 | |
9b6b563c PM |
21 | #include <asm/io.h> |
22 | #include <asm/prom.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/pgtable.h> | |
9b6b563c | 25 | #include <asm/setup.h> |
9b6b563c PM |
26 | #include <asm/smp.h> |
27 | #include <asm/elf.h> | |
28 | #include <asm/cputable.h> | |
29 | #include <asm/bootx.h> | |
30 | #include <asm/btext.h> | |
31 | #include <asm/machdep.h> | |
32 | #include <asm/uaccess.h> | |
33 | #include <asm/system.h> | |
34 | #include <asm/pmac_feature.h> | |
35 | #include <asm/sections.h> | |
36 | #include <asm/nvram.h> | |
37 | #include <asm/xmon.h> | |
6d7f58b0 | 38 | #include <asm/time.h> |
463ce0e1 | 39 | #include <asm/serial.h> |
51d3082f | 40 | #include <asm/udbg.h> |
9b6b563c | 41 | |
66ba135c SR |
42 | #include "setup.h" |
43 | ||
03501dab PM |
44 | #define DBG(fmt...) |
45 | ||
9b6b563c PM |
46 | extern void bootx_init(unsigned long r4, unsigned long phys); |
47 | ||
80579e1f PM |
48 | int boot_cpuid; |
49 | EXPORT_SYMBOL_GPL(boot_cpuid); | |
50 | int boot_cpuid_phys; | |
51 | ||
9b6b563c PM |
52 | unsigned long ISA_DMA_THRESHOLD; |
53 | unsigned int DMA_MODE_READ; | |
54 | unsigned int DMA_MODE_WRITE; | |
55 | ||
e574d238 PM |
56 | int have_of = 1; |
57 | ||
9b6b563c PM |
58 | #ifdef CONFIG_VGA_CONSOLE |
59 | unsigned long vgacon_remap_base; | |
d003e7a1 | 60 | EXPORT_SYMBOL(vgacon_remap_base); |
9b6b563c PM |
61 | #endif |
62 | ||
9b6b563c PM |
63 | /* |
64 | * These are used in binfmt_elf.c to put aux entries on the stack | |
65 | * for each elf executable being started. | |
66 | */ | |
67 | int dcache_bsize; | |
68 | int icache_bsize; | |
69 | int ucache_bsize; | |
70 | ||
9b6b563c PM |
71 | /* |
72 | * We're called here very early in the boot. We determine the machine | |
73 | * type and call the appropriate low-level setup functions. | |
74 | * -- Cort <cort@fsmlabs.com> | |
75 | * | |
76 | * Note that the kernel may be running at an address which is different | |
77 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
78 | * to access static data (including strings). -- paulus | |
79 | */ | |
4e491d14 | 80 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
81 | { |
82 | unsigned long offset = reloc_offset(); | |
42c4aaad | 83 | struct cpu_spec *spec; |
9b6b563c | 84 | |
dd184343 PM |
85 | /* First zero the BSS -- use memset_io, some platforms don't have |
86 | * caches on yet */ | |
556b09c8 MG |
87 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
88 | __bss_stop - __bss_start); | |
dd184343 | 89 | |
9b6b563c PM |
90 | /* |
91 | * Identify the CPU type and fix up code sections | |
92 | * that depend on which cpu we have. | |
93 | */ | |
974a76f5 | 94 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 95 | |
0909c8c2 | 96 | do_feature_fixups(spec->cpu_features, |
42c4aaad BH |
97 | PTRRELOC(&__start___ftr_fixup), |
98 | PTRRELOC(&__stop___ftr_fixup)); | |
9b6b563c | 99 | |
2d1b2027 KG |
100 | do_lwsync_fixups(spec->cpu_features, |
101 | PTRRELOC(&__start___lwsync_fixup), | |
102 | PTRRELOC(&__stop___lwsync_fixup)); | |
103 | ||
9b6b563c PM |
104 | return KERNELBASE + offset; |
105 | } | |
106 | ||
9b6b563c | 107 | |
9b6b563c PM |
108 | /* |
109 | * Find out what kind of machine we're on and save any data we need | |
110 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
111 | * This is called very early on the boot process, after a minimal | |
112 | * MMU environment has been set up but before MMU_init is called. | |
113 | */ | |
4e491d14 | 114 | notrace void __init machine_init(unsigned long dt_ptr, unsigned long phys) |
9b6b563c | 115 | { |
719c91cc DG |
116 | /* Enable early debugging if any specified (see udbg.h) */ |
117 | udbg_early_init(); | |
51d3082f BH |
118 | |
119 | /* Do some early initialization based on the flat device tree */ | |
9b6b563c PM |
120 | early_init_devtree(__va(dt_ptr)); |
121 | ||
e8222502 | 122 | probe_machine(); |
35499c01 | 123 | |
9b6b563c | 124 | #ifdef CONFIG_6xx |
a0652fc9 PM |
125 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
126 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
127 | ppc_md.power_save = ppc6xx_idle; | |
9b6b563c | 128 | #endif |
9b6b563c | 129 | |
fc4033b2 KG |
130 | #ifdef CONFIG_E500 |
131 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
132 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
133 | ppc_md.power_save = e500_idle; | |
134 | #endif | |
9b6b563c PM |
135 | if (ppc_md.progress) |
136 | ppc_md.progress("id mach(): done", 0x200); | |
137 | } | |
138 | ||
139 | #ifdef CONFIG_BOOKE_WDT | |
140 | /* Checks wdt=x and wdt_period=xx command-line option */ | |
4e491d14 | 141 | notrace int __init early_parse_wdt(char *p) |
9b6b563c PM |
142 | { |
143 | if (p && strncmp(p, "0", 1) != 0) | |
144 | booke_wdt_enabled = 1; | |
145 | ||
146 | return 0; | |
147 | } | |
148 | early_param("wdt", early_parse_wdt); | |
149 | ||
150 | int __init early_parse_wdt_period (char *p) | |
151 | { | |
152 | if (p) | |
153 | booke_wdt_period = simple_strtoul(p, NULL, 0); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | early_param("wdt_period", early_parse_wdt_period); | |
158 | #endif /* CONFIG_BOOKE_WDT */ | |
159 | ||
160 | /* Checks "l2cr=xxxx" command-line option */ | |
161 | int __init ppc_setup_l2cr(char *str) | |
162 | { | |
163 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
164 | unsigned long val = simple_strtoul(str, NULL, 0); | |
165 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
166 | _set_L2CR(0); /* force invalidate by disable cache */ | |
167 | _set_L2CR(val); /* and enable it */ | |
168 | } | |
169 | return 1; | |
170 | } | |
171 | __setup("l2cr=", ppc_setup_l2cr); | |
172 | ||
a78bfbfc RB |
173 | /* Checks "l3cr=xxxx" command-line option */ |
174 | int __init ppc_setup_l3cr(char *str) | |
175 | { | |
176 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
177 | unsigned long val = simple_strtoul(str, NULL, 0); | |
178 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
179 | _set_L3CR(val); /* and enable it */ | |
180 | } | |
181 | return 1; | |
182 | } | |
183 | __setup("l3cr=", ppc_setup_l3cr); | |
184 | ||
9b6b563c PM |
185 | #ifdef CONFIG_GENERIC_NVRAM |
186 | ||
187 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
188 | unsigned char nvram_read_byte(int addr) | |
189 | { | |
190 | if (ppc_md.nvram_read_val) | |
191 | return ppc_md.nvram_read_val(addr); | |
192 | return 0xff; | |
193 | } | |
194 | EXPORT_SYMBOL(nvram_read_byte); | |
195 | ||
196 | void nvram_write_byte(unsigned char val, int addr) | |
197 | { | |
198 | if (ppc_md.nvram_write_val) | |
199 | ppc_md.nvram_write_val(addr, val); | |
200 | } | |
201 | EXPORT_SYMBOL(nvram_write_byte); | |
202 | ||
203 | void nvram_sync(void) | |
204 | { | |
205 | if (ppc_md.nvram_sync) | |
206 | ppc_md.nvram_sync(); | |
207 | } | |
208 | EXPORT_SYMBOL(nvram_sync); | |
209 | ||
210 | #endif /* CONFIG_NVRAM */ | |
211 | ||
9b6b563c PM |
212 | int __init ppc_init(void) |
213 | { | |
9b6b563c | 214 | /* clear the progress line */ |
5e41763a GP |
215 | if (ppc_md.progress) |
216 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 217 | |
9b6b563c PM |
218 | /* call platform init */ |
219 | if (ppc_md.init != NULL) { | |
220 | ppc_md.init(); | |
221 | } | |
222 | return 0; | |
223 | } | |
224 | ||
225 | arch_initcall(ppc_init); | |
226 | ||
85218827 KG |
227 | #ifdef CONFIG_IRQSTACKS |
228 | static void __init irqstack_early_init(void) | |
229 | { | |
230 | unsigned int i; | |
231 | ||
232 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
233 | * as the lmb is limited to lowmem by LMB_REAL_LIMIT */ | |
234 | for_each_possible_cpu(i) { | |
235 | softirq_ctx[i] = (struct thread_info *) | |
236 | __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
237 | hardirq_ctx[i] = (struct thread_info *) | |
238 | __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
239 | } | |
240 | } | |
241 | #else | |
242 | #define irqstack_early_init() | |
243 | #endif | |
244 | ||
bcf0b088 KG |
245 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
246 | static void __init exc_lvl_early_init(void) | |
247 | { | |
248 | unsigned int i; | |
249 | ||
250 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
251 | * as the lmb is limited to lowmem by LMB_REAL_LIMIT */ | |
252 | for_each_possible_cpu(i) { | |
253 | critirq_ctx[i] = (struct thread_info *) | |
254 | __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
255 | #ifdef CONFIG_BOOKE | |
256 | dbgirq_ctx[i] = (struct thread_info *) | |
257 | __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
258 | mcheckirq_ctx[i] = (struct thread_info *) | |
259 | __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
260 | #endif | |
261 | } | |
262 | } | |
263 | #else | |
264 | #define exc_lvl_early_init() | |
265 | #endif | |
266 | ||
9b6b563c PM |
267 | /* Warning, IO base is not yet inited */ |
268 | void __init setup_arch(char **cmdline_p) | |
269 | { | |
846f77b0 ME |
270 | *cmdline_p = cmd_line; |
271 | ||
9b6b563c PM |
272 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
273 | loops_per_jiffy = 500000000 / HZ; | |
274 | ||
9b6b563c | 275 | unflatten_device_tree(); |
a82765b6 | 276 | check_for_initrd(); |
463ce0e1 BH |
277 | |
278 | if (ppc_md.init_early) | |
279 | ppc_md.init_early(); | |
280 | ||
463ce0e1 | 281 | find_legacy_serial_ports(); |
9b6b563c | 282 | |
5ad57078 PM |
283 | smp_setup_cpu_maps(); |
284 | ||
51d3082f BH |
285 | /* Register early console */ |
286 | register_early_udbg_console(); | |
9b6b563c | 287 | |
47679283 ME |
288 | xmon_setup(); |
289 | ||
9b6b563c PM |
290 | /* |
291 | * Set cache line size based on type of cpu as a default. | |
292 | * Systems with OF can look in the properties on the cpu node(s) | |
293 | * for a possibly more accurate value. | |
294 | */ | |
4508dc21 DG |
295 | dcache_bsize = cur_cpu_spec->dcache_bsize; |
296 | icache_bsize = cur_cpu_spec->icache_bsize; | |
297 | ucache_bsize = 0; | |
298 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
299 | ucache_bsize = icache_bsize = dcache_bsize; | |
9b6b563c PM |
300 | |
301 | /* reboot on panic */ | |
302 | panic_timeout = 180; | |
303 | ||
7e990266 KG |
304 | if (ppc_md.panic) |
305 | setup_panic(); | |
306 | ||
4846c5de | 307 | init_mm.start_code = (unsigned long)_stext; |
9b6b563c PM |
308 | init_mm.end_code = (unsigned long) _etext; |
309 | init_mm.end_data = (unsigned long) _edata; | |
49b09853 | 310 | init_mm.brk = klimit; |
9b6b563c | 311 | |
bcf0b088 KG |
312 | exc_lvl_early_init(); |
313 | ||
85218827 KG |
314 | irqstack_early_init(); |
315 | ||
9b6b563c PM |
316 | /* set up the bootmem stuff with available memory */ |
317 | do_init_bootmem(); | |
318 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab); | |
319 | ||
9b6b563c PM |
320 | #ifdef CONFIG_DUMMY_CONSOLE |
321 | conswitchp = &dummy_con; | |
322 | #endif | |
323 | ||
38db7e74 GL |
324 | if (ppc_md.setup_arch) |
325 | ppc_md.setup_arch(); | |
9b6b563c PM |
326 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
327 | ||
328 | paging_init(); | |
9b6b563c | 329 | } |