[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / ptrace-common.h

/*
 *  linux/arch/ppc64/kernel/ptrace-common.h
 *
 *    Copyright (c) 2002 Stephen Rothwell, IBM Coproration
 *    Extracted from ptrace.c and ptrace32.c
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file README.legal in the main directory of
 * this archive for more details.
 */

#ifndef _PPC64_PTRACE_COMMON_H
#define _PPC64_PTRACE_COMMON_H

#include <linux/config.h>
#include <asm/system.h>

/*
 * Set of msr bits that gdb can change on behalf of a process.
 */
#define MSR_DEBUGCHANGE	(MSR_FE0 | MSR_SE | MSR_BE | MSR_FE1)

/*
 * Get contents of register REGNO in task TASK.
 */
static inline unsigned long get_reg(struct task_struct *task, int regno)
{
	unsigned long tmp = 0;

	/*
	 * Put the correct FP bits in, they might be wrong as a result
	 * of our lazy FP restore.
	 */
	if (regno == PT_MSR) {
		tmp = ((unsigned long *)task->thread.regs)[PT_MSR];
		tmp |= task->thread.fpexc_mode;
	} else if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
		tmp = ((unsigned long *)task->thread.regs)[regno];
	}

	return tmp;
}

/*
 * Write contents of register REGNO in task TASK.
 */
static inline int put_reg(struct task_struct *task, int regno,
			  unsigned long data)
{
	if (regno < PT_SOFTE) {
		if (regno == PT_MSR)
			data = (data & MSR_DEBUGCHANGE)
				| (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
		((unsigned long *)task->thread.regs)[regno] = data;
		return 0;
	}
	return -EIO;
}

static inline void set_single_step(struct task_struct *task)
{
	struct pt_regs *regs = task->thread.regs;
	if (regs != NULL)
		regs->msr |= MSR_SE;
	set_tsk_thread_flag(task, TIF_SINGLESTEP);
}

static inline void clear_single_step(struct task_struct *task)
{
	struct pt_regs *regs = task->thread.regs;
	if (regs != NULL)
		regs->msr &= ~MSR_SE;
	clear_tsk_thread_flag(task, TIF_SINGLESTEP);
}

#ifdef CONFIG_ALTIVEC
/*
 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
 * The transfer totals 34 quadword.  Quadwords 0-31 contain the
 * corresponding vector registers.  Quadword 32 contains the vscr as the
 * last word (offset 12) within that quadword.  Quadword 33 contains the
 * vrsave as the first word (offset 0) within the quadword.
 *
 * This definition of the VMX state is compatible with the current PPC32
 * ptrace interface.  This allows signal handling and ptrace to use the
 * same structures.  This also simplifies the implementation of a bi-arch
 * (combined (32- and 64-bit) gdb.
 */

/*
 * Get contents of AltiVec register state in task TASK
 */
static inline int get_vrregs(unsigned long __user *data,
			     struct task_struct *task)
{
	unsigned long regsize;

	/* copy AltiVec registers VR[0] .. VR[31] */
	regsize = 32 * sizeof(vector128);
	if (copy_to_user(data, task->thread.vr, regsize))
		return -EFAULT;
	data += (regsize / sizeof(unsigned long));

	/* copy VSCR */
	regsize = 1 * sizeof(vector128);
	if (copy_to_user(data, &task->thread.vscr, regsize))
		return -EFAULT;
	data += (regsize / sizeof(unsigned long));

	/* copy VRSAVE */
	if (put_user(task->thread.vrsave, (u32 __user *)data))
		return -EFAULT;

	return 0;
}

/*
 * Write contents of AltiVec register state into task TASK.
 */
static inline int set_vrregs(struct task_struct *task,
			     unsigned long __user *data)
{
	unsigned long regsize;

	/* copy AltiVec registers VR[0] .. VR[31] */
	regsize = 32 * sizeof(vector128);
	if (copy_from_user(task->thread.vr, data, regsize))
		return -EFAULT;
	data += (regsize / sizeof(unsigned long));

	/* copy VSCR */
	regsize = 1 * sizeof(vector128);
	if (copy_from_user(&task->thread.vscr, data, regsize))
		return -EFAULT;
	data += (regsize / sizeof(unsigned long));

	/* copy VRSAVE */
	if (get_user(task->thread.vrsave, (u32 __user *)data))
		return -EFAULT;

	return 0;
}
#endif

static inline int ptrace_set_debugreg(struct task_struct *task,
				      unsigned long addr, unsigned long data)
{
	/* We only support one DABR and no IABRS at the moment */
	if (addr > 0)
		return -EINVAL;

	/* The bottom 3 bits are flags */
	if ((data & ~0x7UL) >= TASK_SIZE)
		return -EIO;

	/* Ensure translation is on */
	if (data && !(data & DABR_TRANSLATION))
		return -EIO;

	task->thread.dabr = data;
	return 0;
}

#endif /* _PPC64_PTRACE_COMMON_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/ppc64/kernel/ptrace-common.h
	3	*
	4	* Copyright (c) 2002 Stephen Rothwell, IBM Coproration
	5	* Extracted from ptrace.c and ptrace32.c
	6	*
	7	* This file is subject to the terms and conditions of the GNU General
	8	* Public License. See the file README.legal in the main directory of
	9	* this archive for more details.
	10	*/
	11
	12	#ifndef _PPC64_PTRACE_COMMON_H
	13	#define _PPC64_PTRACE_COMMON_H
962bca7f RJ	14
962bca7f RJ	15	#include <linux/config.h>
fd9648df	16	#include <asm/system.h>
962bca7f	17
1da177e4 LT	18	/*
	19	* Set of msr bits that gdb can change on behalf of a process.
	20	*/
	21	#define MSR_DEBUGCHANGE (MSR_FE0 \| MSR_SE \| MSR_BE \| MSR_FE1)
	22
	23	/*
	24	* Get contents of register REGNO in task TASK.
	25	*/
	26	static inline unsigned long get_reg(struct task_struct *task, int regno)
	27	{
	28	unsigned long tmp = 0;
	29
	30	/*
	31	* Put the correct FP bits in, they might be wrong as a result
	32	* of our lazy FP restore.
	33	*/
	34	if (regno == PT_MSR) {
	35	tmp = ((unsigned long *)task->thread.regs)[PT_MSR];
	36	tmp \|= task->thread.fpexc_mode;
	37	} else if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
	38	tmp = ((unsigned long *)task->thread.regs)[regno];
	39	}
	40
	41	return tmp;
	42	}
	43
	44	/*
	45	* Write contents of register REGNO in task TASK.
	46	*/
	47	static inline int put_reg(struct task_struct *task, int regno,
	48	unsigned long data)
	49	{
	50	if (regno < PT_SOFTE) {
	51	if (regno == PT_MSR)
	52	data = (data & MSR_DEBUGCHANGE)
	53	\| (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
	54	((unsigned long *)task->thread.regs)[regno] = data;
	55	return 0;
	56	}
	57	return -EIO;
	58	}
	59
	60	static inline void set_single_step(struct task_struct *task)
	61	{
	62	struct pt_regs *regs = task->thread.regs;
	63	if (regs != NULL)
	64	regs->msr \|= MSR_SE;
b5e2fc1c	65	set_tsk_thread_flag(task, TIF_SINGLESTEP);
1da177e4 LT	66	}
	67
	68	static inline void clear_single_step(struct task_struct *task)
	69	{
	70	struct pt_regs *regs = task->thread.regs;
	71	if (regs != NULL)
	72	regs->msr &= ~MSR_SE;
b5e2fc1c	73	clear_tsk_thread_flag(task, TIF_SINGLESTEP);
1da177e4 LT	74	}
1da177e4 LT	75
962bca7f RJ	76	#ifdef CONFIG_ALTIVEC
	77	/*
	78	* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
	79	* The transfer totals 34 quadword. Quadwords 0-31 contain the
	80	* corresponding vector registers. Quadword 32 contains the vscr as the
	81	* last word (offset 12) within that quadword. Quadword 33 contains the
	82	* vrsave as the first word (offset 0) within the quadword.
	83	*
	84	* This definition of the VMX state is compatible with the current PPC32
	85	* ptrace interface. This allows signal handling and ptrace to use the
	86	* same structures. This also simplifies the implementation of a bi-arch
	87	* (combined (32- and 64-bit) gdb.
	88	*/
	89
	90	/*
	91	* Get contents of AltiVec register state in task TASK
	92	*/
	93	static inline int get_vrregs(unsigned long __user *data,
	94	struct task_struct *task)
	95	{
	96	unsigned long regsize;
	97
	98	/* copy AltiVec registers VR[0] .. VR[31] */
	99	regsize = 32 * sizeof(vector128);
	100	if (copy_to_user(data, task->thread.vr, regsize))
	101	return -EFAULT;
	102	data += (regsize / sizeof(unsigned long));
	103
	104	/* copy VSCR */
	105	regsize = 1 * sizeof(vector128);
	106	if (copy_to_user(data, &task->thread.vscr, regsize))
	107	return -EFAULT;
	108	data += (regsize / sizeof(unsigned long));
	109
	110	/* copy VRSAVE */
	111	if (put_user(task->thread.vrsave, (u32 __user *)data))
	112	return -EFAULT;
	113
	114	return 0;
	115	}
	116
	117	/*
	118	* Write contents of AltiVec register state into task TASK.
	119	*/
	120	static inline int set_vrregs(struct task_struct *task,
	121	unsigned long __user *data)
	122	{
	123	unsigned long regsize;
	124
	125	/* copy AltiVec registers VR[0] .. VR[31] */
	126	regsize = 32 * sizeof(vector128);
	127	if (copy_from_user(task->thread.vr, data, regsize))
	128	return -EFAULT;
	129	data += (regsize / sizeof(unsigned long));
	130
	131	/* copy VSCR */
	132	regsize = 1 * sizeof(vector128);
	133	if (copy_from_user(&task->thread.vscr, data, regsize))
	134	return -EFAULT;
	135	data += (regsize / sizeof(unsigned long));
	136
	137	/* copy VRSAVE */
	138	if (get_user(task->thread.vrsave, (u32 __user *)data))
	139	return -EFAULT;
140
141	return 0;
142	}
143	#endif
144
fd9648df AB	145	static inline int ptrace_set_debugreg(struct task_struct *task,
	146	unsigned long addr, unsigned long data)
	147	{
	148	/* We only support one DABR and no IABRS at the moment */
	149	if (addr > 0)
	150	return -EINVAL;
	151
	152	/* The bottom 3 bits are flags */
	153	if ((data & ~0x7UL) >= TASK_SIZE)
	154	return -EIO;
	155
	156	/* Ensure translation is on */
	157	if (data && !(data & DABR_TRANSLATION))
	158	return -EIO;
	159
	160	task->thread.dabr = data;
	161	return 0;
	162	}
	163
1da177e4	164	#endif /* _PPC64_PTRACE_COMMON_H */