Commit | Line | Data |
---|---|---|
4da52960 PM |
1 | /* |
2 | * Performance counter support for POWER7 processors. | |
3 | * | |
4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
cdd6c482 | 12 | #include <linux/perf_event.h> |
079b3c56 | 13 | #include <linux/string.h> |
4da52960 | 14 | #include <asm/reg.h> |
079b3c56 | 15 | #include <asm/cputable.h> |
4da52960 PM |
16 | |
17 | /* | |
18 | * Bits in event code for POWER7 | |
19 | */ | |
20 | #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */ | |
21 | #define PM_PMC_MSK 0xf | |
22 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | |
23 | #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */ | |
24 | #define PM_UNIT_MSK 0xf | |
25 | #define PM_COMBINE_SH 11 /* Combined event bit */ | |
26 | #define PM_COMBINE_MSK 1 | |
27 | #define PM_COMBINE_MSKS 0x800 | |
28 | #define PM_L2SEL_SH 8 /* L2 event select */ | |
29 | #define PM_L2SEL_MSK 7 | |
30 | #define PM_PMCSEL_MSK 0xff | |
31 | ||
32 | /* | |
33 | * Bits in MMCR1 for POWER7 | |
34 | */ | |
35 | #define MMCR1_TTM0SEL_SH 60 | |
36 | #define MMCR1_TTM1SEL_SH 56 | |
37 | #define MMCR1_TTM2SEL_SH 52 | |
38 | #define MMCR1_TTM3SEL_SH 48 | |
39 | #define MMCR1_TTMSEL_MSK 0xf | |
40 | #define MMCR1_L2SEL_SH 45 | |
41 | #define MMCR1_L2SEL_MSK 7 | |
42 | #define MMCR1_PMC1_COMBINE_SH 35 | |
43 | #define MMCR1_PMC2_COMBINE_SH 34 | |
44 | #define MMCR1_PMC3_COMBINE_SH 33 | |
45 | #define MMCR1_PMC4_COMBINE_SH 32 | |
46 | #define MMCR1_PMC1SEL_SH 24 | |
47 | #define MMCR1_PMC2SEL_SH 16 | |
48 | #define MMCR1_PMC3SEL_SH 8 | |
49 | #define MMCR1_PMC4SEL_SH 0 | |
50 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | |
51 | #define MMCR1_PMCSEL_MSK 0xff | |
52 | ||
4da52960 PM |
53 | /* |
54 | * Layout of constraint bits: | |
55 | * 6666555555555544444444443333333333222222222211111111110000000000 | |
56 | * 3210987654321098765432109876543210987654321098765432109876543210 | |
57 | * [ ><><><><><><> | |
58 | * NC P6P5P4P3P2P1 | |
59 | * | |
60 | * NC - number of counters | |
61 | * 15: NC error 0x8000 | |
62 | * 12-14: number of events needing PMC1-4 0x7000 | |
63 | * | |
64 | * P6 | |
65 | * 11: P6 error 0x800 | |
66 | * 10-11: Count of events needing PMC6 | |
67 | * | |
68 | * P1..P5 | |
69 | * 0-9: Count of events needing PMC1..PMC5 | |
70 | */ | |
71 | ||
448d64f8 PM |
72 | static int power7_get_constraint(u64 event, unsigned long *maskp, |
73 | unsigned long *valp) | |
4da52960 PM |
74 | { |
75 | int pmc, sh; | |
448d64f8 | 76 | unsigned long mask = 0, value = 0; |
4da52960 PM |
77 | |
78 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
79 | if (pmc) { | |
80 | if (pmc > 6) | |
81 | return -1; | |
82 | sh = (pmc - 1) * 2; | |
83 | mask |= 2 << sh; | |
84 | value |= 1 << sh; | |
85 | if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) | |
86 | return -1; | |
87 | } | |
88 | if (pmc < 5) { | |
89 | /* need a counter from PMC1-4 set */ | |
90 | mask |= 0x8000; | |
91 | value |= 0x1000; | |
92 | } | |
93 | *maskp = mask; | |
94 | *valp = value; | |
95 | return 0; | |
96 | } | |
97 | ||
98 | #define MAX_ALT 2 /* at most 2 alternatives for any event */ | |
99 | ||
100 | static const unsigned int event_alternatives[][MAX_ALT] = { | |
101 | { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ | |
102 | { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ | |
103 | { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ | |
104 | }; | |
105 | ||
106 | /* | |
107 | * Scan the alternatives table for a match and return the | |
108 | * index into the alternatives table if found, else -1. | |
109 | */ | |
110 | static int find_alternative(u64 event) | |
111 | { | |
112 | int i, j; | |
113 | ||
114 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | |
115 | if (event < event_alternatives[i][0]) | |
116 | break; | |
117 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | |
118 | if (event == event_alternatives[i][j]) | |
119 | return i; | |
120 | } | |
121 | return -1; | |
122 | } | |
123 | ||
124 | static s64 find_alternative_decode(u64 event) | |
125 | { | |
126 | int pmc, psel; | |
127 | ||
128 | /* this only handles the 4x decode events */ | |
129 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
130 | psel = event & PM_PMCSEL_MSK; | |
131 | if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) | |
132 | return event - (1 << PM_PMC_SH) + 8; | |
133 | if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48) | |
134 | return event + (1 << PM_PMC_SH) - 8; | |
135 | return -1; | |
136 | } | |
137 | ||
138 | static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | |
139 | { | |
140 | int i, j, nalt = 1; | |
141 | s64 ae; | |
142 | ||
143 | alt[0] = event; | |
144 | nalt = 1; | |
145 | i = find_alternative(event); | |
146 | if (i >= 0) { | |
147 | for (j = 0; j < MAX_ALT; ++j) { | |
148 | ae = event_alternatives[i][j]; | |
149 | if (ae && ae != event) | |
150 | alt[nalt++] = ae; | |
151 | } | |
152 | } else { | |
153 | ae = find_alternative_decode(event); | |
154 | if (ae > 0) | |
155 | alt[nalt++] = ae; | |
156 | } | |
157 | ||
158 | if (flags & PPMU_ONLY_COUNT_RUN) { | |
159 | /* | |
160 | * We're only counting in RUN state, | |
161 | * so PM_CYC is equivalent to PM_RUN_CYC | |
162 | * and PM_INST_CMPL === PM_RUN_INST_CMPL. | |
163 | * This doesn't include alternatives that don't provide | |
164 | * any extra flexibility in assigning PMCs. | |
165 | */ | |
166 | j = nalt; | |
167 | for (i = 0; i < nalt; ++i) { | |
168 | switch (alt[i]) { | |
169 | case 0x1e: /* PM_CYC */ | |
170 | alt[j++] = 0x600f4; /* PM_RUN_CYC */ | |
171 | break; | |
172 | case 0x600f4: /* PM_RUN_CYC */ | |
173 | alt[j++] = 0x1e; | |
174 | break; | |
175 | case 0x2: /* PM_PPC_CMPL */ | |
176 | alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ | |
177 | break; | |
178 | case 0x500fa: /* PM_RUN_INST_CMPL */ | |
179 | alt[j++] = 0x2; /* PM_PPC_CMPL */ | |
180 | break; | |
181 | } | |
182 | } | |
183 | nalt = j; | |
184 | } | |
185 | ||
186 | return nalt; | |
187 | } | |
188 | ||
189 | /* | |
190 | * Returns 1 if event counts things relating to marked instructions | |
191 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | |
192 | */ | |
193 | static int power7_marked_instr_event(u64 event) | |
194 | { | |
195 | int pmc, psel; | |
196 | int unit; | |
197 | ||
198 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
199 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | |
200 | psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */ | |
201 | if (pmc >= 5) | |
202 | return 0; | |
203 | ||
204 | switch (psel >> 4) { | |
205 | case 2: | |
206 | return pmc == 2 || pmc == 4; | |
207 | case 3: | |
208 | if (psel == 0x3c) | |
209 | return pmc == 1; | |
210 | if (psel == 0x3e) | |
211 | return pmc != 2; | |
212 | return 1; | |
213 | case 4: | |
214 | case 5: | |
215 | return unit == 0xd; | |
216 | case 6: | |
217 | if (psel == 0x64) | |
218 | return pmc >= 3; | |
219 | case 8: | |
220 | return unit == 0xd; | |
221 | } | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static int power7_compute_mmcr(u64 event[], int n_ev, | |
448d64f8 | 226 | unsigned int hwc[], unsigned long mmcr[]) |
4da52960 | 227 | { |
448d64f8 | 228 | unsigned long mmcr1 = 0; |
81cd5ae3 | 229 | unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS; |
4da52960 PM |
230 | unsigned int pmc, unit, combine, l2sel, psel; |
231 | unsigned int pmc_inuse = 0; | |
232 | int i; | |
233 | ||
234 | /* First pass to count resource use */ | |
235 | for (i = 0; i < n_ev; ++i) { | |
236 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
237 | if (pmc) { | |
238 | if (pmc > 6) | |
239 | return -1; | |
240 | if (pmc_inuse & (1 << (pmc - 1))) | |
241 | return -1; | |
242 | pmc_inuse |= 1 << (pmc - 1); | |
243 | } | |
244 | } | |
245 | ||
246 | /* Second pass: assign PMCs, set all MMCR1 fields */ | |
247 | for (i = 0; i < n_ev; ++i) { | |
248 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
249 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | |
250 | combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK; | |
251 | l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK; | |
252 | psel = event[i] & PM_PMCSEL_MSK; | |
253 | if (!pmc) { | |
254 | /* Bus event or any-PMC direct event */ | |
255 | for (pmc = 0; pmc < 4; ++pmc) { | |
256 | if (!(pmc_inuse & (1 << pmc))) | |
257 | break; | |
258 | } | |
259 | if (pmc >= 4) | |
260 | return -1; | |
261 | pmc_inuse |= 1 << pmc; | |
262 | } else { | |
263 | /* Direct or decoded event */ | |
264 | --pmc; | |
265 | } | |
266 | if (pmc <= 3) { | |
448d64f8 PM |
267 | mmcr1 |= (unsigned long) unit |
268 | << (MMCR1_TTM0SEL_SH - 4 * pmc); | |
269 | mmcr1 |= (unsigned long) combine | |
270 | << (MMCR1_PMC1_COMBINE_SH - pmc); | |
4da52960 PM |
271 | mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); |
272 | if (unit == 6) /* L2 events */ | |
448d64f8 PM |
273 | mmcr1 |= (unsigned long) l2sel |
274 | << MMCR1_L2SEL_SH; | |
4da52960 PM |
275 | } |
276 | if (power7_marked_instr_event(event[i])) | |
277 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
278 | hwc[i] = pmc; | |
279 | } | |
280 | ||
281 | /* Return MMCRx values */ | |
282 | mmcr[0] = 0; | |
283 | if (pmc_inuse & 1) | |
284 | mmcr[0] = MMCR0_PMC1CE; | |
285 | if (pmc_inuse & 0x3e) | |
286 | mmcr[0] |= MMCR0_PMCjCE; | |
287 | mmcr[1] = mmcr1; | |
288 | mmcr[2] = mmcra; | |
289 | return 0; | |
290 | } | |
291 | ||
448d64f8 | 292 | static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) |
4da52960 PM |
293 | { |
294 | if (pmc <= 3) | |
448d64f8 | 295 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); |
4da52960 PM |
296 | } |
297 | ||
298 | static int power7_generic_events[] = { | |
4c921126 JSR |
299 | [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, |
300 | [PERF_COUNT_HW_INSTRUCTIONS] = 2, | |
301 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ | |
302 | [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */ | |
303 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */ | |
304 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */ | |
4da52960 PM |
305 | }; |
306 | ||
106b506c PM |
307 | #define C(x) PERF_COUNT_HW_CACHE_##x |
308 | ||
309 | /* | |
310 | * Table of generalized cache-related events. | |
311 | * 0 means not supported, -1 means nonsensical, other values | |
312 | * are event codes. | |
313 | */ | |
314 | static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | |
315 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | |
a3df6f7d | 316 | [C(OP_READ)] = { 0xc880, 0x400f0 }, |
106b506c PM |
317 | [C(OP_WRITE)] = { 0, 0x300f0 }, |
318 | [C(OP_PREFETCH)] = { 0xd8b8, 0 }, | |
319 | }, | |
320 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | |
321 | [C(OP_READ)] = { 0, 0x200fc }, | |
322 | [C(OP_WRITE)] = { -1, -1 }, | |
323 | [C(OP_PREFETCH)] = { 0x408a, 0 }, | |
324 | }, | |
8be6e8f3 | 325 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ |
a3df6f7d PM |
326 | [C(OP_READ)] = { 0x16080, 0x26080 }, |
327 | [C(OP_WRITE)] = { 0x16082, 0x26082 }, | |
106b506c PM |
328 | [C(OP_PREFETCH)] = { 0, 0 }, |
329 | }, | |
330 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | |
331 | [C(OP_READ)] = { 0, 0x300fc }, | |
332 | [C(OP_WRITE)] = { -1, -1 }, | |
333 | [C(OP_PREFETCH)] = { -1, -1 }, | |
334 | }, | |
335 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | |
336 | [C(OP_READ)] = { 0, 0x400fc }, | |
337 | [C(OP_WRITE)] = { -1, -1 }, | |
338 | [C(OP_PREFETCH)] = { -1, -1 }, | |
339 | }, | |
340 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | |
341 | [C(OP_READ)] = { 0x10068, 0x400f6 }, | |
342 | [C(OP_WRITE)] = { -1, -1 }, | |
343 | [C(OP_PREFETCH)] = { -1, -1 }, | |
344 | }, | |
345 | }; | |
346 | ||
079b3c56 PM |
347 | static struct power_pmu power7_pmu = { |
348 | .name = "POWER7", | |
448d64f8 PM |
349 | .n_counter = 6, |
350 | .max_alternatives = MAX_ALT + 1, | |
351 | .add_fields = 0x1555ul, | |
352 | .test_adder = 0x3000ul, | |
353 | .compute_mmcr = power7_compute_mmcr, | |
354 | .get_constraint = power7_get_constraint, | |
355 | .get_alternatives = power7_get_alternatives, | |
356 | .disable_pmc = power7_disable_pmc, | |
0a456fc5 | 357 | .flags = PPMU_ALT_SIPR, |
448d64f8 PM |
358 | .n_generic = ARRAY_SIZE(power7_generic_events), |
359 | .generic_events = power7_generic_events, | |
360 | .cache_events = &power7_cache_events, | |
4da52960 | 361 | }; |
079b3c56 PM |
362 | |
363 | static int init_power7_pmu(void) | |
364 | { | |
e0d82a0a BH |
365 | if (!cur_cpu_spec->oprofile_cpu_type || |
366 | strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) | |
079b3c56 PM |
367 | return -ENODEV; |
368 | ||
369 | return register_power_pmu(&power7_pmu); | |
370 | } | |
371 | ||
372 | arch_initcall(init_power7_pmu); |