[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / pci_64.c

/*
 * Port for PPC64 David Engebretsen, IBM Corp.
 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
 * 
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/mm.h>
#include <linux/list.h>
#include <linux/syscalls.h>
#include <linux/irq.h>
#include <linux/vmalloc.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/ppc-pci.h>

/* pci_io_base -- the base address from which io bars are offsets.
 * This is the lowest I/O base address (so bar values are always positive),
 * and it *must* be the start of ISA space if an ISA bus exists because
 * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
 * is mapped on the first 64K of IO space
 */
unsigned long pci_io_base = ISA_IO_BASE;
EXPORT_SYMBOL(pci_io_base);

static int __init pcibios_init(void)
{
	struct pci_controller *hose, *tmp;

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

	/* For now, override phys_mem_access_prot. If we need it,g
	 * later, we may move that initialization to each ppc_md
	 */
	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	/* On ppc64, we always enable PCI domains and we keep domain 0
	 * backward compatible in /proc for video cards
	 */
	pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		pcibios_scan_phb(hose);
		pci_bus_add_devices(hose->bus);
	}

	/* Call common code to handle resource allocation */
	pcibios_resource_survey();

	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");

	return 0;
}

subsys_initcall(pcibios_init);

int pcibios_unmap_io_space(struct pci_bus *bus)
{
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this is not a PHB, we only flush the hash table over
	 * the area mapped by this bridge. We don't play with the PTE
	 * mappings since we might have to deal with sub-page alignemnts
	 * so flushing the hash table is the only sane way to make sure
	 * that no hash entries are covering that removed bridge area
	 * while still allowing other busses overlapping those pages
	 *
	 * Note: If we ever support P2P hotplug on Book3E, we'll have
	 * to do an appropriate TLB flush here too
	 */
	if (bus->self) {
#ifdef CONFIG_PPC_STD_MMU_64
		struct resource *res = bus->resource[0];
#endif

		pr_debug("IO unmapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));

#ifdef CONFIG_PPC_STD_MMU_64
		__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
					 res->end + _IO_BASE + 1);
#endif
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);

	/* Check if we have IOs allocated */
	if (hose->io_base_alloc == 0)
		return 0;

	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  alloc=0x%p\n", hose->io_base_alloc);

	/* This is a PHB, we fully unmap the IO area */
	vunmap(hose->io_base_alloc);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);

static int pcibios_map_phb_io_space(struct pci_controller *hose)
{
	struct vm_struct *area;
	unsigned long phys_page;
	unsigned long size_page;
	unsigned long io_virt_offset;

	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);

	/* Make sure IO area address is clear */
	hose->io_base_alloc = NULL;

	/* If there's no IO to map on that bus, get away too */
	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
		return 0;

	/* Let's allocate some IO space for that guy. We don't pass
	 * VM_IOREMAP because we don't care about alignment tricks that
	 * the core does in that case. Maybe we should due to stupid card
	 * with incomplete address decoding but I'd rather not deal with
	 * those outside of the reserved 64K legacy region.
	 */
	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	if (area == NULL)
		return -ENOMEM;
	hose->io_base_alloc = area->addr;
	hose->io_base_virt = (void __iomem *)(area->addr +
					      hose->io_base_phys - phys_page);

	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
		 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
	pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
		 hose->pci_io_size, size_page);

	/* Establish the mapping */
	if (__ioremap_at(phys_page, area->addr, size_page,
			 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
		return -ENOMEM;

	/* Fixup hose IO resource */
	io_virt_offset = pcibios_io_space_offset(hose);
	hose->io_resource.start += io_virt_offset;
	hose->io_resource.end += io_virt_offset;

	pr_debug("  hose->io_resource=%pR\n", &hose->io_resource);

	return 0;
}

int pcibios_map_io_space(struct pci_bus *bus)
{
	WARN_ON(bus == NULL);

	/* If this not a PHB, nothing to do, page tables still exist and
	 * thus HPTEs will be faulted in when needed
	 */
	if (bus->self) {
		pr_debug("IO mapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));
		pr_debug("  virt=0x%016llx...0x%016llx\n",
			 bus->resource[0]->start + _IO_BASE,
			 bus->resource[0]->end + _IO_BASE);
		return 0;
	}

	return pcibios_map_phb_io_space(pci_bus_to_host(bus));
}
EXPORT_SYMBOL_GPL(pcibios_map_io_space);

void pcibios_setup_phb_io_space(struct pci_controller *hose)
{
	pcibios_map_phb_io_space(hose);
}

#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

long sys_pciconfig_iobase(long which, unsigned long in_bus,
			  unsigned long in_devfn)
{
	struct pci_controller* hose;
	struct list_head *ln;
	struct pci_bus *bus = NULL;
	struct device_node *hose_node;

	/* Argh ! Please forgive me for that hack, but that's the
	 * simplest way to get existing XFree to not lockup on some
	 * G5 machines... So when something asks for bus 0 io base
	 * (bus 0 is HT root), we return the AGP one instead.
	 */
	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
		struct device_node *agp;

		agp = of_find_compatible_node(NULL, NULL, "u3-agp");
		if (agp)
			in_bus = 0xf0;
		of_node_put(agp);
	}

	/* That syscall isn't quite compatible with PCI domains, but it's
	 * used on pre-domains setup. We return the first match
	 */

	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
		bus = pci_bus_b(ln);
		if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
			break;
		bus = NULL;
	}
	if (bus == NULL || bus->dev.of_node == NULL)
		return -ENODEV;

	hose_node = bus->dev.of_node;
	hose = PCI_DN(hose_node)->phb;

	switch (which) {
	case IOBASE_BRIDGE_NUMBER:
		return (long)hose->first_busno;
	case IOBASE_MEMORY:
		return (long)hose->pci_mem_offset;
	case IOBASE_IO:
		return (long)hose->io_base_phys;
	case IOBASE_ISA_IO:
		return (long)isa_io_base;
	case IOBASE_ISA_MEM:
		return -EINVAL;
	}

	return -EOPNOTSUPP;
}

#ifdef CONFIG_NUMA
int pcibus_to_node(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);
	return phb->node;
}
EXPORT_SYMBOL(pcibus_to_node);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Port for PPC64 David Engebretsen, IBM Corp.
	3	* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
	4	*
	5	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	6	* Rework, based on alpha PCI code.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#undef DEBUG
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/bootmem.h>
66b15db6	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/mm.h>
1da177e4 LT	23	#include <linux/list.h>
b2ad7b5e	24	#include <linux/syscalls.h>
6e99e458	25	#include <linux/irq.h>
3d5134ee	26	#include <linux/vmalloc.h>
1da177e4 LT	27
	28	#include <asm/processor.h>
	29	#include <asm/io.h>
	30	#include <asm/prom.h>
	31	#include <asm/pci-bridge.h>
	32	#include <asm/byteorder.h>
1da177e4	33	#include <asm/machdep.h>
d387899f	34	#include <asm/ppc-pci.h>
1da177e4	35
1da177e4 LT	36	/* pci_io_base -- the base address from which io bars are offsets.
	37	* This is the lowest I/O base address (so bar values are always positive),
	38	* and it must be the start of ISA space if an ISA bus exists because
3d5134ee BH	39	* ISA drivers use hard coded offsets. If no ISA bus exists nothing
3d5134ee BH	40	* is mapped on the first 64K of IO space
1da177e4	41	*/
3d5134ee	42	unsigned long pci_io_base = ISA_IO_BASE;
1da177e4 LT	43	EXPORT_SYMBOL(pci_io_base);
1da177e4 LT	44
1da177e4 LT	45	static int __init pcibios_init(void)
	46	{
	47	struct pci_controller hose, tmp;
1da177e4	48
3fd94c6b BH	49	printk(KERN_INFO "PCI: Probing PCI hardware\n");
3fd94c6b BH	50
53280323	51	/* For now, override phys_mem_access_prot. If we need it,g
1da177e4 LT	52	* later, we may move that initialization to each ppc_md
	53	*/
	54	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	55
1fd0f525 BH	56	/* On ppc64, we always enable PCI domains and we keep domain 0
	57	* backward compatible in /proc for video cards
	58	*/
0e47ff1c	59	pci_add_flags(PCI_ENABLE_PROC_DOMAINS \| PCI_COMPAT_DOMAIN_0);
1fd0f525	60
1da177e4	61	/* Scan all of the recorded PCI controllers. */
92eb4602	62	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
b5d937de	63	pcibios_scan_phb(hose);
92eb4602 JR	64	pci_bus_add_devices(hose->bus);
92eb4602 JR	65	}
1da177e4	66
3fd94c6b BH	67	/* Call common code to handle resource allocation */
3fd94c6b BH	68	pcibios_resource_survey();
1da177e4	69
e884e9c5	70	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
1da177e4 LT	71
	72	return 0;
	73	}
	74
	75	subsys_initcall(pcibios_init);
	76
3d5134ee	77	int pcibios_unmap_io_space(struct pci_bus *bus)
1da177e4	78	{
3d5134ee	79	struct pci_controller *hose;
1da177e4	80
3d5134ee	81	WARN_ON(bus == NULL);
de821204	82
3d5134ee BH	83	/* If this is not a PHB, we only flush the hash table over
	84	* the area mapped by this bridge. We don't play with the PTE
	85	* mappings since we might have to deal with sub-page alignemnts
	86	* so flushing the hash table is the only sane way to make sure
	87	* that no hash entries are covering that removed bridge area
	88	* while still allowing other busses overlapping those pages
94491685 BH	89	*
	90	* Note: If we ever support P2P hotplug on Book3E, we'll have
	91	* to do an appropriate TLB flush here too
3d5134ee BH	92	*/
3d5134ee BH	93	if (bus->self) {
ce7a35c7	94	#ifdef CONFIG_PPC_STD_MMU_64
3d5134ee	95	struct resource *res = bus->resource[0];
ce7a35c7	96	#endif
1da177e4	97
b0494bc8 BH	98	pr_debug("IO unmapping for PCI-PCI bridge %s\n",
b0494bc8 BH	99	pci_name(bus->self));
de821204	100
94491685	101	#ifdef CONFIG_PPC_STD_MMU_64
3d5134ee	102	__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
b30115ea	103	res->end + _IO_BASE + 1);
94491685	104	#endif
3d5134ee BH	105	return 0;
3d5134ee BH	106	}
1da177e4	107
3d5134ee BH	108	/* Get the host bridge */
3d5134ee BH	109	hose = pci_bus_to_host(bus);
1da177e4	110
3d5134ee BH	111	/* Check if we have IOs allocated */
	112	if (hose->io_base_alloc == 0)
	113	return 0;
de821204	114
b0494bc8 BH	115	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
b0494bc8 BH	116	pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
1da177e4	117
3d5134ee BH	118	/* This is a PHB, we fully unmap the IO area */
3d5134ee BH	119	vunmap(hose->io_base_alloc);
1da177e4	120
3d5134ee	121	return 0;
1da177e4	122	}
3d5134ee	123	EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
1da177e4	124
cad5cef6	125	static int pcibios_map_phb_io_space(struct pci_controller *hose)
1da177e4	126	{
3d5134ee BH	127	struct vm_struct *area;
	128	unsigned long phys_page;
	129	unsigned long size_page;
	130	unsigned long io_virt_offset;
1da177e4	131
3d5134ee BH	132	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
3d5134ee BH	133	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
1da177e4	134
3d5134ee BH	135	/* Make sure IO area address is clear */
3d5134ee BH	136	hose->io_base_alloc = NULL;
1da177e4	137
3d5134ee BH	138	/* If there's no IO to map on that bus, get away too */
	139	if (hose->pci_io_size == 0 \|\| hose->io_base_phys == 0)
	140	return 0;
1da177e4	141
3d5134ee BH	142	/* Let's allocate some IO space for that guy. We don't pass
	143	* VM_IOREMAP because we don't care about alignment tricks that
	144	* the core does in that case. Maybe we should due to stupid card
	145	* with incomplete address decoding but I'd rather not deal with
	146	* those outside of the reserved 64K legacy region.
	147	*/
	148	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	149	if (area == NULL)
	150	return -ENOMEM;
	151	hose->io_base_alloc = area->addr;
	152	hose->io_base_virt = (void __iomem *)(area->addr +
	153	hose->io_base_phys - phys_page);
	154
b0494bc8	155	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
9477e455	156	pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
b0494bc8	157	hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
bcba0778	158	pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
b0494bc8	159	hose->pci_io_size, size_page);
3d5134ee BH	160
	161	/* Establish the mapping */
	162	if (__ioremap_at(phys_page, area->addr, size_page,
	163	_PAGE_NO_CACHE \| _PAGE_GUARDED) == NULL)
	164	return -ENOMEM;
	165
	166	/* Fixup hose IO resource */
38973ba7	167	io_virt_offset = pcibios_io_space_offset(hose);
3d5134ee BH	168	hose->io_resource.start += io_virt_offset;
	169	hose->io_resource.end += io_virt_offset;
	170
518fdae2	171	pr_debug(" hose->io_resource=%pR\n", &hose->io_resource);
1da177e4 LT	172
	173	return 0;
	174	}
49a6cba4	175
cad5cef6	176	int pcibios_map_io_space(struct pci_bus *bus)
49a6cba4 BH	177	{
	178	WARN_ON(bus == NULL);
	179
	180	/* If this not a PHB, nothing to do, page tables still exist and
	181	* thus HPTEs will be faulted in when needed
	182	*/
	183	if (bus->self) {
	184	pr_debug("IO mapping for PCI-PCI bridge %s\n",
	185	pci_name(bus->self));
	186	pr_debug(" virt=0x%016llx...0x%016llx\n",
	187	bus->resource[0]->start + _IO_BASE,
	188	bus->resource[0]->end + _IO_BASE);
	189	return 0;
	190	}
	191
	192	return pcibios_map_phb_io_space(pci_bus_to_host(bus));
	193	}
3d5134ee	194	EXPORT_SYMBOL_GPL(pcibios_map_io_space);
1da177e4	195
cad5cef6	196	void pcibios_setup_phb_io_space(struct pci_controller *hose)
0ed2c722	197	{
49a6cba4	198	pcibios_map_phb_io_space(hose);
0ed2c722 GL	199	}
0ed2c722 GL	200
b2ad7b5e PM	201	#define IOBASE_BRIDGE_NUMBER 0
	202	#define IOBASE_MEMORY 1
	203	#define IOBASE_IO 2
	204	#define IOBASE_ISA_IO 3
	205	#define IOBASE_ISA_MEM 4
	206
	207	long sys_pciconfig_iobase(long which, unsigned long in_bus,
	208	unsigned long in_devfn)
	209	{
	210	struct pci_controller* hose;
	211	struct list_head *ln;
	212	struct pci_bus *bus = NULL;
	213	struct device_node *hose_node;
	214
	215	/* Argh ! Please forgive me for that hack, but that's the
	216	* simplest way to get existing XFree to not lockup on some
	217	* G5 machines... So when something asks for bus 0 io base
	218	* (bus 0 is HT root), we return the AGP one instead.
	219	*/
71a157e8	220	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
16124f10 PM	221	struct device_node *agp;
	222
	223	agp = of_find_compatible_node(NULL, NULL, "u3-agp");
	224	if (agp)
b2ad7b5e	225	in_bus = 0xf0;
16124f10 PM	226	of_node_put(agp);
16124f10 PM	227	}
b2ad7b5e PM	228
	229	/* That syscall isn't quite compatible with PCI domains, but it's
	230	* used on pre-domains setup. We return the first match
	231	*/
	232
	233	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
	234	bus = pci_bus_b(ln);
b918c62e	235	if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
b2ad7b5e PM	236	break;
	237	bus = NULL;
	238	}
b5d937de	239	if (bus == NULL \|\| bus->dev.of_node == NULL)
b2ad7b5e PM	240	return -ENODEV;
b2ad7b5e PM	241
b5d937de	242	hose_node = bus->dev.of_node;
b2ad7b5e PM	243	hose = PCI_DN(hose_node)->phb;
	244
	245	switch (which) {
	246	case IOBASE_BRIDGE_NUMBER:
	247	return (long)hose->first_busno;
	248	case IOBASE_MEMORY:
	249	return (long)hose->pci_mem_offset;
	250	case IOBASE_IO:
	251	return (long)hose->io_base_phys;
	252	case IOBASE_ISA_IO:
	253	return (long)isa_io_base;
	254	case IOBASE_ISA_MEM:
	255	return -EINVAL;
	256	}
	257
	258	return -EOPNOTSUPP;
	259	}
357518fa AB	260
	261	#ifdef CONFIG_NUMA
	262	int pcibus_to_node(struct pci_bus *bus)
	263	{
	264	struct pci_controller *phb = pci_bus_to_host(bus);
	265	return phb->node;
	266	}
	267	EXPORT_SYMBOL(pcibus_to_node);
	268	#endif