Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/pci.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/list.h> | |
b2ad7b5e | 23 | #include <linux/syscalls.h> |
1da177e4 LT |
24 | |
25 | #include <asm/processor.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/byteorder.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/machdep.h> | |
d387899f | 32 | #include <asm/ppc-pci.h> |
1da177e4 LT |
33 | |
34 | #ifdef DEBUG | |
f9e4ec57 | 35 | #include <asm/udbg.h> |
1beb6a7d | 36 | #define DBG(fmt...) printk(fmt) |
1da177e4 LT |
37 | #else |
38 | #define DBG(fmt...) | |
39 | #endif | |
40 | ||
41 | unsigned long pci_probe_only = 1; | |
f8ef2705 | 42 | int pci_assign_all_buses = 0; |
1da177e4 | 43 | |
4267292b PM |
44 | #ifdef CONFIG_PPC_MULTIPLATFORM |
45 | static void fixup_resource(struct resource *res, struct pci_dev *dev); | |
46 | static void do_bus_setup(struct pci_bus *bus); | |
9623b5d3 | 47 | static void phbs_remap_io(void); |
4267292b | 48 | #endif |
1da177e4 | 49 | |
1da177e4 LT |
50 | /* pci_io_base -- the base address from which io bars are offsets. |
51 | * This is the lowest I/O base address (so bar values are always positive), | |
52 | * and it *must* be the start of ISA space if an ISA bus exists because | |
53 | * ISA drivers use hard coded offsets. If no ISA bus exists a dummy | |
54 | * page is mapped and isa_io_limit prevents access to it. | |
55 | */ | |
56 | unsigned long isa_io_base; /* NULL if no ISA bus */ | |
57 | EXPORT_SYMBOL(isa_io_base); | |
58 | unsigned long pci_io_base; | |
59 | EXPORT_SYMBOL(pci_io_base); | |
60 | ||
61 | void iSeries_pcibios_init(void); | |
62 | ||
63 | LIST_HEAD(hose_list); | |
64 | ||
65 | struct dma_mapping_ops pci_dma_ops; | |
66 | EXPORT_SYMBOL(pci_dma_ops); | |
67 | ||
68 | int global_phb_number; /* Global phb counter */ | |
69 | ||
70 | /* Cached ISA bridge dev. */ | |
71 | struct pci_dev *ppc64_isabridge_dev = NULL; | |
b239cbe9 | 72 | EXPORT_SYMBOL_GPL(ppc64_isabridge_dev); |
1da177e4 LT |
73 | |
74 | static void fixup_broken_pcnet32(struct pci_dev* dev) | |
75 | { | |
76 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
77 | dev->vendor = PCI_VENDOR_ID_AMD; | |
78 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
79 | } |
80 | } | |
81 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
82 | ||
83 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
84 | struct resource *res) | |
85 | { | |
86 | unsigned long offset = 0; | |
87 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
88 | ||
89 | if (!hose) | |
90 | return; | |
91 | ||
92 | if (res->flags & IORESOURCE_IO) | |
93 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
94 | ||
95 | if (res->flags & IORESOURCE_MEM) | |
96 | offset = hose->pci_mem_offset; | |
97 | ||
98 | region->start = res->start - offset; | |
99 | region->end = res->end - offset; | |
100 | } | |
101 | ||
43c34735 DB |
102 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
103 | struct pci_bus_region *region) | |
104 | { | |
105 | unsigned long offset = 0; | |
106 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
107 | ||
108 | if (!hose) | |
109 | return; | |
110 | ||
111 | if (res->flags & IORESOURCE_IO) | |
112 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
113 | ||
114 | if (res->flags & IORESOURCE_MEM) | |
115 | offset = hose->pci_mem_offset; | |
116 | ||
117 | res->start = region->start + offset; | |
118 | res->end = region->end + offset; | |
119 | } | |
120 | ||
1da177e4 LT |
121 | #ifdef CONFIG_HOTPLUG |
122 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 123 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
124 | #endif |
125 | ||
126 | /* | |
127 | * We need to avoid collisions with `mirrored' VGA ports | |
128 | * and other strange ISA hardware, so we always want the | |
129 | * addresses to be allocated in the 0x000-0x0ff region | |
130 | * modulo 0x400. | |
131 | * | |
132 | * Why? Because some silly external IO cards only decode | |
133 | * the low 10 bits of the IO address. The 0x00-0xff region | |
134 | * is reserved for motherboard devices that decode all 16 | |
135 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
136 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
137 | * which might have be mirrored at 0x0100-0x03ff.. | |
138 | */ | |
139 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 140 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
141 | { |
142 | struct pci_dev *dev = data; | |
143 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
e31dd6e4 | 144 | resource_size_t start = res->start; |
1da177e4 LT |
145 | unsigned long alignto; |
146 | ||
147 | if (res->flags & IORESOURCE_IO) { | |
148 | unsigned long offset = (unsigned long)hose->io_base_virt - | |
149 | pci_io_base; | |
150 | /* Make sure we start at our min on all hoses */ | |
151 | if (start - offset < PCIBIOS_MIN_IO) | |
152 | start = PCIBIOS_MIN_IO + offset; | |
153 | ||
154 | /* | |
155 | * Put everything into 0x00-0xff region modulo 0x400 | |
156 | */ | |
157 | if (start & 0x300) | |
158 | start = (start + 0x3ff) & ~0x3ff; | |
159 | ||
160 | } else if (res->flags & IORESOURCE_MEM) { | |
161 | /* Make sure we start at our min on all hoses */ | |
162 | if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) | |
163 | start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; | |
164 | ||
165 | /* Align to multiple of size of minimum base. */ | |
166 | alignto = max(0x1000UL, align); | |
167 | start = ALIGN(start, alignto); | |
168 | } | |
169 | ||
170 | res->start = start; | |
171 | } | |
172 | ||
173 | static DEFINE_SPINLOCK(hose_spinlock); | |
174 | ||
175 | /* | |
176 | * pci_controller(phb) initialized common variables. | |
177 | */ | |
b5166cc2 | 178 | static void __devinit pci_setup_pci_controller(struct pci_controller *hose) |
1da177e4 LT |
179 | { |
180 | memset(hose, 0, sizeof(struct pci_controller)); | |
181 | ||
182 | spin_lock(&hose_spinlock); | |
183 | hose->global_number = global_phb_number++; | |
184 | list_add_tail(&hose->list_node, &hose_list); | |
185 | spin_unlock(&hose_spinlock); | |
186 | } | |
187 | ||
b5166cc2 BH |
188 | static void add_linux_pci_domain(struct device_node *dev, |
189 | struct pci_controller *phb) | |
190 | { | |
191 | struct property *of_prop; | |
192 | unsigned int size; | |
193 | ||
194 | of_prop = (struct property *) | |
195 | get_property(dev, "linux,pci-domain", &size); | |
196 | if (of_prop != NULL) | |
197 | return; | |
198 | WARN_ON(of_prop && size < sizeof(int)); | |
199 | if (of_prop && size < sizeof(int)) | |
200 | of_prop = NULL; | |
201 | size = sizeof(struct property) + sizeof(int); | |
202 | if (of_prop == NULL) { | |
203 | if (mem_init_done) | |
204 | of_prop = kmalloc(size, GFP_KERNEL); | |
205 | else | |
206 | of_prop = alloc_bootmem(size); | |
207 | } | |
208 | memset(of_prop, 0, sizeof(struct property)); | |
209 | of_prop->name = "linux,pci-domain"; | |
210 | of_prop->length = sizeof(int); | |
211 | of_prop->value = (unsigned char *)&of_prop[1]; | |
212 | *((int *)of_prop->value) = phb->global_number; | |
213 | prom_add_property(dev, of_prop); | |
214 | } | |
215 | ||
216 | struct pci_controller * pcibios_alloc_controller(struct device_node *dev) | |
217 | { | |
218 | struct pci_controller *phb; | |
219 | ||
220 | if (mem_init_done) | |
221 | phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL); | |
222 | else | |
223 | phb = alloc_bootmem(sizeof (struct pci_controller)); | |
224 | if (phb == NULL) | |
225 | return NULL; | |
226 | pci_setup_pci_controller(phb); | |
227 | phb->arch_data = dev; | |
228 | phb->is_dynamic = mem_init_done; | |
357518fa AB |
229 | if (dev) { |
230 | PHB_SET_NODE(phb, of_node_to_nid(dev)); | |
b5166cc2 | 231 | add_linux_pci_domain(dev, phb); |
357518fa | 232 | } |
b5166cc2 BH |
233 | return phb; |
234 | } | |
235 | ||
236 | void pcibios_free_controller(struct pci_controller *phb) | |
237 | { | |
238 | if (phb->arch_data) { | |
239 | struct device_node *np = phb->arch_data; | |
240 | int *domain = (int *)get_property(np, | |
241 | "linux,pci-domain", NULL); | |
242 | if (domain) | |
243 | *domain = -1; | |
244 | } | |
245 | if (phb->is_dynamic) | |
246 | kfree(phb); | |
247 | } | |
248 | ||
9623b5d3 | 249 | #ifndef CONFIG_PPC_ISERIES |
facf0787 | 250 | void __devinit pcibios_claim_one_bus(struct pci_bus *b) |
1da177e4 LT |
251 | { |
252 | struct pci_dev *dev; | |
253 | struct pci_bus *child_bus; | |
254 | ||
255 | list_for_each_entry(dev, &b->devices, bus_list) { | |
256 | int i; | |
257 | ||
258 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
259 | struct resource *r = &dev->resource[i]; | |
260 | ||
261 | if (r->parent || !r->start || !r->flags) | |
262 | continue; | |
263 | pci_claim_resource(dev, i); | |
264 | } | |
265 | } | |
266 | ||
267 | list_for_each_entry(child_bus, &b->children, node) | |
268 | pcibios_claim_one_bus(child_bus); | |
269 | } | |
af9deabe LV |
270 | #ifdef CONFIG_HOTPLUG |
271 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
272 | #endif | |
1da177e4 | 273 | |
1da177e4 LT |
274 | static void __init pcibios_claim_of_setup(void) |
275 | { | |
276 | struct pci_bus *b; | |
277 | ||
278 | list_for_each_entry(b, &pci_root_buses, node) | |
279 | pcibios_claim_one_bus(b); | |
280 | } | |
281 | #endif | |
282 | ||
4267292b PM |
283 | #ifdef CONFIG_PPC_MULTIPLATFORM |
284 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) | |
285 | { | |
286 | u32 *prop; | |
287 | int len; | |
288 | ||
289 | prop = (u32 *) get_property(np, name, &len); | |
290 | if (prop && len >= 4) | |
291 | return *prop; | |
292 | return def; | |
293 | } | |
294 | ||
295 | static unsigned int pci_parse_of_flags(u32 addr0) | |
296 | { | |
297 | unsigned int flags = 0; | |
298 | ||
299 | if (addr0 & 0x02000000) { | |
d79e743e PM |
300 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
301 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
302 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
4267292b | 303 | if (addr0 & 0x40000000) |
d79e743e PM |
304 | flags |= IORESOURCE_PREFETCH |
305 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
4267292b | 306 | } else if (addr0 & 0x01000000) |
d79e743e | 307 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
4267292b PM |
308 | return flags; |
309 | } | |
310 | ||
311 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
312 | ||
313 | static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) | |
314 | { | |
315 | u64 base, size; | |
316 | unsigned int flags; | |
317 | struct resource *res; | |
318 | u32 *addrs, i; | |
319 | int proplen; | |
320 | ||
321 | addrs = (u32 *) get_property(node, "assigned-addresses", &proplen); | |
322 | if (!addrs) | |
323 | return; | |
1beb6a7d | 324 | DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs); |
4267292b PM |
325 | for (; proplen >= 20; proplen -= 20, addrs += 5) { |
326 | flags = pci_parse_of_flags(addrs[0]); | |
327 | if (!flags) | |
328 | continue; | |
329 | base = GET_64BIT(addrs, 1); | |
330 | size = GET_64BIT(addrs, 3); | |
331 | if (!size) | |
332 | continue; | |
333 | i = addrs[0] & 0xff; | |
1beb6a7d BH |
334 | DBG(" base: %llx, size: %llx, i: %x\n", |
335 | (unsigned long long)base, (unsigned long long)size, i); | |
336 | ||
4267292b PM |
337 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { |
338 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
339 | } else if (i == dev->rom_base_reg) { | |
340 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
341 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
342 | } else { | |
343 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
344 | continue; | |
345 | } | |
346 | res->start = base; | |
347 | res->end = base + size - 1; | |
348 | res->flags = flags; | |
349 | res->name = pci_name(dev); | |
350 | fixup_resource(res, dev); | |
351 | } | |
352 | } | |
353 | ||
ead83717 JR |
354 | struct pci_dev *of_create_pci_dev(struct device_node *node, |
355 | struct pci_bus *bus, int devfn) | |
4267292b PM |
356 | { |
357 | struct pci_dev *dev; | |
358 | const char *type; | |
359 | ||
360 | dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
361 | if (!dev) | |
362 | return NULL; | |
363 | type = get_property(node, "device_type", NULL); | |
364 | if (type == NULL) | |
365 | type = ""; | |
366 | ||
1beb6a7d BH |
367 | DBG(" create device, devfn: %x, type: %s\n", devfn, type); |
368 | ||
4267292b PM |
369 | memset(dev, 0, sizeof(struct pci_dev)); |
370 | dev->bus = bus; | |
371 | dev->sysdata = node; | |
372 | dev->dev.parent = bus->bridge; | |
373 | dev->dev.bus = &pci_bus_type; | |
374 | dev->devfn = devfn; | |
375 | dev->multifunction = 0; /* maybe a lie? */ | |
376 | ||
377 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); | |
378 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
379 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
380 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
381 | ||
9d17a5c6 | 382 | dev->cfg_size = pci_cfg_space_size(dev); |
4267292b PM |
383 | |
384 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
385 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
386 | dev->class = get_int_prop(node, "class-code", 0); | |
387 | ||
1beb6a7d BH |
388 | DBG(" class: 0x%x\n", dev->class); |
389 | ||
4267292b PM |
390 | dev->current_state = 4; /* unknown power state */ |
391 | ||
bb53bb3d | 392 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
4267292b PM |
393 | /* a PCI-PCI bridge */ |
394 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
395 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
396 | } else if (!strcmp(type, "cardbus")) { | |
397 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
398 | } else { | |
399 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
400 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
0ebfff14 | 401 | /* Maybe do a default OF mapping here */ |
4267292b | 402 | dev->irq = NO_IRQ; |
4267292b PM |
403 | } |
404 | ||
405 | pci_parse_of_addrs(node, dev); | |
406 | ||
1beb6a7d BH |
407 | DBG(" adding to system ...\n"); |
408 | ||
4267292b PM |
409 | pci_device_add(dev, bus); |
410 | ||
411 | /* XXX pci_scan_msi_device(dev); */ | |
412 | ||
413 | return dev; | |
414 | } | |
ead83717 | 415 | EXPORT_SYMBOL(of_create_pci_dev); |
4267292b | 416 | |
ead83717 | 417 | void __devinit of_scan_bus(struct device_node *node, |
4267292b PM |
418 | struct pci_bus *bus) |
419 | { | |
420 | struct device_node *child = NULL; | |
421 | u32 *reg; | |
422 | int reglen, devfn; | |
423 | struct pci_dev *dev; | |
424 | ||
1beb6a7d BH |
425 | DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number); |
426 | ||
4267292b | 427 | while ((child = of_get_next_child(node, child)) != NULL) { |
1beb6a7d | 428 | DBG(" * %s\n", child->full_name); |
4267292b PM |
429 | reg = (u32 *) get_property(child, "reg", ®len); |
430 | if (reg == NULL || reglen < 20) | |
431 | continue; | |
432 | devfn = (reg[0] >> 8) & 0xff; | |
1beb6a7d | 433 | |
4267292b PM |
434 | /* create a new pci_dev for this device */ |
435 | dev = of_create_pci_dev(child, bus, devfn); | |
436 | if (!dev) | |
437 | continue; | |
1beb6a7d BH |
438 | DBG("dev header type: %x\n", dev->hdr_type); |
439 | ||
4267292b PM |
440 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
441 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
442 | of_scan_pci_bridge(child, dev); | |
443 | } | |
444 | ||
445 | do_bus_setup(bus); | |
446 | } | |
ead83717 | 447 | EXPORT_SYMBOL(of_scan_bus); |
4267292b | 448 | |
ead83717 JR |
449 | void __devinit of_scan_pci_bridge(struct device_node *node, |
450 | struct pci_dev *dev) | |
4267292b PM |
451 | { |
452 | struct pci_bus *bus; | |
453 | u32 *busrange, *ranges; | |
454 | int len, i, mode; | |
455 | struct resource *res; | |
456 | unsigned int flags; | |
457 | u64 size; | |
458 | ||
1beb6a7d BH |
459 | DBG("of_scan_pci_bridge(%s)\n", node->full_name); |
460 | ||
4267292b PM |
461 | /* parse bus-range property */ |
462 | busrange = (u32 *) get_property(node, "bus-range", &len); | |
463 | if (busrange == NULL || len != 8) { | |
1beb6a7d | 464 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", |
4267292b PM |
465 | node->full_name); |
466 | return; | |
467 | } | |
468 | ranges = (u32 *) get_property(node, "ranges", &len); | |
469 | if (ranges == NULL) { | |
1beb6a7d | 470 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", |
4267292b PM |
471 | node->full_name); |
472 | return; | |
473 | } | |
474 | ||
475 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
476 | if (!bus) { | |
477 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
478 | node->full_name); | |
479 | return; | |
480 | } | |
481 | ||
482 | bus->primary = dev->bus->number; | |
483 | bus->subordinate = busrange[1]; | |
484 | bus->bridge_ctl = 0; | |
485 | bus->sysdata = node; | |
486 | ||
487 | /* parse ranges property */ | |
488 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
489 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
490 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
491 | res->flags = 0; | |
492 | bus->resource[i] = res; | |
493 | ++res; | |
494 | } | |
495 | i = 1; | |
496 | for (; len >= 32; len -= 32, ranges += 8) { | |
497 | flags = pci_parse_of_flags(ranges[0]); | |
498 | size = GET_64BIT(ranges, 6); | |
499 | if (flags == 0 || size == 0) | |
500 | continue; | |
501 | if (flags & IORESOURCE_IO) { | |
502 | res = bus->resource[0]; | |
503 | if (res->flags) { | |
504 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
505 | " for bridge %s\n", node->full_name); | |
506 | continue; | |
507 | } | |
508 | } else { | |
509 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
510 | printk(KERN_ERR "PCI: too many memory ranges" | |
511 | " for bridge %s\n", node->full_name); | |
512 | continue; | |
513 | } | |
514 | res = bus->resource[i]; | |
515 | ++i; | |
516 | } | |
517 | res->start = GET_64BIT(ranges, 1); | |
518 | res->end = res->start + size - 1; | |
519 | res->flags = flags; | |
520 | fixup_resource(res, dev); | |
521 | } | |
522 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
523 | bus->number); | |
1beb6a7d | 524 | DBG(" bus name: %s\n", bus->name); |
4267292b PM |
525 | |
526 | mode = PCI_PROBE_NORMAL; | |
527 | if (ppc_md.pci_probe_mode) | |
528 | mode = ppc_md.pci_probe_mode(bus); | |
1beb6a7d BH |
529 | DBG(" probe mode: %d\n", mode); |
530 | ||
4267292b PM |
531 | if (mode == PCI_PROBE_DEVTREE) |
532 | of_scan_bus(node, bus); | |
533 | else if (mode == PCI_PROBE_NORMAL) | |
534 | pci_scan_child_bus(bus); | |
535 | } | |
ead83717 | 536 | EXPORT_SYMBOL(of_scan_pci_bridge); |
4267292b PM |
537 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
538 | ||
ead83717 | 539 | void __devinit scan_phb(struct pci_controller *hose) |
4267292b PM |
540 | { |
541 | struct pci_bus *bus; | |
542 | struct device_node *node = hose->arch_data; | |
543 | int i, mode; | |
544 | struct resource *res; | |
545 | ||
1beb6a7d BH |
546 | DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>"); |
547 | ||
4267292b PM |
548 | bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node); |
549 | if (bus == NULL) { | |
550 | printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", | |
551 | hose->global_number); | |
552 | return; | |
553 | } | |
554 | bus->secondary = hose->first_busno; | |
555 | hose->bus = bus; | |
556 | ||
557 | bus->resource[0] = res = &hose->io_resource; | |
558 | if (res->flags && request_resource(&ioport_resource, res)) | |
559 | printk(KERN_ERR "Failed to request PCI IO region " | |
560 | "on PCI domain %04x\n", hose->global_number); | |
561 | ||
562 | for (i = 0; i < 3; ++i) { | |
563 | res = &hose->mem_resources[i]; | |
564 | bus->resource[i+1] = res; | |
565 | if (res->flags && request_resource(&iomem_resource, res)) | |
566 | printk(KERN_ERR "Failed to request PCI memory region " | |
567 | "on PCI domain %04x\n", hose->global_number); | |
568 | } | |
569 | ||
570 | mode = PCI_PROBE_NORMAL; | |
571 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1beb6a7d | 572 | if (node && ppc_md.pci_probe_mode) |
4267292b | 573 | mode = ppc_md.pci_probe_mode(bus); |
1beb6a7d | 574 | DBG(" probe mode: %d\n", mode); |
4267292b PM |
575 | if (mode == PCI_PROBE_DEVTREE) { |
576 | bus->subordinate = hose->last_busno; | |
577 | of_scan_bus(node, bus); | |
578 | } | |
579 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
580 | if (mode == PCI_PROBE_NORMAL) | |
581 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
4267292b PM |
582 | } |
583 | ||
1da177e4 LT |
584 | static int __init pcibios_init(void) |
585 | { | |
586 | struct pci_controller *hose, *tmp; | |
1da177e4 LT |
587 | |
588 | /* For now, override phys_mem_access_prot. If we need it, | |
589 | * later, we may move that initialization to each ppc_md | |
590 | */ | |
591 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
592 | ||
593 | #ifdef CONFIG_PPC_ISERIES | |
594 | iSeries_pcibios_init(); | |
595 | #endif | |
596 | ||
e884e9c5 | 597 | printk(KERN_DEBUG "PCI: Probing PCI hardware\n"); |
1da177e4 LT |
598 | |
599 | /* Scan all of the recorded PCI controllers. */ | |
92eb4602 | 600 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
4267292b | 601 | scan_phb(hose); |
92eb4602 JR |
602 | pci_bus_add_devices(hose->bus); |
603 | } | |
1da177e4 LT |
604 | |
605 | #ifndef CONFIG_PPC_ISERIES | |
606 | if (pci_probe_only) | |
607 | pcibios_claim_of_setup(); | |
608 | else | |
609 | /* FIXME: `else' will be removed when | |
610 | pci_assign_unassigned_resources() is able to work | |
611 | correctly with [partially] allocated PCI tree. */ | |
612 | pci_assign_unassigned_resources(); | |
613 | #endif /* !CONFIG_PPC_ISERIES */ | |
614 | ||
615 | /* Call machine dependent final fixup */ | |
616 | if (ppc_md.pcibios_fixup) | |
617 | ppc_md.pcibios_fixup(); | |
618 | ||
619 | /* Cache the location of the ISA bridge (if we have one) */ | |
620 | ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
621 | if (ppc64_isabridge_dev != NULL) | |
e884e9c5 | 622 | printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev)); |
1da177e4 | 623 | |
fe360cdf | 624 | #ifdef CONFIG_PPC_MULTIPLATFORM |
0f34f490 BH |
625 | /* map in PCI I/O space */ |
626 | phbs_remap_io(); | |
fe360cdf | 627 | #endif |
0f34f490 | 628 | |
e884e9c5 | 629 | printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); |
1da177e4 LT |
630 | |
631 | return 0; | |
632 | } | |
633 | ||
634 | subsys_initcall(pcibios_init); | |
635 | ||
636 | char __init *pcibios_setup(char *str) | |
637 | { | |
638 | return str; | |
639 | } | |
640 | ||
641 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
642 | { | |
643 | u16 cmd, oldcmd; | |
644 | int i; | |
645 | ||
646 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
647 | oldcmd = cmd; | |
648 | ||
649 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
650 | struct resource *res = &dev->resource[i]; | |
651 | ||
652 | /* Only set up the requested stuff */ | |
653 | if (!(mask & (1<<i))) | |
654 | continue; | |
655 | ||
656 | if (res->flags & IORESOURCE_IO) | |
657 | cmd |= PCI_COMMAND_IO; | |
658 | if (res->flags & IORESOURCE_MEM) | |
659 | cmd |= PCI_COMMAND_MEMORY; | |
660 | } | |
661 | ||
662 | if (cmd != oldcmd) { | |
663 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
664 | pci_name(dev), cmd); | |
665 | /* Enable the appropriate bits in the PCI command register. */ | |
666 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
667 | } | |
668 | return 0; | |
669 | } | |
670 | ||
671 | /* | |
672 | * Return the domain number for this bus. | |
673 | */ | |
674 | int pci_domain_nr(struct pci_bus *bus) | |
675 | { | |
676 | #ifdef CONFIG_PPC_ISERIES | |
677 | return 0; | |
678 | #else | |
679 | struct pci_controller *hose = pci_bus_to_host(bus); | |
680 | ||
681 | return hose->global_number; | |
682 | #endif | |
683 | } | |
684 | ||
685 | EXPORT_SYMBOL(pci_domain_nr); | |
686 | ||
687 | /* Decide whether to display the domain number in /proc */ | |
688 | int pci_proc_domain(struct pci_bus *bus) | |
689 | { | |
690 | #ifdef CONFIG_PPC_ISERIES | |
691 | return 0; | |
692 | #else | |
693 | struct pci_controller *hose = pci_bus_to_host(bus); | |
694 | return hose->buid; | |
695 | #endif | |
696 | } | |
697 | ||
698 | /* | |
699 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
700 | * modelled on the sparc64 implementation by Dave Miller. | |
701 | * -- paulus. | |
702 | */ | |
703 | ||
704 | /* | |
705 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
706 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
707 | * | |
708 | * Basically, the user finds the base address for his device which he wishes | |
709 | * to mmap. They read the 32-bit value from the config space base register, | |
710 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
711 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
712 | * | |
713 | * Returns negative error code on failure, zero on success. | |
714 | */ | |
715 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
716 | unsigned long *offset, | |
717 | enum pci_mmap_state mmap_state) | |
718 | { | |
719 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
720 | unsigned long io_offset = 0; | |
721 | int i, res_bit; | |
722 | ||
723 | if (hose == 0) | |
724 | return NULL; /* should never happen */ | |
725 | ||
726 | /* If memory, add on the PCI bridge address offset */ | |
727 | if (mmap_state == pci_mmap_mem) { | |
728 | *offset += hose->pci_mem_offset; | |
729 | res_bit = IORESOURCE_MEM; | |
730 | } else { | |
2311b1f2 | 731 | io_offset = (unsigned long)hose->io_base_virt - pci_io_base; |
1da177e4 LT |
732 | *offset += io_offset; |
733 | res_bit = IORESOURCE_IO; | |
734 | } | |
735 | ||
736 | /* | |
737 | * Check that the offset requested corresponds to one of the | |
738 | * resources of the device. | |
739 | */ | |
740 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
741 | struct resource *rp = &dev->resource[i]; | |
742 | int flags = rp->flags; | |
743 | ||
744 | /* treat ROM as memory (should be already) */ | |
745 | if (i == PCI_ROM_RESOURCE) | |
746 | flags |= IORESOURCE_MEM; | |
747 | ||
748 | /* Active and same type? */ | |
749 | if ((flags & res_bit) == 0) | |
750 | continue; | |
751 | ||
752 | /* In the range of this resource? */ | |
753 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
754 | continue; | |
755 | ||
756 | /* found it! construct the final physical address */ | |
757 | if (mmap_state == pci_mmap_io) | |
2311b1f2 | 758 | *offset += hose->io_base_phys - io_offset; |
1da177e4 LT |
759 | return rp; |
760 | } | |
761 | ||
762 | return NULL; | |
763 | } | |
764 | ||
765 | /* | |
766 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
767 | * device mapping. | |
768 | */ | |
769 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
770 | pgprot_t protection, | |
771 | enum pci_mmap_state mmap_state, | |
772 | int write_combine) | |
773 | { | |
774 | unsigned long prot = pgprot_val(protection); | |
775 | ||
776 | /* Write combine is always 0 on non-memory space mappings. On | |
777 | * memory space, if the user didn't pass 1, we check for a | |
778 | * "prefetchable" resource. This is a bit hackish, but we use | |
779 | * this to workaround the inability of /sysfs to provide a write | |
780 | * combine bit | |
781 | */ | |
782 | if (mmap_state != pci_mmap_mem) | |
783 | write_combine = 0; | |
784 | else if (write_combine == 0) { | |
785 | if (rp->flags & IORESOURCE_PREFETCH) | |
786 | write_combine = 1; | |
787 | } | |
788 | ||
789 | /* XXX would be nice to have a way to ask for write-through */ | |
790 | prot |= _PAGE_NO_CACHE; | |
791 | if (write_combine) | |
792 | prot &= ~_PAGE_GUARDED; | |
793 | else | |
794 | prot |= _PAGE_GUARDED; | |
795 | ||
e884e9c5 | 796 | printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, |
1da177e4 LT |
797 | prot); |
798 | ||
799 | return __pgprot(prot); | |
800 | } | |
801 | ||
802 | /* | |
803 | * This one is used by /dev/mem and fbdev who have no clue about the | |
804 | * PCI device, it tries to find the PCI device first and calls the | |
805 | * above routine | |
806 | */ | |
807 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 808 | unsigned long pfn, |
1da177e4 LT |
809 | unsigned long size, |
810 | pgprot_t protection) | |
811 | { | |
812 | struct pci_dev *pdev = NULL; | |
813 | struct resource *found = NULL; | |
814 | unsigned long prot = pgprot_val(protection); | |
8b150478 | 815 | unsigned long offset = pfn << PAGE_SHIFT; |
1da177e4 LT |
816 | int i; |
817 | ||
8b150478 | 818 | if (page_is_ram(pfn)) |
1f8d419e | 819 | return __pgprot(prot); |
1da177e4 LT |
820 | |
821 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
822 | ||
823 | for_each_pci_dev(pdev) { | |
824 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
825 | struct resource *rp = &pdev->resource[i]; | |
826 | int flags = rp->flags; | |
827 | ||
828 | /* Active and same type? */ | |
829 | if ((flags & IORESOURCE_MEM) == 0) | |
830 | continue; | |
831 | /* In the range of this resource? */ | |
832 | if (offset < (rp->start & PAGE_MASK) || | |
833 | offset > rp->end) | |
834 | continue; | |
835 | found = rp; | |
836 | break; | |
837 | } | |
838 | if (found) | |
839 | break; | |
840 | } | |
841 | if (found) { | |
842 | if (found->flags & IORESOURCE_PREFETCH) | |
843 | prot &= ~_PAGE_GUARDED; | |
844 | pci_dev_put(pdev); | |
845 | } | |
846 | ||
847 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); | |
848 | ||
849 | return __pgprot(prot); | |
850 | } | |
851 | ||
852 | ||
853 | /* | |
854 | * Perform the actual remap of the pages for a PCI device mapping, as | |
855 | * appropriate for this architecture. The region in the process to map | |
856 | * is described by vm_start and vm_end members of VMA, the base physical | |
857 | * address is found in vm_pgoff. | |
858 | * The pci device structure is provided so that architectures may make mapping | |
859 | * decisions on a per-device or per-bus basis. | |
860 | * | |
861 | * Returns a negative error code on failure, zero on success. | |
862 | */ | |
863 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1beb6a7d | 864 | enum pci_mmap_state mmap_state, int write_combine) |
1da177e4 LT |
865 | { |
866 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | |
867 | struct resource *rp; | |
868 | int ret; | |
869 | ||
870 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
871 | if (rp == NULL) | |
872 | return -EINVAL; | |
873 | ||
874 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
1da177e4 LT |
875 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, |
876 | vma->vm_page_prot, | |
877 | mmap_state, write_combine); | |
878 | ||
879 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
880 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
881 | ||
882 | return ret; | |
883 | } | |
884 | ||
efbd3869 SR |
885 | static ssize_t pci_show_devspec(struct device *dev, |
886 | struct device_attribute *attr, char *buf) | |
1da177e4 LT |
887 | { |
888 | struct pci_dev *pdev; | |
889 | struct device_node *np; | |
890 | ||
891 | pdev = to_pci_dev (dev); | |
892 | np = pci_device_to_OF_node(pdev); | |
893 | if (np == NULL || np->full_name == NULL) | |
894 | return 0; | |
895 | return sprintf(buf, "%s", np->full_name); | |
896 | } | |
897 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
1da177e4 LT |
898 | |
899 | void pcibios_add_platform_entries(struct pci_dev *pdev) | |
900 | { | |
1da177e4 | 901 | device_create_file(&pdev->dev, &dev_attr_devspec); |
1da177e4 LT |
902 | } |
903 | ||
904 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
905 | ||
906 | #define ISA_SPACE_MASK 0x1 | |
907 | #define ISA_SPACE_IO 0x1 | |
908 | ||
909 | static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node, | |
910 | unsigned long phb_io_base_phys, | |
911 | void __iomem * phb_io_base_virt) | |
912 | { | |
cc5d0189 BH |
913 | /* Remove these asap */ |
914 | ||
915 | struct pci_address { | |
916 | u32 a_hi; | |
917 | u32 a_mid; | |
918 | u32 a_lo; | |
919 | }; | |
920 | ||
921 | struct isa_address { | |
922 | u32 a_hi; | |
923 | u32 a_lo; | |
924 | }; | |
925 | ||
926 | struct isa_range { | |
927 | struct isa_address isa_addr; | |
928 | struct pci_address pci_addr; | |
929 | unsigned int size; | |
930 | }; | |
931 | ||
1da177e4 LT |
932 | struct isa_range *range; |
933 | unsigned long pci_addr; | |
934 | unsigned int isa_addr; | |
935 | unsigned int size; | |
936 | int rlen = 0; | |
937 | ||
938 | range = (struct isa_range *) get_property(isa_node, "ranges", &rlen); | |
939 | if (range == NULL || (rlen < sizeof(struct isa_range))) { | |
940 | printk(KERN_ERR "no ISA ranges or unexpected isa range size," | |
941 | "mapping 64k\n"); | |
dfbacdc1 BH |
942 | __ioremap_explicit(phb_io_base_phys, |
943 | (unsigned long)phb_io_base_virt, | |
944 | 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED); | |
1da177e4 LT |
945 | return; |
946 | } | |
947 | ||
948 | /* From "ISA Binding to 1275" | |
949 | * The ranges property is laid out as an array of elements, | |
950 | * each of which comprises: | |
951 | * cells 0 - 1: an ISA address | |
952 | * cells 2 - 4: a PCI address | |
953 | * (size depending on dev->n_addr_cells) | |
954 | * cell 5: the size of the range | |
955 | */ | |
956 | if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) { | |
957 | isa_addr = range->isa_addr.a_lo; | |
958 | pci_addr = (unsigned long) range->pci_addr.a_mid << 32 | | |
959 | range->pci_addr.a_lo; | |
960 | ||
961 | /* Assume these are both zero */ | |
962 | if ((pci_addr != 0) || (isa_addr != 0)) { | |
963 | printk(KERN_ERR "unexpected isa to pci mapping: %s\n", | |
964 | __FUNCTION__); | |
965 | return; | |
966 | } | |
967 | ||
968 | size = PAGE_ALIGN(range->size); | |
969 | ||
970 | __ioremap_explicit(phb_io_base_phys, | |
971 | (unsigned long) phb_io_base_virt, | |
dfbacdc1 | 972 | size, _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
973 | } |
974 | } | |
975 | ||
976 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
f7abbc19 | 977 | struct device_node *dev, int prim) |
1da177e4 | 978 | { |
f7abbc19 | 979 | unsigned int *ranges, pci_space; |
1da177e4 LT |
980 | unsigned long size; |
981 | int rlen = 0; | |
982 | int memno = 0; | |
983 | struct resource *res; | |
984 | int np, na = prom_n_addr_cells(dev); | |
985 | unsigned long pci_addr, cpu_phys_addr; | |
986 | ||
987 | np = na + 5; | |
988 | ||
989 | /* From "PCI Binding to 1275" | |
990 | * The ranges property is laid out as an array of elements, | |
991 | * each of which comprises: | |
992 | * cells 0 - 2: a PCI address | |
993 | * cells 3 or 3+4: a CPU physical address | |
994 | * (size depending on dev->n_addr_cells) | |
995 | * cells 4+5 or 5+6: the size of the range | |
996 | */ | |
1da177e4 | 997 | ranges = (unsigned int *) get_property(dev, "ranges", &rlen); |
b5166cc2 BH |
998 | if (ranges == NULL) |
999 | return; | |
1000 | hose->io_base_phys = 0; | |
1da177e4 LT |
1001 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { |
1002 | res = NULL; | |
f7abbc19 PM |
1003 | pci_space = ranges[0]; |
1004 | pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
1da177e4 LT |
1005 | |
1006 | cpu_phys_addr = ranges[3]; | |
f7abbc19 PM |
1007 | if (na >= 2) |
1008 | cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4]; | |
1da177e4 | 1009 | |
f7abbc19 PM |
1010 | size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4]; |
1011 | ranges += np; | |
1da177e4 LT |
1012 | if (size == 0) |
1013 | continue; | |
f7abbc19 PM |
1014 | |
1015 | /* Now consume following elements while they are contiguous */ | |
1016 | while (rlen >= np * sizeof(unsigned int)) { | |
1017 | unsigned long addr, phys; | |
1018 | ||
1019 | if (ranges[0] != pci_space) | |
1020 | break; | |
1021 | addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
1022 | phys = ranges[3]; | |
1023 | if (na >= 2) | |
1024 | phys = (phys << 32) | ranges[4]; | |
1025 | if (addr != pci_addr + size || | |
1026 | phys != cpu_phys_addr + size) | |
1027 | break; | |
1028 | ||
1029 | size += ((unsigned long)ranges[na+3] << 32) | |
1030 | | ranges[na+4]; | |
1031 | ranges += np; | |
1032 | rlen -= np * sizeof(unsigned int); | |
1033 | } | |
1034 | ||
1035 | switch ((pci_space >> 24) & 0x3) { | |
1da177e4 LT |
1036 | case 1: /* I/O space */ |
1037 | hose->io_base_phys = cpu_phys_addr; | |
1038 | hose->pci_io_size = size; | |
1039 | ||
1040 | res = &hose->io_resource; | |
1041 | res->flags = IORESOURCE_IO; | |
1042 | res->start = pci_addr; | |
1043 | DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number, | |
1044 | res->start, res->start + size - 1); | |
1045 | break; | |
1046 | case 2: /* memory space */ | |
1047 | memno = 0; | |
1048 | while (memno < 3 && hose->mem_resources[memno].flags) | |
1049 | ++memno; | |
1050 | ||
1051 | if (memno == 0) | |
1052 | hose->pci_mem_offset = cpu_phys_addr - pci_addr; | |
1053 | if (memno < 3) { | |
1054 | res = &hose->mem_resources[memno]; | |
1055 | res->flags = IORESOURCE_MEM; | |
1056 | res->start = cpu_phys_addr; | |
1057 | DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number, | |
1058 | res->start, res->start + size - 1); | |
1059 | } | |
1060 | break; | |
1061 | } | |
1062 | if (res != NULL) { | |
1063 | res->name = dev->full_name; | |
1064 | res->end = res->start + size - 1; | |
1065 | res->parent = NULL; | |
1066 | res->sibling = NULL; | |
1067 | res->child = NULL; | |
1068 | } | |
1da177e4 LT |
1069 | } |
1070 | } | |
1071 | ||
1072 | void __init pci_setup_phb_io(struct pci_controller *hose, int primary) | |
1073 | { | |
1074 | unsigned long size = hose->pci_io_size; | |
1075 | unsigned long io_virt_offset; | |
1076 | struct resource *res; | |
1077 | struct device_node *isa_dn; | |
1078 | ||
1079 | hose->io_base_virt = reserve_phb_iospace(size); | |
1080 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", | |
1081 | hose->global_number, hose->io_base_phys, | |
1082 | (unsigned long) hose->io_base_virt); | |
1083 | ||
1084 | if (primary) { | |
1085 | pci_io_base = (unsigned long)hose->io_base_virt; | |
1086 | isa_dn = of_find_node_by_type(NULL, "isa"); | |
1087 | if (isa_dn) { | |
1088 | isa_io_base = pci_io_base; | |
1089 | pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys, | |
1090 | hose->io_base_virt); | |
1091 | of_node_put(isa_dn); | |
1da177e4 LT |
1092 | } |
1093 | } | |
1094 | ||
1095 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1096 | res = &hose->io_resource; | |
1097 | res->start += io_virt_offset; | |
1098 | res->end += io_virt_offset; | |
1099 | } | |
1100 | ||
1101 | void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose, | |
1102 | int primary) | |
1103 | { | |
1104 | unsigned long size = hose->pci_io_size; | |
1105 | unsigned long io_virt_offset; | |
1106 | struct resource *res; | |
1107 | ||
1108 | hose->io_base_virt = __ioremap(hose->io_base_phys, size, | |
dfbacdc1 | 1109 | _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
1110 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", |
1111 | hose->global_number, hose->io_base_phys, | |
1112 | (unsigned long) hose->io_base_virt); | |
1113 | ||
1114 | if (primary) | |
1115 | pci_io_base = (unsigned long)hose->io_base_virt; | |
1116 | ||
1117 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1118 | res = &hose->io_resource; | |
1119 | res->start += io_virt_offset; | |
1120 | res->end += io_virt_offset; | |
1121 | } | |
1122 | ||
1123 | ||
1124 | static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys, | |
1125 | unsigned long *start_virt, unsigned long *size) | |
1126 | { | |
1127 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1128 | struct pci_bus_region region; | |
1129 | struct resource *res; | |
1130 | ||
1131 | if (bus->self) { | |
1132 | res = bus->resource[0]; | |
1133 | pcibios_resource_to_bus(bus->self, ®ion, res); | |
1134 | *start_phys = hose->io_base_phys + region.start; | |
1135 | *start_virt = (unsigned long) hose->io_base_virt + | |
1136 | region.start; | |
1137 | if (region.end > region.start) | |
1138 | *size = region.end - region.start + 1; | |
1139 | else { | |
1140 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1141 | __FUNCTION__, region.start, region.end); | |
1142 | return 1; | |
1143 | } | |
1144 | ||
1145 | } else { | |
1146 | /* Root Bus */ | |
1147 | res = &hose->io_resource; | |
1148 | *start_phys = hose->io_base_phys; | |
1149 | *start_virt = (unsigned long) hose->io_base_virt; | |
1150 | if (res->end > res->start) | |
1151 | *size = res->end - res->start + 1; | |
1152 | else { | |
1153 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1154 | __FUNCTION__, res->start, res->end); | |
1155 | return 1; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | int unmap_bus_range(struct pci_bus *bus) | |
1163 | { | |
1164 | unsigned long start_phys; | |
1165 | unsigned long start_virt; | |
1166 | unsigned long size; | |
1167 | ||
1168 | if (!bus) { | |
1169 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1170 | return 1; | |
1171 | } | |
1172 | ||
1173 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1174 | return 1; | |
1175 | if (iounmap_explicit((void __iomem *) start_virt, size)) | |
1176 | return 1; | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | EXPORT_SYMBOL(unmap_bus_range); | |
1181 | ||
1182 | int remap_bus_range(struct pci_bus *bus) | |
1183 | { | |
1184 | unsigned long start_phys; | |
1185 | unsigned long start_virt; | |
1186 | unsigned long size; | |
1187 | ||
1188 | if (!bus) { | |
1189 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1190 | return 1; | |
1191 | } | |
1192 | ||
1193 | ||
1194 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1195 | return 1; | |
b5166cc2 BH |
1196 | if (start_phys == 0) |
1197 | return 1; | |
e884e9c5 | 1198 | printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size); |
dfbacdc1 BH |
1199 | if (__ioremap_explicit(start_phys, start_virt, size, |
1200 | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
1da177e4 LT |
1201 | return 1; |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | EXPORT_SYMBOL(remap_bus_range); | |
1206 | ||
9623b5d3 | 1207 | static void phbs_remap_io(void) |
1da177e4 LT |
1208 | { |
1209 | struct pci_controller *hose, *tmp; | |
1210 | ||
1211 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1212 | remap_bus_range(hose->bus); | |
1213 | } | |
1214 | ||
4267292b PM |
1215 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) |
1216 | { | |
1217 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
c256f4b9 | 1218 | unsigned long offset; |
1da177e4 | 1219 | |
4267292b PM |
1220 | if (res->flags & IORESOURCE_IO) { |
1221 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1da177e4 | 1222 | |
c256f4b9 AB |
1223 | res->start += offset; |
1224 | res->end += offset; | |
4267292b PM |
1225 | } else if (res->flags & IORESOURCE_MEM) { |
1226 | res->start += hose->pci_mem_offset; | |
1227 | res->end += hose->pci_mem_offset; | |
1228 | } | |
1229 | } | |
1da177e4 LT |
1230 | |
1231 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, | |
4267292b | 1232 | struct pci_bus *bus) |
1da177e4 LT |
1233 | { |
1234 | /* Update device resources. */ | |
1da177e4 LT |
1235 | int i; |
1236 | ||
4267292b PM |
1237 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
1238 | if (dev->resource[i].flags) | |
1239 | fixup_resource(&dev->resource[i], dev); | |
1da177e4 LT |
1240 | } |
1241 | EXPORT_SYMBOL(pcibios_fixup_device_resources); | |
1242 | ||
463ce0e1 | 1243 | |
4267292b | 1244 | static void __devinit do_bus_setup(struct pci_bus *bus) |
1da177e4 | 1245 | { |
4267292b | 1246 | struct pci_dev *dev; |
1da177e4 | 1247 | |
4267292b | 1248 | ppc_md.iommu_bus_setup(bus); |
1da177e4 | 1249 | |
4267292b PM |
1250 | list_for_each_entry(dev, &bus->devices, bus_list) |
1251 | ppc_md.iommu_dev_setup(dev); | |
1da177e4 | 1252 | |
4267292b PM |
1253 | if (ppc_md.irq_bus_setup) |
1254 | ppc_md.irq_bus_setup(bus); | |
1255 | } | |
1da177e4 | 1256 | |
4267292b PM |
1257 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1258 | { | |
1259 | struct pci_dev *dev = bus->self; | |
1260 | ||
1261 | if (dev && pci_probe_only && | |
1262 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1da177e4 LT |
1263 | /* This is a subordinate bridge */ |
1264 | ||
1265 | pci_read_bridge_bases(bus); | |
1266 | pcibios_fixup_device_resources(dev, bus); | |
1267 | } | |
1268 | ||
4267292b | 1269 | do_bus_setup(bus); |
dad32bbf | 1270 | |
1da177e4 LT |
1271 | if (!pci_probe_only) |
1272 | return; | |
1273 | ||
4267292b | 1274 | list_for_each_entry(dev, &bus->devices, bus_list) |
1da177e4 LT |
1275 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
1276 | pcibios_fixup_device_resources(dev, bus); | |
1da177e4 LT |
1277 | } |
1278 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
1279 | ||
1280 | /* | |
1281 | * Reads the interrupt pin to determine if interrupt is use by card. | |
1282 | * If the interrupt is used, then gets the interrupt line from the | |
1283 | * openfirmware and sets it in the pci_dev and pci_config line. | |
1284 | */ | |
1285 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
1286 | { | |
0ebfff14 BH |
1287 | struct of_irq oirq; |
1288 | unsigned int virq; | |
1da177e4 | 1289 | |
0ebfff14 | 1290 | DBG("Try to map irq for %s...\n", pci_name(pci_dev)); |
1da177e4 | 1291 | |
0ebfff14 BH |
1292 | if (of_irq_map_pci(pci_dev, &oirq)) { |
1293 | DBG(" -> failed !\n"); | |
1da177e4 | 1294 | return -1; |
0ebfff14 | 1295 | } |
1da177e4 | 1296 | |
0ebfff14 BH |
1297 | DBG(" -> got one, spec %d cells (0x%08x...) on %s\n", |
1298 | oirq.size, oirq.specifier[0], oirq.controller->full_name); | |
1da177e4 | 1299 | |
0ebfff14 BH |
1300 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, oirq.size); |
1301 | if(virq == NO_IRQ) { | |
1302 | DBG(" -> failed to map !\n"); | |
1303 | return -1; | |
1304 | } | |
1305 | pci_dev->irq = virq; | |
1306 | pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq); | |
1da177e4 LT |
1307 | |
1308 | return 0; | |
1309 | } | |
1310 | EXPORT_SYMBOL(pci_read_irq_line); | |
1311 | ||
2311b1f2 ME |
1312 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1313 | const struct resource *rsrc, | |
1314 | u64 *start, u64 *end) | |
1315 | { | |
1316 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1317 | unsigned long offset = 0; | |
1318 | ||
1319 | if (hose == NULL) | |
1320 | return; | |
1321 | ||
1322 | if (rsrc->flags & IORESOURCE_IO) | |
1323 | offset = pci_io_base - (unsigned long)hose->io_base_virt + | |
1324 | hose->io_base_phys; | |
1325 | ||
1326 | *start = rsrc->start + offset; | |
1327 | *end = rsrc->end + offset; | |
1328 | } | |
1329 | ||
463ce0e1 BH |
1330 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) |
1331 | { | |
1332 | if (!have_of) | |
1333 | return NULL; | |
1334 | while(node) { | |
1335 | struct pci_controller *hose, *tmp; | |
1336 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1337 | if (hose->arch_data == node) | |
1338 | return hose; | |
1339 | node = node->parent; | |
1340 | } | |
1341 | return NULL; | |
1342 | } | |
1343 | ||
1da177e4 | 1344 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
b2ad7b5e | 1345 | |
f2c4583a | 1346 | unsigned long pci_address_to_pio(phys_addr_t address) |
d4e4b352 SR |
1347 | { |
1348 | struct pci_controller *hose, *tmp; | |
1349 | ||
1350 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1351 | if (address >= hose->io_base_phys && | |
f2c4583a BH |
1352 | address < (hose->io_base_phys + hose->pci_io_size)) { |
1353 | unsigned long base = | |
1354 | (unsigned long)hose->io_base_virt - pci_io_base; | |
1355 | return base + (address - hose->io_base_phys); | |
1356 | } | |
d4e4b352 SR |
1357 | } |
1358 | return (unsigned int)-1; | |
1359 | } | |
1360 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
1361 | ||
b2ad7b5e PM |
1362 | |
1363 | #define IOBASE_BRIDGE_NUMBER 0 | |
1364 | #define IOBASE_MEMORY 1 | |
1365 | #define IOBASE_IO 2 | |
1366 | #define IOBASE_ISA_IO 3 | |
1367 | #define IOBASE_ISA_MEM 4 | |
1368 | ||
1369 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
1370 | unsigned long in_devfn) | |
1371 | { | |
1372 | struct pci_controller* hose; | |
1373 | struct list_head *ln; | |
1374 | struct pci_bus *bus = NULL; | |
1375 | struct device_node *hose_node; | |
1376 | ||
1377 | /* Argh ! Please forgive me for that hack, but that's the | |
1378 | * simplest way to get existing XFree to not lockup on some | |
1379 | * G5 machines... So when something asks for bus 0 io base | |
1380 | * (bus 0 is HT root), we return the AGP one instead. | |
1381 | */ | |
799d6046 | 1382 | if (machine_is_compatible("MacRISC4")) |
b2ad7b5e PM |
1383 | if (in_bus == 0) |
1384 | in_bus = 0xf0; | |
b2ad7b5e PM |
1385 | |
1386 | /* That syscall isn't quite compatible with PCI domains, but it's | |
1387 | * used on pre-domains setup. We return the first match | |
1388 | */ | |
1389 | ||
1390 | for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { | |
1391 | bus = pci_bus_b(ln); | |
1392 | if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate)) | |
1393 | break; | |
1394 | bus = NULL; | |
1395 | } | |
1396 | if (bus == NULL || bus->sysdata == NULL) | |
1397 | return -ENODEV; | |
1398 | ||
1399 | hose_node = (struct device_node *)bus->sysdata; | |
1400 | hose = PCI_DN(hose_node)->phb; | |
1401 | ||
1402 | switch (which) { | |
1403 | case IOBASE_BRIDGE_NUMBER: | |
1404 | return (long)hose->first_busno; | |
1405 | case IOBASE_MEMORY: | |
1406 | return (long)hose->pci_mem_offset; | |
1407 | case IOBASE_IO: | |
1408 | return (long)hose->io_base_phys; | |
1409 | case IOBASE_ISA_IO: | |
1410 | return (long)isa_io_base; | |
1411 | case IOBASE_ISA_MEM: | |
1412 | return -EINVAL; | |
1413 | } | |
1414 | ||
1415 | return -EOPNOTSUPP; | |
1416 | } | |
357518fa AB |
1417 | |
1418 | #ifdef CONFIG_NUMA | |
1419 | int pcibus_to_node(struct pci_bus *bus) | |
1420 | { | |
1421 | struct pci_controller *phb = pci_bus_to_host(bus); | |
1422 | return phb->node; | |
1423 | } | |
1424 | EXPORT_SYMBOL(pcibus_to_node); | |
1425 | #endif |