[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / pci_64.c

/*
 * Port for PPC64 David Engebretsen, IBM Corp.
 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
 * 
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/list.h>
#include <linux/syscalls.h>
#include <linux/irq.h>
#include <linux/vmalloc.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/ppc-pci.h>

unsigned long pci_probe_only = 1;

/* pci_io_base -- the base address from which io bars are offsets.
 * This is the lowest I/O base address (so bar values are always positive),
 * and it *must* be the start of ISA space if an ISA bus exists because
 * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
 * is mapped on the first 64K of IO space
 */
unsigned long pci_io_base = ISA_IO_BASE;
EXPORT_SYMBOL(pci_io_base);

static int __init pcibios_init(void)
{
	struct pci_controller *hose, *tmp;

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

	/* For now, override phys_mem_access_prot. If we need it,g
	 * later, we may move that initialization to each ppc_md
	 */
	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	if (pci_probe_only)
		ppc_pci_flags |= PPC_PCI_PROBE_ONLY;

	/* On ppc64, we always enable PCI domains and we keep domain 0
	 * backward compatible in /proc for video cards
	 */
	ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		pcibios_scan_phb(hose, hose->dn);
		pci_bus_add_devices(hose->bus);
	}

	/* Call common code to handle resource allocation */
	pcibios_resource_survey();

	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");

	return 0;
}

subsys_initcall(pcibios_init);

#ifdef CONFIG_HOTPLUG

int pcibios_unmap_io_space(struct pci_bus *bus)
{
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this is not a PHB, we only flush the hash table over
	 * the area mapped by this bridge. We don't play with the PTE
	 * mappings since we might have to deal with sub-page alignemnts
	 * so flushing the hash table is the only sane way to make sure
	 * that no hash entries are covering that removed bridge area
	 * while still allowing other busses overlapping those pages
	 *
	 * Note: If we ever support P2P hotplug on Book3E, we'll have
	 * to do an appropriate TLB flush here too
	 */
	if (bus->self) {
#ifdef CONFIG_PPC_STD_MMU_64
		struct resource *res = bus->resource[0];
#endif

		pr_debug("IO unmapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));

#ifdef CONFIG_PPC_STD_MMU_64
		__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
					 res->end + _IO_BASE + 1);
#endif
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);

	/* Check if we have IOs allocated */
	if (hose->io_base_alloc == 0)
		return 0;

	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  alloc=0x%p\n", hose->io_base_alloc);

	/* This is a PHB, we fully unmap the IO area */
	vunmap(hose->io_base_alloc);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);

#endif /* CONFIG_HOTPLUG */

int __devinit pcibios_map_io_space(struct pci_bus *bus)
{
	struct vm_struct *area;
	unsigned long phys_page;
	unsigned long size_page;
	unsigned long io_virt_offset;
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this not a PHB, nothing to do, page tables still exist and
	 * thus HPTEs will be faulted in when needed
	 */
	if (bus->self) {
		pr_debug("IO mapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));
		pr_debug("  virt=0x%016llx...0x%016llx\n",
			 bus->resource[0]->start + _IO_BASE,
			 bus->resource[0]->end + _IO_BASE);
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);
	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);

	/* Make sure IO area address is clear */
	hose->io_base_alloc = NULL;

	/* If there's no IO to map on that bus, get away too */
	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
		return 0;

	/* Let's allocate some IO space for that guy. We don't pass
	 * VM_IOREMAP because we don't care about alignment tricks that
	 * the core does in that case. Maybe we should due to stupid card
	 * with incomplete address decoding but I'd rather not deal with
	 * those outside of the reserved 64K legacy region.
	 */
	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	if (area == NULL)
		return -ENOMEM;
	hose->io_base_alloc = area->addr;
	hose->io_base_virt = (void __iomem *)(area->addr +
					      hose->io_base_phys - phys_page);

	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
		 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
	pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
		 hose->pci_io_size, size_page);

	/* Establish the mapping */
	if (__ioremap_at(phys_page, area->addr, size_page,
			 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
		return -ENOMEM;

	/* Fixup hose IO resource */
	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	hose->io_resource.start += io_virt_offset;
	hose->io_resource.end += io_virt_offset;

	pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
		 hose->io_resource.start, hose->io_resource.end);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_map_io_space);

void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
{
	pcibios_map_io_space(hose->bus);
}

#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

long sys_pciconfig_iobase(long which, unsigned long in_bus,
			  unsigned long in_devfn)
{
	struct pci_controller* hose;
	struct list_head *ln;
	struct pci_bus *bus = NULL;
	struct device_node *hose_node;

	/* Argh ! Please forgive me for that hack, but that's the
	 * simplest way to get existing XFree to not lockup on some
	 * G5 machines... So when something asks for bus 0 io base
	 * (bus 0 is HT root), we return the AGP one instead.
	 */
	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
		struct device_node *agp;

		agp = of_find_compatible_node(NULL, NULL, "u3-agp");
		if (agp)
			in_bus = 0xf0;
		of_node_put(agp);
	}

	/* That syscall isn't quite compatible with PCI domains, but it's
	 * used on pre-domains setup. We return the first match
	 */

	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
		bus = pci_bus_b(ln);
		if (in_bus >= bus->number && in_bus <= bus->subordinate)
			break;
		bus = NULL;
	}
	if (bus == NULL || bus->sysdata == NULL)
		return -ENODEV;

	hose_node = (struct device_node *)bus->sysdata;
	hose = PCI_DN(hose_node)->phb;

	switch (which) {
	case IOBASE_BRIDGE_NUMBER:
		return (long)hose->first_busno;
	case IOBASE_MEMORY:
		return (long)hose->pci_mem_offset;
	case IOBASE_IO:
		return (long)hose->io_base_phys;
	case IOBASE_ISA_IO:
		return (long)isa_io_base;
	case IOBASE_ISA_MEM:
		return -EINVAL;
	}

	return -EOPNOTSUPP;
}

#ifdef CONFIG_NUMA
int pcibus_to_node(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);
	return phb->node;
}
EXPORT_SYMBOL(pcibus_to_node);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Port for PPC64 David Engebretsen, IBM Corp.
	3	* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
	4	*
	5	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	6	* Rework, based on alpha PCI code.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#undef DEBUG
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/bootmem.h>
	21	#include <linux/mm.h>
	22	#include <linux/list.h>
b2ad7b5e	23	#include <linux/syscalls.h>
6e99e458	24	#include <linux/irq.h>
3d5134ee	25	#include <linux/vmalloc.h>
1da177e4 LT	26
	27	#include <asm/processor.h>
	28	#include <asm/io.h>
	29	#include <asm/prom.h>
	30	#include <asm/pci-bridge.h>
	31	#include <asm/byteorder.h>
1da177e4	32	#include <asm/machdep.h>
d387899f	33	#include <asm/ppc-pci.h>
1da177e4	34
1da177e4	35	unsigned long pci_probe_only = 1;
1da177e4	36
1da177e4 LT	37	/* pci_io_base -- the base address from which io bars are offsets.
	38	* This is the lowest I/O base address (so bar values are always positive),
	39	* and it must be the start of ISA space if an ISA bus exists because
3d5134ee BH	40	* ISA drivers use hard coded offsets. If no ISA bus exists nothing
3d5134ee BH	41	* is mapped on the first 64K of IO space
1da177e4	42	*/
3d5134ee	43	unsigned long pci_io_base = ISA_IO_BASE;
1da177e4 LT	44	EXPORT_SYMBOL(pci_io_base);
1da177e4 LT	45
1da177e4 LT	46	static int __init pcibios_init(void)
	47	{
	48	struct pci_controller hose, tmp;
1da177e4	49
3fd94c6b BH	50	printk(KERN_INFO "PCI: Probing PCI hardware\n");
3fd94c6b BH	51
53280323	52	/* For now, override phys_mem_access_prot. If we need it,g
1da177e4 LT	53	* later, we may move that initialization to each ppc_md
	54	*/
	55	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	56
3fd94c6b BH	57	if (pci_probe_only)
3fd94c6b BH	58	ppc_pci_flags \|= PPC_PCI_PROBE_ONLY;
1da177e4	59
1fd0f525 BH	60	/* On ppc64, we always enable PCI domains and we keep domain 0
	61	* backward compatible in /proc for video cards
	62	*/
	63	ppc_pci_flags \|= PPC_PCI_ENABLE_PROC_DOMAINS \| PPC_PCI_COMPAT_DOMAIN_0;
	64
1da177e4	65	/* Scan all of the recorded PCI controllers. */
92eb4602	66	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
0ed2c722	67	pcibios_scan_phb(hose, hose->dn);
92eb4602 JR	68	pci_bus_add_devices(hose->bus);
92eb4602 JR	69	}
1da177e4	70
3fd94c6b BH	71	/* Call common code to handle resource allocation */
3fd94c6b BH	72	pcibios_resource_survey();
1da177e4	73
e884e9c5	74	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
1da177e4 LT	75
	76	return 0;
	77	}
	78
	79	subsys_initcall(pcibios_init);
	80
3d5134ee BH	81	#ifdef CONFIG_HOTPLUG
	82
	83	int pcibios_unmap_io_space(struct pci_bus *bus)
1da177e4	84	{
3d5134ee	85	struct pci_controller *hose;
1da177e4	86
3d5134ee	87	WARN_ON(bus == NULL);
de821204	88
3d5134ee BH	89	/* If this is not a PHB, we only flush the hash table over
	90	* the area mapped by this bridge. We don't play with the PTE
	91	* mappings since we might have to deal with sub-page alignemnts
	92	* so flushing the hash table is the only sane way to make sure
	93	* that no hash entries are covering that removed bridge area
	94	* while still allowing other busses overlapping those pages
94491685 BH	95	*
	96	* Note: If we ever support P2P hotplug on Book3E, we'll have
	97	* to do an appropriate TLB flush here too
3d5134ee BH	98	*/
3d5134ee BH	99	if (bus->self) {
ce7a35c7	100	#ifdef CONFIG_PPC_STD_MMU_64
3d5134ee	101	struct resource *res = bus->resource[0];
ce7a35c7	102	#endif
1da177e4	103
b0494bc8 BH	104	pr_debug("IO unmapping for PCI-PCI bridge %s\n",
b0494bc8 BH	105	pci_name(bus->self));
de821204	106
94491685	107	#ifdef CONFIG_PPC_STD_MMU_64
3d5134ee	108	__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
b30115ea	109	res->end + _IO_BASE + 1);
94491685	110	#endif
3d5134ee BH	111	return 0;
3d5134ee BH	112	}
1da177e4	113
3d5134ee BH	114	/* Get the host bridge */
3d5134ee BH	115	hose = pci_bus_to_host(bus);
1da177e4	116
3d5134ee BH	117	/* Check if we have IOs allocated */
	118	if (hose->io_base_alloc == 0)
	119	return 0;
de821204	120
b0494bc8 BH	121	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
b0494bc8 BH	122	pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
1da177e4	123
3d5134ee BH	124	/* This is a PHB, we fully unmap the IO area */
3d5134ee BH	125	vunmap(hose->io_base_alloc);
1da177e4	126
3d5134ee	127	return 0;
1da177e4	128	}
3d5134ee	129	EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
1da177e4	130
3d5134ee	131	#endif /* CONFIG_HOTPLUG */
1da177e4	132
3d5134ee	133	int __devinit pcibios_map_io_space(struct pci_bus *bus)
1da177e4	134	{
3d5134ee BH	135	struct vm_struct *area;
	136	unsigned long phys_page;
	137	unsigned long size_page;
	138	unsigned long io_virt_offset;
	139	struct pci_controller *hose;
de821204	140
3d5134ee	141	WARN_ON(bus == NULL);
31e92e0a	142
3d5134ee BH	143	/* If this not a PHB, nothing to do, page tables still exist and
	144	* thus HPTEs will be faulted in when needed
	145	*/
	146	if (bus->self) {
b0494bc8 BH	147	pr_debug("IO mapping for PCI-PCI bridge %s\n",
b0494bc8 BH	148	pci_name(bus->self));
9477e455	149	pr_debug(" virt=0x%016llx...0x%016llx\n",
b0494bc8 BH	150	bus->resource[0]->start + _IO_BASE,
b0494bc8 BH	151	bus->resource[0]->end + _IO_BASE);
3d5134ee	152	return 0;
1da177e4 LT	153	}
1da177e4 LT	154
3d5134ee BH	155	/* Get the host bridge */
	156	hose = pci_bus_to_host(bus);
	157	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	158	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
1da177e4	159
3d5134ee BH	160	/* Make sure IO area address is clear */
3d5134ee BH	161	hose->io_base_alloc = NULL;
1da177e4	162
3d5134ee BH	163	/* If there's no IO to map on that bus, get away too */
	164	if (hose->pci_io_size == 0 \|\| hose->io_base_phys == 0)
	165	return 0;
1da177e4	166
3d5134ee BH	167	/* Let's allocate some IO space for that guy. We don't pass
	168	* VM_IOREMAP because we don't care about alignment tricks that
	169	* the core does in that case. Maybe we should due to stupid card
	170	* with incomplete address decoding but I'd rather not deal with
	171	* those outside of the reserved 64K legacy region.
	172	*/
	173	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	174	if (area == NULL)
	175	return -ENOMEM;
	176	hose->io_base_alloc = area->addr;
	177	hose->io_base_virt = (void __iomem *)(area->addr +
	178	hose->io_base_phys - phys_page);
	179
b0494bc8	180	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
9477e455	181	pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
b0494bc8	182	hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
bcba0778	183	pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
b0494bc8	184	hose->pci_io_size, size_page);
3d5134ee BH	185
	186	/* Establish the mapping */
	187	if (__ioremap_at(phys_page, area->addr, size_page,
	188	_PAGE_NO_CACHE \| _PAGE_GUARDED) == NULL)
	189	return -ENOMEM;
	190
	191	/* Fixup hose IO resource */
	192	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	193	hose->io_resource.start += io_virt_offset;
	194	hose->io_resource.end += io_virt_offset;
	195
9477e455	196	pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n",
b0494bc8	197	hose->io_resource.start, hose->io_resource.end);
1da177e4 LT	198
	199	return 0;
	200	}
3d5134ee	201	EXPORT_SYMBOL_GPL(pcibios_map_io_space);
1da177e4	202
0ed2c722 GL	203	void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
	204	{
	205	pcibios_map_io_space(hose->bus);
	206	}
	207
b2ad7b5e PM	208	#define IOBASE_BRIDGE_NUMBER 0
	209	#define IOBASE_MEMORY 1
	210	#define IOBASE_IO 2
	211	#define IOBASE_ISA_IO 3
	212	#define IOBASE_ISA_MEM 4
	213
	214	long sys_pciconfig_iobase(long which, unsigned long in_bus,
	215	unsigned long in_devfn)
	216	{
	217	struct pci_controller* hose;
	218	struct list_head *ln;
	219	struct pci_bus *bus = NULL;
	220	struct device_node *hose_node;
	221
	222	/* Argh ! Please forgive me for that hack, but that's the
	223	* simplest way to get existing XFree to not lockup on some
	224	* G5 machines... So when something asks for bus 0 io base
	225	* (bus 0 is HT root), we return the AGP one instead.
	226	*/
71a157e8	227	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
16124f10 PM	228	struct device_node *agp;
	229
	230	agp = of_find_compatible_node(NULL, NULL, "u3-agp");
	231	if (agp)
b2ad7b5e	232	in_bus = 0xf0;
16124f10 PM	233	of_node_put(agp);
16124f10 PM	234	}
b2ad7b5e PM	235
	236	/* That syscall isn't quite compatible with PCI domains, but it's
	237	* used on pre-domains setup. We return the first match
	238	*/
	239
	240	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
	241	bus = pci_bus_b(ln);
545da94f	242	if (in_bus >= bus->number && in_bus <= bus->subordinate)
b2ad7b5e PM	243	break;
	244	bus = NULL;
	245	}
	246	if (bus == NULL \|\| bus->sysdata == NULL)
	247	return -ENODEV;
	248
	249	hose_node = (struct device_node *)bus->sysdata;
	250	hose = PCI_DN(hose_node)->phb;
	251
	252	switch (which) {
	253	case IOBASE_BRIDGE_NUMBER:
	254	return (long)hose->first_busno;
	255	case IOBASE_MEMORY:
	256	return (long)hose->pci_mem_offset;
	257	case IOBASE_IO:
	258	return (long)hose->io_base_phys;
	259	case IOBASE_ISA_IO:
	260	return (long)isa_io_base;
	261	case IOBASE_ISA_MEM:
	262	return -EINVAL;
	263	}
	264
	265	return -EOPNOTSUPP;
	266	}
357518fa AB	267
	268	#ifdef CONFIG_NUMA
	269	int pcibus_to_node(struct pci_bus *bus)
	270	{
	271	struct pci_controller *phb = pci_bus_to_host(bus);
	272	return phb->node;
	273	}
	274	EXPORT_SYMBOL(pcibus_to_node);
	275	#endif