Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Derived from arch/i386/kernel/irq.c |
3 | * Copyright (C) 1992 Linus Torvalds | |
4 | * Adapted from arch/i386 by Gary Thomas | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
756e7104 SR |
6 | * Updated and modified by Cort Dougan <cort@fsmlabs.com> |
7 | * Copyright (C) 1996-2001 Cort Dougan | |
1da177e4 LT |
8 | * Adapted for Power Macintosh by Paul Mackerras |
9 | * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au) | |
756e7104 | 10 | * |
1da177e4 LT |
11 | * This program is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This file contains the code used by various IRQ handling routines: | |
17 | * asking for different IRQ's should be done through these routines | |
18 | * instead of just grabbing them. Thus setups with different IRQ numbers | |
19 | * shouldn't result in any weird surprises, and installing new handlers | |
20 | * should be easier. | |
756e7104 SR |
21 | * |
22 | * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the | |
23 | * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit | |
24 | * mask register (of which only 16 are defined), hence the weird shifting | |
25 | * and complement of the cached_irq_mask. I want to be able to stuff | |
26 | * this right into the SIU SMASK register. | |
27 | * Many of the prep/chrp functions are conditional compiled on CONFIG_8xx | |
28 | * to reduce code space and undefined function references. | |
1da177e4 LT |
29 | */ |
30 | ||
0ebfff14 BH |
31 | #undef DEBUG |
32 | ||
1da177e4 LT |
33 | #include <linux/module.h> |
34 | #include <linux/threads.h> | |
35 | #include <linux/kernel_stat.h> | |
36 | #include <linux/signal.h> | |
37 | #include <linux/sched.h> | |
756e7104 | 38 | #include <linux/ptrace.h> |
1da177e4 LT |
39 | #include <linux/ioport.h> |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/timex.h> | |
1da177e4 LT |
42 | #include <linux/init.h> |
43 | #include <linux/slab.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/irq.h> | |
756e7104 SR |
46 | #include <linux/seq_file.h> |
47 | #include <linux/cpumask.h> | |
1da177e4 LT |
48 | #include <linux/profile.h> |
49 | #include <linux/bitops.h> | |
0ebfff14 BH |
50 | #include <linux/list.h> |
51 | #include <linux/radix-tree.h> | |
52 | #include <linux/mutex.h> | |
53 | #include <linux/bootmem.h> | |
45934c47 | 54 | #include <linux/pci.h> |
1da177e4 LT |
55 | |
56 | #include <asm/uaccess.h> | |
57 | #include <asm/system.h> | |
58 | #include <asm/io.h> | |
59 | #include <asm/pgtable.h> | |
60 | #include <asm/irq.h> | |
61 | #include <asm/cache.h> | |
62 | #include <asm/prom.h> | |
63 | #include <asm/ptrace.h> | |
1da177e4 | 64 | #include <asm/machdep.h> |
0ebfff14 | 65 | #include <asm/udbg.h> |
d04c56f7 | 66 | #ifdef CONFIG_PPC64 |
1da177e4 | 67 | #include <asm/paca.h> |
d04c56f7 | 68 | #include <asm/firmware.h> |
0874dd40 | 69 | #include <asm/lv1call.h> |
756e7104 | 70 | #endif |
1da177e4 | 71 | |
868accb7 | 72 | int __irq_offset_value; |
756e7104 SR |
73 | static int ppc_spurious_interrupts; |
74 | ||
756e7104 | 75 | #ifdef CONFIG_PPC32 |
b9e5b4e6 BH |
76 | EXPORT_SYMBOL(__irq_offset_value); |
77 | atomic_t ppc_n_lost_interrupts; | |
756e7104 | 78 | |
b9e5b4e6 BH |
79 | #ifndef CONFIG_PPC_MERGE |
80 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) | |
756e7104 | 81 | unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; |
b9e5b4e6 | 82 | #endif |
756e7104 SR |
83 | |
84 | #ifdef CONFIG_TAU_INT | |
85 | extern int tau_initialized; | |
86 | extern int tau_interrupts(int); | |
87 | #endif | |
b9e5b4e6 | 88 | #endif /* CONFIG_PPC32 */ |
756e7104 SR |
89 | |
90 | #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE) | |
91 | extern atomic_t ipi_recv; | |
92 | extern atomic_t ipi_sent; | |
93 | #endif | |
756e7104 SR |
94 | |
95 | #ifdef CONFIG_PPC64 | |
1da177e4 LT |
96 | EXPORT_SYMBOL(irq_desc); |
97 | ||
98 | int distribute_irqs = 1; | |
d04c56f7 | 99 | |
ef2b343e HD |
100 | static inline unsigned long get_hard_enabled(void) |
101 | { | |
102 | unsigned long enabled; | |
103 | ||
104 | __asm__ __volatile__("lbz %0,%1(13)" | |
105 | : "=r" (enabled) : "i" (offsetof(struct paca_struct, hard_enabled))); | |
106 | ||
107 | return enabled; | |
108 | } | |
109 | ||
110 | static inline void set_soft_enabled(unsigned long enable) | |
111 | { | |
112 | __asm__ __volatile__("stb %0,%1(13)" | |
113 | : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); | |
114 | } | |
115 | ||
d04c56f7 PM |
116 | void local_irq_restore(unsigned long en) |
117 | { | |
ef2b343e HD |
118 | /* |
119 | * get_paca()->soft_enabled = en; | |
120 | * Is it ever valid to use local_irq_restore(0) when soft_enabled is 1? | |
121 | * That was allowed before, and in such a case we do need to take care | |
122 | * that gcc will set soft_enabled directly via r13, not choose to use | |
123 | * an intermediate register, lest we're preempted to a different cpu. | |
124 | */ | |
125 | set_soft_enabled(en); | |
d04c56f7 PM |
126 | if (!en) |
127 | return; | |
128 | ||
129 | if (firmware_has_feature(FW_FEATURE_ISERIES)) { | |
ef2b343e HD |
130 | /* |
131 | * Do we need to disable preemption here? Not really: in the | |
132 | * unlikely event that we're preempted to a different cpu in | |
133 | * between getting r13, loading its lppaca_ptr, and loading | |
134 | * its any_int, we might call iseries_handle_interrupts without | |
135 | * an interrupt pending on the new cpu, but that's no disaster, | |
136 | * is it? And the business of preempting us off the old cpu | |
137 | * would itself involve a local_irq_restore which handles the | |
138 | * interrupt to that cpu. | |
139 | * | |
140 | * But use "local_paca->lppaca_ptr" instead of "get_lppaca()" | |
141 | * to avoid any preemption checking added into get_paca(). | |
142 | */ | |
143 | if (local_paca->lppaca_ptr->int_dword.any_int) | |
d04c56f7 PM |
144 | iseries_handle_interrupts(); |
145 | return; | |
146 | } | |
147 | ||
ef2b343e HD |
148 | /* |
149 | * if (get_paca()->hard_enabled) return; | |
150 | * But again we need to take care that gcc gets hard_enabled directly | |
151 | * via r13, not choose to use an intermediate register, lest we're | |
152 | * preempted to a different cpu in between the two instructions. | |
153 | */ | |
154 | if (get_hard_enabled()) | |
d04c56f7 | 155 | return; |
ef2b343e HD |
156 | |
157 | /* | |
158 | * Need to hard-enable interrupts here. Since currently disabled, | |
159 | * no need to take further asm precautions against preemption; but | |
160 | * use local_paca instead of get_paca() to avoid preemption checking. | |
161 | */ | |
162 | local_paca->hard_enabled = en; | |
d04c56f7 PM |
163 | if ((int)mfspr(SPRN_DEC) < 0) |
164 | mtspr(SPRN_DEC, 1); | |
0874dd40 TS |
165 | |
166 | /* | |
167 | * Force the delivery of pending soft-disabled interrupts on PS3. | |
168 | * Any HV call will have this side effect. | |
169 | */ | |
170 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
171 | u64 tmp; | |
172 | lv1_get_version_info(&tmp); | |
173 | } | |
174 | ||
e1fa2e13 | 175 | __hard_irq_enable(); |
d04c56f7 | 176 | } |
756e7104 | 177 | #endif /* CONFIG_PPC64 */ |
1da177e4 LT |
178 | |
179 | int show_interrupts(struct seq_file *p, void *v) | |
180 | { | |
756e7104 SR |
181 | int i = *(loff_t *)v, j; |
182 | struct irqaction *action; | |
1da177e4 LT |
183 | irq_desc_t *desc; |
184 | unsigned long flags; | |
185 | ||
186 | if (i == 0) { | |
756e7104 SR |
187 | seq_puts(p, " "); |
188 | for_each_online_cpu(j) | |
189 | seq_printf(p, "CPU%d ", j); | |
1da177e4 LT |
190 | seq_putc(p, '\n'); |
191 | } | |
192 | ||
193 | if (i < NR_IRQS) { | |
194 | desc = get_irq_desc(i); | |
195 | spin_lock_irqsave(&desc->lock, flags); | |
196 | action = desc->action; | |
197 | if (!action || !action->handler) | |
198 | goto skip; | |
199 | seq_printf(p, "%3d: ", i); | |
200 | #ifdef CONFIG_SMP | |
756e7104 SR |
201 | for_each_online_cpu(j) |
202 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 LT |
203 | #else |
204 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
205 | #endif /* CONFIG_SMP */ | |
d1bef4ed IM |
206 | if (desc->chip) |
207 | seq_printf(p, " %s ", desc->chip->typename); | |
1da177e4 | 208 | else |
756e7104 | 209 | seq_puts(p, " None "); |
1da177e4 | 210 | seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge "); |
756e7104 SR |
211 | seq_printf(p, " %s", action->name); |
212 | for (action = action->next; action; action = action->next) | |
1da177e4 LT |
213 | seq_printf(p, ", %s", action->name); |
214 | seq_putc(p, '\n'); | |
215 | skip: | |
216 | spin_unlock_irqrestore(&desc->lock, flags); | |
756e7104 SR |
217 | } else if (i == NR_IRQS) { |
218 | #ifdef CONFIG_PPC32 | |
219 | #ifdef CONFIG_TAU_INT | |
220 | if (tau_initialized){ | |
221 | seq_puts(p, "TAU: "); | |
394e3902 AM |
222 | for_each_online_cpu(j) |
223 | seq_printf(p, "%10u ", tau_interrupts(j)); | |
756e7104 SR |
224 | seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n"); |
225 | } | |
226 | #endif | |
227 | #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE) | |
228 | /* should this be per processor send/receive? */ | |
229 | seq_printf(p, "IPI (recv/sent): %10u/%u\n", | |
230 | atomic_read(&ipi_recv), atomic_read(&ipi_sent)); | |
231 | #endif | |
232 | #endif /* CONFIG_PPC32 */ | |
1da177e4 | 233 | seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts); |
756e7104 | 234 | } |
1da177e4 LT |
235 | return 0; |
236 | } | |
237 | ||
238 | #ifdef CONFIG_HOTPLUG_CPU | |
239 | void fixup_irqs(cpumask_t map) | |
240 | { | |
241 | unsigned int irq; | |
242 | static int warned; | |
243 | ||
244 | for_each_irq(irq) { | |
245 | cpumask_t mask; | |
246 | ||
247 | if (irq_desc[irq].status & IRQ_PER_CPU) | |
248 | continue; | |
249 | ||
a53da52f | 250 | cpus_and(mask, irq_desc[irq].affinity, map); |
1da177e4 LT |
251 | if (any_online_cpu(mask) == NR_CPUS) { |
252 | printk("Breaking affinity for irq %i\n", irq); | |
253 | mask = map; | |
254 | } | |
d1bef4ed IM |
255 | if (irq_desc[irq].chip->set_affinity) |
256 | irq_desc[irq].chip->set_affinity(irq, mask); | |
1da177e4 LT |
257 | else if (irq_desc[irq].action && !(warned++)) |
258 | printk("Cannot set affinity for irq %i\n", irq); | |
259 | } | |
260 | ||
261 | local_irq_enable(); | |
262 | mdelay(1); | |
263 | local_irq_disable(); | |
264 | } | |
265 | #endif | |
266 | ||
1da177e4 LT |
267 | void do_IRQ(struct pt_regs *regs) |
268 | { | |
7d12e780 | 269 | struct pt_regs *old_regs = set_irq_regs(regs); |
0ebfff14 | 270 | unsigned int irq; |
b709c083 SR |
271 | #ifdef CONFIG_IRQSTACKS |
272 | struct thread_info *curtp, *irqtp; | |
273 | #endif | |
1da177e4 | 274 | |
756e7104 | 275 | irq_enter(); |
1da177e4 LT |
276 | |
277 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | |
278 | /* Debugging check for stack overflow: is there less than 2KB free? */ | |
279 | { | |
280 | long sp; | |
281 | ||
282 | sp = __get_SP() & (THREAD_SIZE-1); | |
283 | ||
284 | if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { | |
285 | printk("do_IRQ: stack overflow: %ld\n", | |
286 | sp - sizeof(struct thread_info)); | |
287 | dump_stack(); | |
288 | } | |
289 | } | |
290 | #endif | |
291 | ||
756e7104 SR |
292 | /* |
293 | * Every platform is required to implement ppc_md.get_irq. | |
92d4dda3 | 294 | * This function will either return an irq number or NO_IRQ to |
756e7104 | 295 | * indicate there are no more pending. |
92d4dda3 JB |
296 | * The value NO_IRQ_IGNORE is for buggy hardware and means that this |
297 | * IRQ has already been handled. -- Tom | |
756e7104 | 298 | */ |
35a84c2f | 299 | irq = ppc_md.get_irq(); |
1da177e4 | 300 | |
0ebfff14 | 301 | if (irq != NO_IRQ && irq != NO_IRQ_IGNORE) { |
b709c083 SR |
302 | #ifdef CONFIG_IRQSTACKS |
303 | /* Switch to the irq stack to handle this */ | |
304 | curtp = current_thread_info(); | |
305 | irqtp = hardirq_ctx[smp_processor_id()]; | |
306 | if (curtp != irqtp) { | |
b9e5b4e6 BH |
307 | struct irq_desc *desc = irq_desc + irq; |
308 | void *handler = desc->handle_irq; | |
309 | if (handler == NULL) | |
310 | handler = &__do_IRQ; | |
b709c083 SR |
311 | irqtp->task = curtp->task; |
312 | irqtp->flags = 0; | |
7d12e780 | 313 | call_handle_irq(irq, desc, irqtp, handler); |
b709c083 SR |
314 | irqtp->task = NULL; |
315 | if (irqtp->flags) | |
316 | set_bits(irqtp->flags, &curtp->flags); | |
317 | } else | |
318 | #endif | |
7d12e780 | 319 | generic_handle_irq(irq); |
0ebfff14 | 320 | } else if (irq != NO_IRQ_IGNORE) |
e199500c SR |
321 | /* That's not SMP safe ... but who cares ? */ |
322 | ppc_spurious_interrupts++; | |
323 | ||
756e7104 | 324 | irq_exit(); |
7d12e780 | 325 | set_irq_regs(old_regs); |
756e7104 | 326 | |
e199500c | 327 | #ifdef CONFIG_PPC_ISERIES |
b06a3183 SR |
328 | if (firmware_has_feature(FW_FEATURE_ISERIES) && |
329 | get_lppaca()->int_dword.fields.decr_int) { | |
3356bb9f DG |
330 | get_lppaca()->int_dword.fields.decr_int = 0; |
331 | /* Signal a fake decrementer interrupt */ | |
332 | timer_interrupt(regs); | |
e199500c SR |
333 | } |
334 | #endif | |
335 | } | |
1da177e4 LT |
336 | |
337 | void __init init_IRQ(void) | |
338 | { | |
1da177e4 | 339 | ppc_md.init_IRQ(); |
756e7104 | 340 | #ifdef CONFIG_PPC64 |
1da177e4 | 341 | irq_ctx_init(); |
756e7104 | 342 | #endif |
1da177e4 LT |
343 | } |
344 | ||
1da177e4 | 345 | |
1da177e4 | 346 | #ifdef CONFIG_IRQSTACKS |
22722051 AM |
347 | struct thread_info *softirq_ctx[NR_CPUS] __read_mostly; |
348 | struct thread_info *hardirq_ctx[NR_CPUS] __read_mostly; | |
1da177e4 LT |
349 | |
350 | void irq_ctx_init(void) | |
351 | { | |
352 | struct thread_info *tp; | |
353 | int i; | |
354 | ||
0e551954 | 355 | for_each_possible_cpu(i) { |
1da177e4 LT |
356 | memset((void *)softirq_ctx[i], 0, THREAD_SIZE); |
357 | tp = softirq_ctx[i]; | |
358 | tp->cpu = i; | |
359 | tp->preempt_count = SOFTIRQ_OFFSET; | |
360 | ||
361 | memset((void *)hardirq_ctx[i], 0, THREAD_SIZE); | |
362 | tp = hardirq_ctx[i]; | |
363 | tp->cpu = i; | |
364 | tp->preempt_count = HARDIRQ_OFFSET; | |
365 | } | |
366 | } | |
367 | ||
c6622f63 PM |
368 | static inline void do_softirq_onstack(void) |
369 | { | |
370 | struct thread_info *curtp, *irqtp; | |
371 | ||
372 | curtp = current_thread_info(); | |
373 | irqtp = softirq_ctx[smp_processor_id()]; | |
374 | irqtp->task = curtp->task; | |
375 | call_do_softirq(irqtp); | |
376 | irqtp->task = NULL; | |
377 | } | |
1da177e4 | 378 | |
c6622f63 PM |
379 | #else |
380 | #define do_softirq_onstack() __do_softirq() | |
381 | #endif /* CONFIG_IRQSTACKS */ | |
382 | ||
1da177e4 LT |
383 | void do_softirq(void) |
384 | { | |
385 | unsigned long flags; | |
1da177e4 LT |
386 | |
387 | if (in_interrupt()) | |
1da177e4 LT |
388 | return; |
389 | ||
1da177e4 | 390 | local_irq_save(flags); |
1da177e4 | 391 | |
912b2539 | 392 | if (local_softirq_pending()) |
c6622f63 | 393 | do_softirq_onstack(); |
1da177e4 LT |
394 | |
395 | local_irq_restore(flags); | |
1da177e4 | 396 | } |
1da177e4 LT |
397 | EXPORT_SYMBOL(do_softirq); |
398 | ||
1da177e4 | 399 | |
1da177e4 | 400 | /* |
0ebfff14 | 401 | * IRQ controller and virtual interrupts |
1da177e4 LT |
402 | */ |
403 | ||
0ebfff14 | 404 | #ifdef CONFIG_PPC_MERGE |
1da177e4 | 405 | |
0ebfff14 | 406 | static LIST_HEAD(irq_hosts); |
057b184a | 407 | static DEFINE_SPINLOCK(irq_big_lock); |
8ec8f2e8 BH |
408 | static DEFINE_PER_CPU(unsigned int, irq_radix_reader); |
409 | static unsigned int irq_radix_writer; | |
0ebfff14 BH |
410 | struct irq_map_entry irq_map[NR_IRQS]; |
411 | static unsigned int irq_virq_count = NR_IRQS; | |
412 | static struct irq_host *irq_default_host; | |
1da177e4 | 413 | |
0ebfff14 BH |
414 | struct irq_host *irq_alloc_host(unsigned int revmap_type, |
415 | unsigned int revmap_arg, | |
416 | struct irq_host_ops *ops, | |
417 | irq_hw_number_t inval_irq) | |
1da177e4 | 418 | { |
0ebfff14 BH |
419 | struct irq_host *host; |
420 | unsigned int size = sizeof(struct irq_host); | |
421 | unsigned int i; | |
422 | unsigned int *rmap; | |
423 | unsigned long flags; | |
424 | ||
425 | /* Allocate structure and revmap table if using linear mapping */ | |
426 | if (revmap_type == IRQ_HOST_MAP_LINEAR) | |
427 | size += revmap_arg * sizeof(unsigned int); | |
428 | if (mem_init_done) | |
429 | host = kzalloc(size, GFP_KERNEL); | |
430 | else { | |
431 | host = alloc_bootmem(size); | |
432 | if (host) | |
433 | memset(host, 0, size); | |
434 | } | |
435 | if (host == NULL) | |
436 | return NULL; | |
7d01c880 | 437 | |
0ebfff14 BH |
438 | /* Fill structure */ |
439 | host->revmap_type = revmap_type; | |
440 | host->inval_irq = inval_irq; | |
441 | host->ops = ops; | |
7d01c880 | 442 | |
0ebfff14 BH |
443 | spin_lock_irqsave(&irq_big_lock, flags); |
444 | ||
445 | /* If it's a legacy controller, check for duplicates and | |
446 | * mark it as allocated (we use irq 0 host pointer for that | |
447 | */ | |
448 | if (revmap_type == IRQ_HOST_MAP_LEGACY) { | |
449 | if (irq_map[0].host != NULL) { | |
450 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
451 | /* If we are early boot, we can't free the structure, | |
452 | * too bad... | |
453 | * this will be fixed once slab is made available early | |
454 | * instead of the current cruft | |
455 | */ | |
456 | if (mem_init_done) | |
457 | kfree(host); | |
458 | return NULL; | |
459 | } | |
460 | irq_map[0].host = host; | |
461 | } | |
462 | ||
463 | list_add(&host->link, &irq_hosts); | |
464 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
465 | ||
466 | /* Additional setups per revmap type */ | |
467 | switch(revmap_type) { | |
468 | case IRQ_HOST_MAP_LEGACY: | |
469 | /* 0 is always the invalid number for legacy */ | |
470 | host->inval_irq = 0; | |
471 | /* setup us as the host for all legacy interrupts */ | |
472 | for (i = 1; i < NUM_ISA_INTERRUPTS; i++) { | |
473 | irq_map[i].hwirq = 0; | |
474 | smp_wmb(); | |
475 | irq_map[i].host = host; | |
476 | smp_wmb(); | |
477 | ||
6e99e458 BH |
478 | /* Clear norequest flags */ |
479 | get_irq_desc(i)->status &= ~IRQ_NOREQUEST; | |
0ebfff14 BH |
480 | |
481 | /* Legacy flags are left to default at this point, | |
482 | * one can then use irq_create_mapping() to | |
483 | * explicitely change them | |
484 | */ | |
6e99e458 | 485 | ops->map(host, i, i); |
0ebfff14 BH |
486 | } |
487 | break; | |
488 | case IRQ_HOST_MAP_LINEAR: | |
489 | rmap = (unsigned int *)(host + 1); | |
490 | for (i = 0; i < revmap_arg; i++) | |
f5921697 | 491 | rmap[i] = NO_IRQ; |
0ebfff14 BH |
492 | host->revmap_data.linear.size = revmap_arg; |
493 | smp_wmb(); | |
494 | host->revmap_data.linear.revmap = rmap; | |
495 | break; | |
496 | default: | |
497 | break; | |
498 | } | |
499 | ||
500 | pr_debug("irq: Allocated host of type %d @0x%p\n", revmap_type, host); | |
501 | ||
502 | return host; | |
1da177e4 LT |
503 | } |
504 | ||
0ebfff14 | 505 | struct irq_host *irq_find_host(struct device_node *node) |
1da177e4 | 506 | { |
0ebfff14 BH |
507 | struct irq_host *h, *found = NULL; |
508 | unsigned long flags; | |
509 | ||
510 | /* We might want to match the legacy controller last since | |
511 | * it might potentially be set to match all interrupts in | |
512 | * the absence of a device node. This isn't a problem so far | |
513 | * yet though... | |
514 | */ | |
515 | spin_lock_irqsave(&irq_big_lock, flags); | |
516 | list_for_each_entry(h, &irq_hosts, link) | |
517 | if (h->ops->match == NULL || h->ops->match(h, node)) { | |
518 | found = h; | |
519 | break; | |
520 | } | |
521 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
522 | return found; | |
523 | } | |
524 | EXPORT_SYMBOL_GPL(irq_find_host); | |
525 | ||
526 | void irq_set_default_host(struct irq_host *host) | |
527 | { | |
528 | pr_debug("irq: Default host set to @0x%p\n", host); | |
1da177e4 | 529 | |
0ebfff14 BH |
530 | irq_default_host = host; |
531 | } | |
1da177e4 | 532 | |
0ebfff14 BH |
533 | void irq_set_virq_count(unsigned int count) |
534 | { | |
535 | pr_debug("irq: Trying to set virq count to %d\n", count); | |
fef1c772 | 536 | |
0ebfff14 BH |
537 | BUG_ON(count < NUM_ISA_INTERRUPTS); |
538 | if (count < NR_IRQS) | |
539 | irq_virq_count = count; | |
540 | } | |
541 | ||
8ec8f2e8 BH |
542 | /* radix tree not lockless safe ! we use a brlock-type mecanism |
543 | * for now, until we can use a lockless radix tree | |
544 | */ | |
545 | static void irq_radix_wrlock(unsigned long *flags) | |
546 | { | |
547 | unsigned int cpu, ok; | |
548 | ||
549 | spin_lock_irqsave(&irq_big_lock, *flags); | |
550 | irq_radix_writer = 1; | |
551 | smp_mb(); | |
552 | do { | |
553 | barrier(); | |
554 | ok = 1; | |
555 | for_each_possible_cpu(cpu) { | |
556 | if (per_cpu(irq_radix_reader, cpu)) { | |
557 | ok = 0; | |
558 | break; | |
559 | } | |
560 | } | |
561 | if (!ok) | |
562 | cpu_relax(); | |
563 | } while(!ok); | |
564 | } | |
565 | ||
566 | static void irq_radix_wrunlock(unsigned long flags) | |
567 | { | |
568 | smp_wmb(); | |
569 | irq_radix_writer = 0; | |
570 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
571 | } | |
572 | ||
573 | static void irq_radix_rdlock(unsigned long *flags) | |
574 | { | |
575 | local_irq_save(*flags); | |
576 | __get_cpu_var(irq_radix_reader) = 1; | |
577 | smp_mb(); | |
578 | if (likely(irq_radix_writer == 0)) | |
579 | return; | |
580 | __get_cpu_var(irq_radix_reader) = 0; | |
581 | smp_wmb(); | |
582 | spin_lock(&irq_big_lock); | |
583 | __get_cpu_var(irq_radix_reader) = 1; | |
584 | spin_unlock(&irq_big_lock); | |
585 | } | |
586 | ||
587 | static void irq_radix_rdunlock(unsigned long flags) | |
588 | { | |
589 | __get_cpu_var(irq_radix_reader) = 0; | |
590 | local_irq_restore(flags); | |
591 | } | |
592 | ||
593 | ||
0ebfff14 | 594 | unsigned int irq_create_mapping(struct irq_host *host, |
6e99e458 | 595 | irq_hw_number_t hwirq) |
0ebfff14 BH |
596 | { |
597 | unsigned int virq, hint; | |
598 | ||
6e99e458 | 599 | pr_debug("irq: irq_create_mapping(0x%p, 0x%lx)\n", host, hwirq); |
0ebfff14 BH |
600 | |
601 | /* Look for default host if nececssary */ | |
602 | if (host == NULL) | |
603 | host = irq_default_host; | |
604 | if (host == NULL) { | |
605 | printk(KERN_WARNING "irq_create_mapping called for" | |
606 | " NULL host, hwirq=%lx\n", hwirq); | |
607 | WARN_ON(1); | |
608 | return NO_IRQ; | |
1da177e4 | 609 | } |
0ebfff14 | 610 | pr_debug("irq: -> using host @%p\n", host); |
1da177e4 | 611 | |
0ebfff14 BH |
612 | /* Check if mapping already exist, if it does, call |
613 | * host->ops->map() to update the flags | |
614 | */ | |
615 | virq = irq_find_mapping(host, hwirq); | |
f5921697 | 616 | if (virq != NO_IRQ) { |
acc900ef IK |
617 | if (host->ops->remap) |
618 | host->ops->remap(host, virq, hwirq); | |
0ebfff14 | 619 | pr_debug("irq: -> existing mapping on virq %d\n", virq); |
0ebfff14 | 620 | return virq; |
1da177e4 LT |
621 | } |
622 | ||
0ebfff14 BH |
623 | /* Get a virtual interrupt number */ |
624 | if (host->revmap_type == IRQ_HOST_MAP_LEGACY) { | |
625 | /* Handle legacy */ | |
626 | virq = (unsigned int)hwirq; | |
627 | if (virq == 0 || virq >= NUM_ISA_INTERRUPTS) | |
628 | return NO_IRQ; | |
629 | return virq; | |
630 | } else { | |
631 | /* Allocate a virtual interrupt number */ | |
632 | hint = hwirq % irq_virq_count; | |
633 | virq = irq_alloc_virt(host, 1, hint); | |
634 | if (virq == NO_IRQ) { | |
635 | pr_debug("irq: -> virq allocation failed\n"); | |
636 | return NO_IRQ; | |
637 | } | |
638 | } | |
639 | pr_debug("irq: -> obtained virq %d\n", virq); | |
640 | ||
6e99e458 BH |
641 | /* Clear IRQ_NOREQUEST flag */ |
642 | get_irq_desc(virq)->status &= ~IRQ_NOREQUEST; | |
0ebfff14 BH |
643 | |
644 | /* map it */ | |
6e99e458 BH |
645 | smp_wmb(); |
646 | irq_map[virq].hwirq = hwirq; | |
647 | smp_mb(); | |
648 | if (host->ops->map(host, virq, hwirq)) { | |
0ebfff14 BH |
649 | pr_debug("irq: -> mapping failed, freeing\n"); |
650 | irq_free_virt(virq, 1); | |
651 | return NO_IRQ; | |
652 | } | |
1da177e4 | 653 | return virq; |
0ebfff14 BH |
654 | } |
655 | EXPORT_SYMBOL_GPL(irq_create_mapping); | |
656 | ||
f3d2ab41 AV |
657 | unsigned int irq_create_of_mapping(struct device_node *controller, |
658 | u32 *intspec, unsigned int intsize) | |
0ebfff14 BH |
659 | { |
660 | struct irq_host *host; | |
661 | irq_hw_number_t hwirq; | |
6e99e458 BH |
662 | unsigned int type = IRQ_TYPE_NONE; |
663 | unsigned int virq; | |
1da177e4 | 664 | |
0ebfff14 BH |
665 | if (controller == NULL) |
666 | host = irq_default_host; | |
667 | else | |
668 | host = irq_find_host(controller); | |
6e99e458 BH |
669 | if (host == NULL) { |
670 | printk(KERN_WARNING "irq: no irq host found for %s !\n", | |
671 | controller->full_name); | |
0ebfff14 | 672 | return NO_IRQ; |
6e99e458 | 673 | } |
0ebfff14 BH |
674 | |
675 | /* If host has no translation, then we assume interrupt line */ | |
676 | if (host->ops->xlate == NULL) | |
677 | hwirq = intspec[0]; | |
678 | else { | |
679 | if (host->ops->xlate(host, controller, intspec, intsize, | |
6e99e458 | 680 | &hwirq, &type)) |
0ebfff14 | 681 | return NO_IRQ; |
1da177e4 | 682 | } |
0ebfff14 | 683 | |
6e99e458 BH |
684 | /* Create mapping */ |
685 | virq = irq_create_mapping(host, hwirq); | |
686 | if (virq == NO_IRQ) | |
687 | return virq; | |
688 | ||
689 | /* Set type if specified and different than the current one */ | |
690 | if (type != IRQ_TYPE_NONE && | |
691 | type != (get_irq_desc(virq)->status & IRQF_TRIGGER_MASK)) | |
692 | set_irq_type(virq, type); | |
693 | return virq; | |
1da177e4 | 694 | } |
0ebfff14 | 695 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); |
1da177e4 | 696 | |
0ebfff14 | 697 | unsigned int irq_of_parse_and_map(struct device_node *dev, int index) |
1da177e4 | 698 | { |
0ebfff14 | 699 | struct of_irq oirq; |
1da177e4 | 700 | |
0ebfff14 BH |
701 | if (of_irq_map_one(dev, index, &oirq)) |
702 | return NO_IRQ; | |
1da177e4 | 703 | |
0ebfff14 BH |
704 | return irq_create_of_mapping(oirq.controller, oirq.specifier, |
705 | oirq.size); | |
706 | } | |
707 | EXPORT_SYMBOL_GPL(irq_of_parse_and_map); | |
1da177e4 | 708 | |
0ebfff14 BH |
709 | void irq_dispose_mapping(unsigned int virq) |
710 | { | |
5414c6be | 711 | struct irq_host *host; |
0ebfff14 BH |
712 | irq_hw_number_t hwirq; |
713 | unsigned long flags; | |
1da177e4 | 714 | |
5414c6be ME |
715 | if (virq == NO_IRQ) |
716 | return; | |
717 | ||
718 | host = irq_map[virq].host; | |
0ebfff14 BH |
719 | WARN_ON (host == NULL); |
720 | if (host == NULL) | |
721 | return; | |
1da177e4 | 722 | |
0ebfff14 BH |
723 | /* Never unmap legacy interrupts */ |
724 | if (host->revmap_type == IRQ_HOST_MAP_LEGACY) | |
725 | return; | |
1da177e4 | 726 | |
0ebfff14 BH |
727 | /* remove chip and handler */ |
728 | set_irq_chip_and_handler(virq, NULL, NULL); | |
729 | ||
730 | /* Make sure it's completed */ | |
731 | synchronize_irq(virq); | |
732 | ||
733 | /* Tell the PIC about it */ | |
734 | if (host->ops->unmap) | |
735 | host->ops->unmap(host, virq); | |
736 | smp_mb(); | |
737 | ||
738 | /* Clear reverse map */ | |
739 | hwirq = irq_map[virq].hwirq; | |
740 | switch(host->revmap_type) { | |
741 | case IRQ_HOST_MAP_LINEAR: | |
742 | if (hwirq < host->revmap_data.linear.size) | |
f5921697 | 743 | host->revmap_data.linear.revmap[hwirq] = NO_IRQ; |
0ebfff14 BH |
744 | break; |
745 | case IRQ_HOST_MAP_TREE: | |
746 | /* Check if radix tree allocated yet */ | |
747 | if (host->revmap_data.tree.gfp_mask == 0) | |
748 | break; | |
8ec8f2e8 | 749 | irq_radix_wrlock(&flags); |
0ebfff14 | 750 | radix_tree_delete(&host->revmap_data.tree, hwirq); |
8ec8f2e8 | 751 | irq_radix_wrunlock(flags); |
0ebfff14 BH |
752 | break; |
753 | } | |
1da177e4 | 754 | |
0ebfff14 BH |
755 | /* Destroy map */ |
756 | smp_mb(); | |
757 | irq_map[virq].hwirq = host->inval_irq; | |
1da177e4 | 758 | |
0ebfff14 BH |
759 | /* Set some flags */ |
760 | get_irq_desc(virq)->status |= IRQ_NOREQUEST; | |
1da177e4 | 761 | |
0ebfff14 BH |
762 | /* Free it */ |
763 | irq_free_virt(virq, 1); | |
1da177e4 | 764 | } |
0ebfff14 | 765 | EXPORT_SYMBOL_GPL(irq_dispose_mapping); |
1da177e4 | 766 | |
0ebfff14 BH |
767 | unsigned int irq_find_mapping(struct irq_host *host, |
768 | irq_hw_number_t hwirq) | |
769 | { | |
770 | unsigned int i; | |
771 | unsigned int hint = hwirq % irq_virq_count; | |
772 | ||
773 | /* Look for default host if nececssary */ | |
774 | if (host == NULL) | |
775 | host = irq_default_host; | |
776 | if (host == NULL) | |
777 | return NO_IRQ; | |
778 | ||
779 | /* legacy -> bail early */ | |
780 | if (host->revmap_type == IRQ_HOST_MAP_LEGACY) | |
781 | return hwirq; | |
782 | ||
783 | /* Slow path does a linear search of the map */ | |
784 | if (hint < NUM_ISA_INTERRUPTS) | |
785 | hint = NUM_ISA_INTERRUPTS; | |
786 | i = hint; | |
787 | do { | |
788 | if (irq_map[i].host == host && | |
789 | irq_map[i].hwirq == hwirq) | |
790 | return i; | |
791 | i++; | |
792 | if (i >= irq_virq_count) | |
793 | i = NUM_ISA_INTERRUPTS; | |
794 | } while(i != hint); | |
795 | return NO_IRQ; | |
796 | } | |
797 | EXPORT_SYMBOL_GPL(irq_find_mapping); | |
1da177e4 | 798 | |
0ebfff14 BH |
799 | |
800 | unsigned int irq_radix_revmap(struct irq_host *host, | |
801 | irq_hw_number_t hwirq) | |
1da177e4 | 802 | { |
0ebfff14 BH |
803 | struct radix_tree_root *tree; |
804 | struct irq_map_entry *ptr; | |
805 | unsigned int virq; | |
806 | unsigned long flags; | |
1da177e4 | 807 | |
0ebfff14 | 808 | WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE); |
1da177e4 | 809 | |
0ebfff14 BH |
810 | /* Check if the radix tree exist yet. We test the value of |
811 | * the gfp_mask for that. Sneaky but saves another int in the | |
812 | * structure. If not, we fallback to slow mode | |
813 | */ | |
814 | tree = &host->revmap_data.tree; | |
815 | if (tree->gfp_mask == 0) | |
816 | return irq_find_mapping(host, hwirq); | |
817 | ||
0ebfff14 | 818 | /* Now try to resolve */ |
8ec8f2e8 | 819 | irq_radix_rdlock(&flags); |
0ebfff14 | 820 | ptr = radix_tree_lookup(tree, hwirq); |
8ec8f2e8 BH |
821 | irq_radix_rdunlock(flags); |
822 | ||
0ebfff14 BH |
823 | /* Found it, return */ |
824 | if (ptr) { | |
825 | virq = ptr - irq_map; | |
8ec8f2e8 | 826 | return virq; |
1da177e4 | 827 | } |
0ebfff14 BH |
828 | |
829 | /* If not there, try to insert it */ | |
830 | virq = irq_find_mapping(host, hwirq); | |
8ec8f2e8 BH |
831 | if (virq != NO_IRQ) { |
832 | irq_radix_wrlock(&flags); | |
e5c14ce1 | 833 | radix_tree_insert(tree, hwirq, &irq_map[virq]); |
8ec8f2e8 BH |
834 | irq_radix_wrunlock(flags); |
835 | } | |
0ebfff14 | 836 | return virq; |
1da177e4 LT |
837 | } |
838 | ||
0ebfff14 BH |
839 | unsigned int irq_linear_revmap(struct irq_host *host, |
840 | irq_hw_number_t hwirq) | |
c6622f63 | 841 | { |
0ebfff14 | 842 | unsigned int *revmap; |
c6622f63 | 843 | |
0ebfff14 BH |
844 | WARN_ON(host->revmap_type != IRQ_HOST_MAP_LINEAR); |
845 | ||
846 | /* Check revmap bounds */ | |
847 | if (unlikely(hwirq >= host->revmap_data.linear.size)) | |
848 | return irq_find_mapping(host, hwirq); | |
849 | ||
850 | /* Check if revmap was allocated */ | |
851 | revmap = host->revmap_data.linear.revmap; | |
852 | if (unlikely(revmap == NULL)) | |
853 | return irq_find_mapping(host, hwirq); | |
854 | ||
855 | /* Fill up revmap with slow path if no mapping found */ | |
856 | if (unlikely(revmap[hwirq] == NO_IRQ)) | |
857 | revmap[hwirq] = irq_find_mapping(host, hwirq); | |
858 | ||
859 | return revmap[hwirq]; | |
c6622f63 PM |
860 | } |
861 | ||
0ebfff14 BH |
862 | unsigned int irq_alloc_virt(struct irq_host *host, |
863 | unsigned int count, | |
864 | unsigned int hint) | |
865 | { | |
866 | unsigned long flags; | |
867 | unsigned int i, j, found = NO_IRQ; | |
c6622f63 | 868 | |
0ebfff14 BH |
869 | if (count == 0 || count > (irq_virq_count - NUM_ISA_INTERRUPTS)) |
870 | return NO_IRQ; | |
871 | ||
872 | spin_lock_irqsave(&irq_big_lock, flags); | |
873 | ||
874 | /* Use hint for 1 interrupt if any */ | |
875 | if (count == 1 && hint >= NUM_ISA_INTERRUPTS && | |
876 | hint < irq_virq_count && irq_map[hint].host == NULL) { | |
877 | found = hint; | |
878 | goto hint_found; | |
879 | } | |
880 | ||
881 | /* Look for count consecutive numbers in the allocatable | |
882 | * (non-legacy) space | |
883 | */ | |
e1251465 ME |
884 | for (i = NUM_ISA_INTERRUPTS, j = 0; i < irq_virq_count; i++) { |
885 | if (irq_map[i].host != NULL) | |
886 | j = 0; | |
887 | else | |
888 | j++; | |
889 | ||
890 | if (j == count) { | |
891 | found = i - count + 1; | |
892 | break; | |
893 | } | |
0ebfff14 BH |
894 | } |
895 | if (found == NO_IRQ) { | |
896 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
897 | return NO_IRQ; | |
898 | } | |
899 | hint_found: | |
900 | for (i = found; i < (found + count); i++) { | |
901 | irq_map[i].hwirq = host->inval_irq; | |
902 | smp_wmb(); | |
903 | irq_map[i].host = host; | |
904 | } | |
905 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
906 | return found; | |
907 | } | |
908 | ||
909 | void irq_free_virt(unsigned int virq, unsigned int count) | |
1da177e4 LT |
910 | { |
911 | unsigned long flags; | |
0ebfff14 | 912 | unsigned int i; |
1da177e4 | 913 | |
0ebfff14 BH |
914 | WARN_ON (virq < NUM_ISA_INTERRUPTS); |
915 | WARN_ON (count == 0 || (virq + count) > irq_virq_count); | |
1da177e4 | 916 | |
0ebfff14 BH |
917 | spin_lock_irqsave(&irq_big_lock, flags); |
918 | for (i = virq; i < (virq + count); i++) { | |
919 | struct irq_host *host; | |
1da177e4 | 920 | |
0ebfff14 BH |
921 | if (i < NUM_ISA_INTERRUPTS || |
922 | (virq + count) > irq_virq_count) | |
923 | continue; | |
1da177e4 | 924 | |
0ebfff14 BH |
925 | host = irq_map[i].host; |
926 | irq_map[i].hwirq = host->inval_irq; | |
927 | smp_wmb(); | |
928 | irq_map[i].host = NULL; | |
929 | } | |
930 | spin_unlock_irqrestore(&irq_big_lock, flags); | |
1da177e4 | 931 | } |
0ebfff14 BH |
932 | |
933 | void irq_early_init(void) | |
934 | { | |
935 | unsigned int i; | |
936 | ||
937 | for (i = 0; i < NR_IRQS; i++) | |
938 | get_irq_desc(i)->status |= IRQ_NOREQUEST; | |
939 | } | |
940 | ||
941 | /* We need to create the radix trees late */ | |
942 | static int irq_late_init(void) | |
943 | { | |
944 | struct irq_host *h; | |
945 | unsigned long flags; | |
946 | ||
8ec8f2e8 | 947 | irq_radix_wrlock(&flags); |
0ebfff14 BH |
948 | list_for_each_entry(h, &irq_hosts, link) { |
949 | if (h->revmap_type == IRQ_HOST_MAP_TREE) | |
950 | INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC); | |
951 | } | |
8ec8f2e8 | 952 | irq_radix_wrunlock(flags); |
0ebfff14 BH |
953 | |
954 | return 0; | |
955 | } | |
956 | arch_initcall(irq_late_init); | |
957 | ||
958 | #endif /* CONFIG_PPC_MERGE */ | |
1da177e4 | 959 | |
c6622f63 | 960 | #ifdef CONFIG_PPC64 |
1da177e4 LT |
961 | static int __init setup_noirqdistrib(char *str) |
962 | { | |
963 | distribute_irqs = 0; | |
964 | return 1; | |
965 | } | |
966 | ||
967 | __setup("noirqdistrib", setup_noirqdistrib); | |
756e7104 | 968 | #endif /* CONFIG_PPC64 */ |