projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| ff2e6d7e | 2 | * This file contains the power_save function for 970-family CPUs. |
| 1da177e4 LT |
3 | * |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * as published by the Free Software Foundation; either version | |
| 7 | * 2 of the License, or (at your option) any later version. | |
| 8 | */ | |
| 9 | ||
| 1da177e4 LT |
10 | #include <linux/threads.h> |
| 11 | #include <asm/processor.h> | |
| 12 | #include <asm/page.h> | |
| 13 | #include <asm/cputable.h> | |
| 14 | #include <asm/thread_info.h> | |
| 15 | #include <asm/ppc_asm.h> | |
| 0013a854 | 16 | #include <asm/asm-offsets.h> |
| 1da177e4 LT |
17 | |
| 18 | #undef DEBUG | |
| 19 | ||
| 20 | .text | |
| 21 | ||
| 1da177e4 LT |
22 | _GLOBAL(power4_idle) |
| 23 | BEGIN_FTR_SECTION | |
| 24 | blr | |
| 25 | END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP) | |
| 1da177e4 | 26 | /* Now check if user or arch enabled NAP mode */ |
| e58c3495 DG |
27 | LOAD_REG_ADDRBASE(r3,powersave_nap) |
| 28 | lwz r4,ADDROFF(powersave_nap)(r3) | |
| 1da177e4 LT |
29 | cmpwi 0,r4,0 |
| 30 | beqlr | |
| 31 | ||
| dc1c1ca3 | 32 | /* Go to NAP now */ |
| d04c56f7 PM |
33 | mfmsr r7 |
| 34 | rldicl r0,r7,48,1 | |
| 35 | rotldi r0,r0,16 | |
| 36 | mtmsrd r0,1 /* hard-disable interrupts */ | |
| 37 | li r0,1 | |
| 38 | stb r0,PACASOFTIRQEN(r13) /* we'll hard-enable shortly */ | |
| 39 | stb r0,PACAHARDIRQEN(r13) | |
| 1da177e4 LT |
40 | BEGIN_FTR_SECTION |
| 41 | DSSALL | |
| 42 | sync | |
| 43 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
| f39224a8 PM |
44 | clrrdi r9,r1,THREAD_SHIFT /* current thread_info */ |
| 45 | ld r8,TI_LOCAL_FLAGS(r9) /* set napping bit */ | |
| 46 | ori r8,r8,_TLF_NAPPING /* so when we take an exception */ | |
| 47 | std r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */ | |
| ff2e6d7e | 48 | ori r7,r7,MSR_EE |
| 1da177e4 | 49 | oris r7,r7,MSR_POW@h |
| f39224a8 | 50 | 1: sync |
| 1da177e4 LT |
51 | isync |
| 52 | mtmsrd r7 | |
| 53 | isync | |
| f39224a8 PM |
54 | b 1b |
| 55 | ||
| d9333afd JB |
56 | _GLOBAL(power4_cpu_offline_powersave) |
| 57 | /* Go to NAP now */ | |
| 58 | mfmsr r7 | |
| 59 | rldicl r0,r7,48,1 | |
| 60 | rotldi r0,r0,16 | |
| 61 | mtmsrd r0,1 /* hard-disable interrupts */ | |
| 62 | li r0,1 | |
| 63 | li r6,0 | |
| 64 | stb r0,PACAHARDIRQEN(r13) /* we'll hard-enable shortly */ | |
| 65 | stb r6,PACASOFTIRQEN(r13) /* soft-disable irqs */ | |
| 66 | BEGIN_FTR_SECTION | |
| 67 | DSSALL | |
| 68 | sync | |
| 69 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
| 70 | ori r7,r7,MSR_EE | |
| 71 | oris r7,r7,MSR_POW@h | |
| 72 | sync | |
| 73 | isync | |
| 74 | mtmsrd r7 | |
| 75 | isync | |
| 76 | blr |