[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / hw_breakpoint.c

/*
 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
 * using the CPU's debug registers. Derived from
 * "arch/x86/kernel/hw_breakpoint.c"
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright 2010 IBM Corporation
 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
 *
 */

#include <linux/hw_breakpoint.h>
#include <linux/notifier.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/smp.h>

#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/sstep.h>
#include <asm/uaccess.h>

/*
 * Stores the breakpoints currently in use on each breakpoint address
 * register for every cpu
 */
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);

/*
 * Install a perf counter breakpoint.
 *
 * We seek a free debug address register and use it for this
 * breakpoint.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
int arch_install_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	struct perf_event **slot = &__get_cpu_var(bp_per_reg);

	*slot = bp;

	/*
	 * Do not install DABR values if the instruction must be single-stepped.
	 * If so, DABR will be populated in single_step_dabr_instruction().
	 */
	if (current->thread.last_hit_ubp != bp)
		set_dabr(info->address | info->type | DABR_TRANSLATION);

	return 0;
}

/*
 * Uninstall the breakpoint contained in the given counter.
 *
 * First we search the debug address register it uses and then we disable
 * it.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct perf_event **slot = &__get_cpu_var(bp_per_reg);

	if (*slot != bp) {
		WARN_ONCE(1, "Can't find the breakpoint");
		return;
	}

	*slot = NULL;
	set_dabr(0);
}

/*
 * Perform cleanup of arch-specific counters during unregistration
 * of the perf-event
 */
void arch_unregister_hw_breakpoint(struct perf_event *bp)
{
	/*
	 * If the breakpoint is unregistered between a hw_breakpoint_handler()
	 * and the single_step_dabr_instruction(), then cleanup the breakpoint
	 * restoration variables to prevent dangling pointers.
	 */
	if (bp->ctx->task)
		bp->ctx->task->thread.last_hit_ubp = NULL;
}

/*
 * Check for virtual address in kernel space.
 */
int arch_check_bp_in_kernelspace(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	return is_kernel_addr(info->address);
}

int arch_bp_generic_fields(int type, int *gen_bp_type)
{
	switch (type) {
	case DABR_DATA_READ:
		*gen_bp_type = HW_BREAKPOINT_R;
		break;
	case DABR_DATA_WRITE:
		*gen_bp_type = HW_BREAKPOINT_W;
		break;
	case (DABR_DATA_WRITE | DABR_DATA_READ):
		*gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

/*
 * Validate the arch-specific HW Breakpoint register settings
 */
int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
	int ret = -EINVAL;
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	if (!bp)
		return ret;

	switch (bp->attr.bp_type) {
	case HW_BREAKPOINT_R:
		info->type = DABR_DATA_READ;
		break;
	case HW_BREAKPOINT_W:
		info->type = DABR_DATA_WRITE;
		break;
	case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
		info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
		break;
	default:
		return ret;
	}

	info->address = bp->attr.bp_addr;
	info->len = bp->attr.bp_len;

	/*
	 * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
	 * and breakpoint addresses are aligned to nearest double-word
	 * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
	 * 'symbolsize' should satisfy the check below.
	 */
	if (info->len >
	    (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
		return -EINVAL;
	return 0;
}

/*
 * Restores the breakpoint on the debug registers.
 * Invoke this function if it is known that the execution context is
 * about to change to cause loss of MSR_SE settings.
 */
void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
{
	struct arch_hw_breakpoint *info;

	if (likely(!tsk->thread.last_hit_ubp))
		return;

	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	regs->msr &= ~MSR_SE;
	set_dabr(info->address | info->type | DABR_TRANSLATION);
	tsk->thread.last_hit_ubp = NULL;
}

/*
 * Handle debug exception notifications.
 */
int __kprobes hw_breakpoint_handler(struct die_args *args)
{
	int rc = NOTIFY_STOP;
	struct perf_event *bp;
	struct pt_regs *regs = args->regs;
	int stepped = 1;
	struct arch_hw_breakpoint *info;
	unsigned int instr;
	unsigned long dar = regs->dar;

	/* Disable breakpoints during exception handling */
	set_dabr(0);

	/*
	 * The counter may be concurrently released but that can only
	 * occur from a call_rcu() path. We can then safely fetch
	 * the breakpoint, use its callback, touch its counter
	 * while we are in an rcu_read_lock() path.
	 */
	rcu_read_lock();

	bp = __get_cpu_var(bp_per_reg);
	if (!bp)
		goto out;
	info = counter_arch_bp(bp);

	/*
	 * Return early after invoking user-callback function without restoring
	 * DABR if the breakpoint is from ptrace which always operates in
	 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	 * generated in do_dabr().
	 */
	if (bp->overflow_handler == ptrace_triggered) {
		perf_bp_event(bp, regs);
		rc = NOTIFY_DONE;
		goto out;
	}

	/*
	 * Verify if dar lies within the address range occupied by the symbol
	 * being watched to filter extraneous exceptions.  If it doesn't,
	 * we still need to single-step the instruction, but we don't
	 * generate an event.
	 */
	info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
			(dar - bp->attr.bp_addr < bp->attr.bp_len));

	/* Do not emulate user-space instructions, instead single-step them */
	if (user_mode(regs)) {
		bp->ctx->task->thread.last_hit_ubp = bp;
		regs->msr |= MSR_SE;
		goto out;
	}

	stepped = 0;
	instr = 0;
	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
		stepped = emulate_step(regs, instr);

	/*
	 * emulate_step() could not execute it. We've failed in reliably
	 * handling the hw-breakpoint. Unregister it and throw a warning
	 * message to let the user know about it.
	 */
	if (!stepped) {
		WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
			"0x%lx will be disabled.", info->address);
		perf_event_disable(bp);
		goto out;
	}
	/*
	 * As a policy, the callback is invoked in a 'trigger-after-execute'
	 * fashion
	 */
	if (!info->extraneous_interrupt)
		perf_bp_event(bp, regs);

	set_dabr(info->address | info->type | DABR_TRANSLATION);
out:
	rcu_read_unlock();
	return rc;
}

/*
 * Handle single-step exceptions following a DABR hit.
 */
int __kprobes single_step_dabr_instruction(struct die_args *args)
{
	struct pt_regs *regs = args->regs;
	struct perf_event *bp = NULL;
	struct arch_hw_breakpoint *bp_info;

	bp = current->thread.last_hit_ubp;
	/*
	 * Check if we are single-stepping as a result of a
	 * previous HW Breakpoint exception
	 */
	if (!bp)
		return NOTIFY_DONE;

	bp_info = counter_arch_bp(bp);

	/*
	 * We shall invoke the user-defined callback function in the single
	 * stepping handler to confirm to 'trigger-after-execute' semantics
	 */
	if (!bp_info->extraneous_interrupt)
		perf_bp_event(bp, regs);

	set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
	current->thread.last_hit_ubp = NULL;

	/*
	 * If the process was being single-stepped by ptrace, let the
	 * other single-step actions occur (e.g. generate SIGTRAP).
	 */
	if (test_thread_flag(TIF_SINGLESTEP))
		return NOTIFY_DONE;

	return NOTIFY_STOP;
}

/*
 * Handle debug exception notifications.
 */
int __kprobes hw_breakpoint_exceptions_notify(
		struct notifier_block *unused, unsigned long val, void *data)
{
	int ret = NOTIFY_DONE;

	switch (val) {
	case DIE_DABR_MATCH:
		ret = hw_breakpoint_handler(data);
		break;
	case DIE_SSTEP:
		ret = single_step_dabr_instruction(data);
		break;
	}

	return ret;
}

/*
 * Release the user breakpoints used by ptrace
 */
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	struct thread_struct *t = &tsk->thread;

	unregister_hw_breakpoint(t->ptrace_bps[0]);
	t->ptrace_bps[0] = NULL;
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
	/* TODO */
}
Commit	Line	Data
5aae8a53 P	1	/*
	2	* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
	3	* using the CPU's debug registers. Derived from
	4	* "arch/x86/kernel/hw_breakpoint.c"
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19	*
	20	* Copyright 2010 IBM Corporation
	21	* Author: K.Prasad <prasad@linux.vnet.ibm.com>
	22	*
	23	*/
	24
	25	#include <linux/hw_breakpoint.h>
	26	#include <linux/notifier.h>
	27	#include <linux/kprobes.h>
	28	#include <linux/percpu.h>
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/sched.h>
	32	#include <linux/init.h>
	33	#include <linux/smp.h>
	34
	35	#include <asm/hw_breakpoint.h>
	36	#include <asm/processor.h>
	37	#include <asm/sstep.h>
	38	#include <asm/uaccess.h>
	39
	40	/*
	41	* Stores the breakpoints currently in use on each breakpoint address
	42	* register for every cpu
	43	*/
	44	static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
	45
	46	/*
	47	* Install a perf counter breakpoint.
	48	*
	49	* We seek a free debug address register and use it for this
	50	* breakpoint.
	51	*
	52	* Atomic: we hold the counter->ctx->lock and we only handle variables
	53	* and registers local to this cpu.
	54	*/
	55	int arch_install_hw_breakpoint(struct perf_event *bp)
	56	{
	57	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	58	struct perf_event **slot = &__get_cpu_var(bp_per_reg);
	59
	60	*slot = bp;
	61
	62	/*
	63	* Do not install DABR values if the instruction must be single-stepped.
	64	* If so, DABR will be populated in single_step_dabr_instruction().
65	*/
66	if (current->thread.last_hit_ubp != bp)
67	set_dabr(info->address \| info->type \| DABR_TRANSLATION);
68
69	return 0;
70	}
71
72	/*
73	* Uninstall the breakpoint contained in the given counter.
74	*
75	* First we search the debug address register it uses and then we disable
76	* it.
77	*
78	* Atomic: we hold the counter->ctx->lock and we only handle variables
79	* and registers local to this cpu.
80	*/
81	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
82	{
83	struct perf_event **slot = &__get_cpu_var(bp_per_reg);
84
85	if (*slot != bp) {
86	WARN_ONCE(1, "Can't find the breakpoint");
87	return;
88	}
89
90	*slot = NULL;
91	set_dabr(0);
92	}
93
94	/*
95	* Perform cleanup of arch-specific counters during unregistration
96	* of the perf-event
97	*/
98	void arch_unregister_hw_breakpoint(struct perf_event *bp)
99	{
100	/*
101	* If the breakpoint is unregistered between a hw_breakpoint_handler()
102	* and the single_step_dabr_instruction(), then cleanup the breakpoint
103	* restoration variables to prevent dangling pointers.
104	*/
105	if (bp->ctx->task)
106	bp->ctx->task->thread.last_hit_ubp = NULL;
107	}
108
109	/*
110	* Check for virtual address in kernel space.
111	*/
112	int arch_check_bp_in_kernelspace(struct perf_event *bp)
113	{
114	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
115
116	return is_kernel_addr(info->address);
117	}
118
119	int arch_bp_generic_fields(int type, int *gen_bp_type)
120	{
121	switch (type) {
122	case DABR_DATA_READ:
123	*gen_bp_type = HW_BREAKPOINT_R;
124	break;
125	case DABR_DATA_WRITE:
126	*gen_bp_type = HW_BREAKPOINT_W;
127	break;
128	case (DABR_DATA_WRITE \| DABR_DATA_READ):
129	*gen_bp_type = (HW_BREAKPOINT_W \| HW_BREAKPOINT_R);
130	break;
131	default:
132	return -EINVAL;
133	}
134	return 0;
135	}
136
137	/*
138	* Validate the arch-specific HW Breakpoint register settings
139	*/
140	int arch_validate_hwbkpt_settings(struct perf_event *bp)
141	{
142	int ret = -EINVAL;
143	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
144
145	if (!bp)
146	return ret;
147
148	switch (bp->attr.bp_type) {
149	case HW_BREAKPOINT_R:
150	info->type = DABR_DATA_READ;
151	break;
152	case HW_BREAKPOINT_W:
153	info->type = DABR_DATA_WRITE;
154	break;
155	case HW_BREAKPOINT_R \| HW_BREAKPOINT_W:
156	info->type = (DABR_DATA_READ \| DABR_DATA_WRITE);
157	break;
158	default:
159	return ret;
160	}
161
162	info->address = bp->attr.bp_addr;
163	info->len = bp->attr.bp_len;
164
165	/*
166	* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
167	* and breakpoint addresses are aligned to nearest double-word
168	* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
169	* 'symbolsize' should satisfy the check below.
170	*/
171	if (info->len >
172	(HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
173	return -EINVAL;
174	return 0;
175	}
176
06532a67 P	177	/*
	178	* Restores the breakpoint on the debug registers.
	179	* Invoke this function if it is known that the execution context is
	180	* about to change to cause loss of MSR_SE settings.
	181	*/
	182	void thread_change_pc(struct task_struct tsk, struct pt_regs regs)
	183	{
	184	struct arch_hw_breakpoint *info;
	185
	186	if (likely(!tsk->thread.last_hit_ubp))
	187	return;
	188
	189	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	190	regs->msr &= ~MSR_SE;
	191	set_dabr(info->address \| info->type \| DABR_TRANSLATION);
	192	tsk->thread.last_hit_ubp = NULL;
	193	}
	194
5aae8a53 P	195	/*
	196	* Handle debug exception notifications.
	197	*/
	198	int __kprobes hw_breakpoint_handler(struct die_args *args)
	199	{
5aae8a53 P	200	int rc = NOTIFY_STOP;
	201	struct perf_event *bp;
	202	struct pt_regs *regs = args->regs;
	203	int stepped = 1;
	204	struct arch_hw_breakpoint *info;
	205	unsigned int instr;
e3e94084	206	unsigned long dar = regs->dar;
5aae8a53 P	207
	208	/* Disable breakpoints during exception handling */
	209	set_dabr(0);
574cb248	210
5aae8a53 P	211	/*
	212	* The counter may be concurrently released but that can only
	213	* occur from a call_rcu() path. We can then safely fetch
	214	* the breakpoint, use its callback, touch its counter
	215	* while we are in an rcu_read_lock() path.
	216	*/
	217	rcu_read_lock();
	218
	219	bp = __get_cpu_var(bp_per_reg);
	220	if (!bp)
	221	goto out;
	222	info = counter_arch_bp(bp);
5aae8a53 P	223
	224	/*
	225	* Return early after invoking user-callback function without restoring
	226	* DABR if the breakpoint is from ptrace which always operates in
	227	* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	228	* generated in do_dabr().
	229	*/
574cb248	230	if (bp->overflow_handler == ptrace_triggered) {
5aae8a53 P	231	perf_bp_event(bp, regs);
	232	rc = NOTIFY_DONE;
	233	goto out;
	234	}
	235
e3e94084 P	236	/*
e3e94084 P	237	* Verify if dar lies within the address range occupied by the symbol
574cb248 PM	238	* being watched to filter extraneous exceptions. If it doesn't,
	239	* we still need to single-step the instruction, but we don't
	240	* generate an event.
e3e94084	241	*/
574cb248 PM	242	info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
574cb248 PM	243	(dar - bp->attr.bp_addr < bp->attr.bp_len));
e3e94084	244
5aae8a53 P	245	/* Do not emulate user-space instructions, instead single-step them */
	246	if (user_mode(regs)) {
	247	bp->ctx->task->thread.last_hit_ubp = bp;
	248	regs->msr \|= MSR_SE;
	249	goto out;
	250	}
	251
	252	stepped = 0;
	253	instr = 0;
	254	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
	255	stepped = emulate_step(regs, instr);
	256
	257	/*
	258	* emulate_step() could not execute it. We've failed in reliably
	259	* handling the hw-breakpoint. Unregister it and throw a warning
	260	* message to let the user know about it.
	261	*/
	262	if (!stepped) {
	263	WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
	264	"0x%lx will be disabled.", info->address);
	265	perf_event_disable(bp);
	266	goto out;
	267	}
	268	/*
	269	* As a policy, the callback is invoked in a 'trigger-after-execute'
	270	* fashion
	271	*/
e3e94084 P	272	if (!info->extraneous_interrupt)
e3e94084 P	273	perf_bp_event(bp, regs);
5aae8a53 P	274
	275	set_dabr(info->address \| info->type \| DABR_TRANSLATION);
	276	out:
	277	rcu_read_unlock();
	278	return rc;
	279	}
	280
	281	/*
	282	* Handle single-step exceptions following a DABR hit.
	283	*/
	284	int __kprobes single_step_dabr_instruction(struct die_args *args)
	285	{
	286	struct pt_regs *regs = args->regs;
	287	struct perf_event *bp = NULL;
	288	struct arch_hw_breakpoint *bp_info;
	289
	290	bp = current->thread.last_hit_ubp;
	291	/*
	292	* Check if we are single-stepping as a result of a
	293	* previous HW Breakpoint exception
	294	*/
	295	if (!bp)
	296	return NOTIFY_DONE;
	297
	298	bp_info = counter_arch_bp(bp);
	299
	300	/*
	301	* We shall invoke the user-defined callback function in the single
	302	* stepping handler to confirm to 'trigger-after-execute' semantics
	303	*/
e3e94084 P	304	if (!bp_info->extraneous_interrupt)
e3e94084 P	305	perf_bp_event(bp, regs);
5aae8a53	306
76b0f133 PM	307	set_dabr(bp_info->address \| bp_info->type \| DABR_TRANSLATION);
	308	current->thread.last_hit_ubp = NULL;
	309
5aae8a53	310	/*
76b0f133 PM	311	* If the process was being single-stepped by ptrace, let the
76b0f133 PM	312	* other single-step actions occur (e.g. generate SIGTRAP).
5aae8a53	313	*/
76b0f133 PM	314	if (test_thread_flag(TIF_SINGLESTEP))
76b0f133 PM	315	return NOTIFY_DONE;
5aae8a53	316
5aae8a53 P	317	return NOTIFY_STOP;
	318	}
	319
	320	/*
	321	* Handle debug exception notifications.
	322	*/
	323	int __kprobes hw_breakpoint_exceptions_notify(
	324	struct notifier_block unused, unsigned long val, void data)
	325	{
	326	int ret = NOTIFY_DONE;
	327
	328	switch (val) {
	329	case DIE_DABR_MATCH:
	330	ret = hw_breakpoint_handler(data);
	331	break;
	332	case DIE_SSTEP:
	333	ret = single_step_dabr_instruction(data);
	334	break;
	335	}
	336
	337	return ret;
	338	}
	339
	340	/*
	341	* Release the user breakpoints used by ptrace
	342	*/
	343	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
	344	{
	345	struct thread_struct *t = &tsk->thread;
	346
	347	unregister_hw_breakpoint(t->ptrace_bps[0]);
	348	t->ptrace_bps[0] = NULL;
	349	}
	350
	351	void hw_breakpoint_pmu_read(struct perf_event *bp)
	352	{
	353	/* TODO */
	354	}