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Merge ../powerpc-merge
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / head_64.S
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14cf11af 1/*
14cf11af
PM		 2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24#include <linux/config.h>
25#include <linux/threads.h>
b5bbeb23 26#include <asm/reg.h>
14cf11af
PM		 27#include <asm/page.h>
28#include <asm/mmu.h>
14cf11af
PM		 29#include <asm/ppc_asm.h>
30#include <asm/asm-offsets.h>
31#include <asm/bug.h>
32#include <asm/cputable.h>
33#include <asm/setup.h>
34#include <asm/hvcall.h>
c43a55ff 35#include <asm/iseries/lpar_map.h>
6cb7bfeb 36#include <asm/thread_info.h>
14cf11af
PM		 37
38#ifdef CONFIG_PPC_ISERIES
39#define DO_SOFT_DISABLE
40#endif
41
42/*
43 * We layout physical memory as follows:
44 * 0x0000 - 0x00ff : Secondary processor spin code
45 * 0x0100 - 0x2fff : pSeries Interrupt prologs
46 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
47 * 0x6000 - 0x6fff : Initial (CPU0) segment table
48 * 0x7000 - 0x7fff : FWNMI data area
49 * 0x8000 - : Early init and support code
50 */
51
52/*
53 * SPRG Usage
54 *
55 * Register Definition
56 *
57 * SPRG0 reserved for hypervisor
58 * SPRG1 temp - used to save gpr
59 * SPRG2 temp - used to save gpr
60 * SPRG3 virt addr of paca
61 */
62
63/*
64 * Entering into this code we make the following assumptions:
65 * For pSeries:
66 * 1. The MMU is off & open firmware is running in real mode.
67 * 2. The kernel is entered at __start
68 *
69 * For iSeries:
70 * 1. The MMU is on (as it always is for iSeries)
71 * 2. The kernel is entered at system_reset_iSeries
72 */
73
74 .text
75 .globl _stext
76_stext:
77#ifdef CONFIG_PPC_MULTIPLATFORM
78_GLOBAL(__start)
79 /* NOP this out unconditionally */
80BEGIN_FTR_SECTION
b85a046a 81 b .__start_initialization_multiplatform
14cf11af
PM		 82END_FTR_SECTION(0, 1)
83#endif /* CONFIG_PPC_MULTIPLATFORM */
84
85 /* Catch branch to 0 in real mode */
86 trap
87
88#ifdef CONFIG_PPC_ISERIES
89 /*
90 * At offset 0x20, there is a pointer to iSeries LPAR data.
91 * This is required by the hypervisor
92 */
93 . = 0x20
94 .llong hvReleaseData-KERNELBASE
95
96 /*
97 * At offset 0x28 and 0x30 are offsets to the mschunks_map
98 * array (used by the iSeries LPAR debugger to do translation
99 * between physical addresses and absolute addresses) and
100 * to the pidhash table (also used by the debugger)
101 */
102 .llong mschunks_map-KERNELBASE
103 .llong 0 /* pidhash-KERNELBASE SFRXXX */
104
105 /* Offset 0x38 - Pointer to start of embedded System.map */
106 .globl embedded_sysmap_start
107embedded_sysmap_start:
108 .llong 0
109 /* Offset 0x40 - Pointer to end of embedded System.map */
110 .globl embedded_sysmap_end
111embedded_sysmap_end:
112 .llong 0
113
114#endif /* CONFIG_PPC_ISERIES */
115
116 /* Secondary processors spin on this value until it goes to 1. */
117 .globl __secondary_hold_spinloop
118__secondary_hold_spinloop:
119 .llong 0x0
120
121 /* Secondary processors write this value with their cpu # */
122 /* after they enter the spin loop immediately below. */
123 .globl __secondary_hold_acknowledge
124__secondary_hold_acknowledge:
125 .llong 0x0
126
127 . = 0x60
128/*
129 * The following code is used on pSeries to hold secondary processors
130 * in a spin loop after they have been freed from OpenFirmware, but
131 * before the bulk of the kernel has been relocated. This code
132 * is relocated to physical address 0x60 before prom_init is run.
133 * All of it must fit below the first exception vector at 0x100.
134 */
135_GLOBAL(__secondary_hold)
136 mfmsr r24
137 ori r24,r24,MSR_RI
138 mtmsrd r24 /* RI on */
139
f1870f77 140 /* Grab our physical cpu number */
14cf11af
PM		 141 mr r24,r3
142
143 /* Tell the master cpu we're here */
144 /* Relocation is off & we are located at an address less */
145 /* than 0x100, so only need to grab low order offset. */
146 std r24,__secondary_hold_acknowledge@l(0)
147 sync
148
149 /* All secondary cpus wait here until told to start. */
150100: ld r4,__secondary_hold_spinloop@l(0)
151 cmpdi 0,r4,1
152 bne 100b
153
f1870f77 154#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
e58c3495 155 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
758438a7 156 mtctr r4
14cf11af 157 mr r3,r24
758438a7 158 bctr
14cf11af
PM		 159#else
160 BUG_OPCODE
161#endif
14cf11af
PM		 162
163/* This value is used to mark exception frames on the stack. */
164 .section ".toc","aw"
165exception_marker:
166 .tc ID_72656773_68657265[TC],0x7265677368657265
167 .text
168
169/*
170 * The following macros define the code that appears as
171 * the prologue to each of the exception handlers. They
172 * are split into two parts to allow a single kernel binary
173 * to be used for pSeries and iSeries.
174 * LOL. One day... - paulus
175 */
176
177/*
178 * We make as much of the exception code common between native
179 * exception handlers (including pSeries LPAR) and iSeries LPAR
180 * implementations as possible.
181 */
182
183/*
184 * This is the start of the interrupt handlers for pSeries
185 * This code runs with relocation off.
186 */
187#define EX_R9 0
188#define EX_R10 8
189#define EX_R11 16
190#define EX_R12 24
191#define EX_R13 32
192#define EX_SRR0 40
14cf11af 193#define EX_DAR 48
14cf11af
PM		 194#define EX_DSISR 56
195#define EX_CCR 60
3c726f8d
BH		 196#define EX_R3 64
197#define EX_LR 72
14cf11af 198
758438a7 199/*
e58c3495
DG		 200 * We're short on space and time in the exception prolog, so we can't
201 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
202 * low halfword of the address, but for Kdump we need the whole low
203 * word.
758438a7
ME		 204 */
205#ifdef CONFIG_CRASH_DUMP
206#define LOAD_HANDLER(reg, label) \
207 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
208 ori reg,reg,(label)@l; /* .. and the rest */
209#else
210#define LOAD_HANDLER(reg, label) \
211 ori reg,reg,(label)@l; /* virt addr of handler ... */
212#endif
213
14cf11af 214#define EXCEPTION_PROLOG_PSERIES(area, label) \
b5bbeb23 215 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
14cf11af
PM		 216 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
217 std r10,area+EX_R10(r13); \
218 std r11,area+EX_R11(r13); \
219 std r12,area+EX_R12(r13); \
b5bbeb23 220 mfspr r9,SPRN_SPRG1; \
14cf11af
PM		 221 std r9,area+EX_R13(r13); \
222 mfcr r9; \
223 clrrdi r12,r13,32; /* get high part of &label */ \
224 mfmsr r10; \
b5bbeb23 225 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
758438a7 226 LOAD_HANDLER(r12,label) \
14cf11af 227 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
b5bbeb23
PM		 228 mtspr SPRN_SRR0,r12; \
229 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
230 mtspr SPRN_SRR1,r10; \
14cf11af
PM		 231 rfid; \
232 b . /* prevent speculative execution */
233
234/*
235 * This is the start of the interrupt handlers for iSeries
236 * This code runs with relocation on.
237 */
238#define EXCEPTION_PROLOG_ISERIES_1(area) \
b5bbeb23 239 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
14cf11af
PM		 240 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
241 std r10,area+EX_R10(r13); \
242 std r11,area+EX_R11(r13); \
243 std r12,area+EX_R12(r13); \
b5bbeb23 244 mfspr r9,SPRN_SPRG1; \
14cf11af
PM		 245 std r9,area+EX_R13(r13); \
246 mfcr r9
247
248#define EXCEPTION_PROLOG_ISERIES_2 \
249 mfmsr r10; \
3356bb9f
DG		 250 ld r12,PACALPPACAPTR(r13); \
251 ld r11,LPPACASRR0(r12); \
252 ld r12,LPPACASRR1(r12); \
14cf11af
PM		 253 ori r10,r10,MSR_RI; \
254 mtmsrd r10,1
255
256/*
257 * The common exception prolog is used for all except a few exceptions
258 * such as a segment miss on a kernel address. We have to be prepared
259 * to take another exception from the point where we first touch the
260 * kernel stack onwards.
261 *
262 * On entry r13 points to the paca, r9-r13 are saved in the paca,
263 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
264 * SRR1, and relocation is on.
265 */
266#define EXCEPTION_PROLOG_COMMON(n, area) \
267 andi. r10,r12,MSR_PR; /* See if coming from user */ \
268 mr r10,r1; /* Save r1 */ \
269 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
270 beq- 1f; \
271 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
2721: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
273 bge- cr1,bad_stack; /* abort if it is */ \
274 std r9,_CCR(r1); /* save CR in stackframe */ \
275 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
276 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
277 std r10,0(r1); /* make stack chain pointer */ \
278 std r0,GPR0(r1); /* save r0 in stackframe */ \
279 std r10,GPR1(r1); /* save r1 in stackframe */ \
280 std r2,GPR2(r1); /* save r2 in stackframe */ \
281 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
282 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
283 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
284 ld r10,area+EX_R10(r13); \
285 std r9,GPR9(r1); \
286 std r10,GPR10(r1); \
287 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
288 ld r10,area+EX_R12(r13); \
289 ld r11,area+EX_R13(r13); \
290 std r9,GPR11(r1); \
291 std r10,GPR12(r1); \
292 std r11,GPR13(r1); \
293 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
294 mflr r9; /* save LR in stackframe */ \
295 std r9,_LINK(r1); \
296 mfctr r10; /* save CTR in stackframe */ \
297 std r10,_CTR(r1); \
b5bbeb23 298 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
14cf11af
PM		 299 std r11,_XER(r1); \
300 li r9,(n)+1; \
301 std r9,_TRAP(r1); /* set trap number */ \
302 li r10,0; \
303 ld r11,exception_marker@toc(r2); \
304 std r10,RESULT(r1); /* clear regs->result */ \
305 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
306
307/*
308 * Exception vectors.
309 */
310#define STD_EXCEPTION_PSERIES(n, label) \
311 . = n; \
312 .globl label##_pSeries; \
313label##_pSeries: \
314 HMT_MEDIUM; \
b5bbeb23 315 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 316 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
317
318#define STD_EXCEPTION_ISERIES(n, label, area) \
319 .globl label##_iSeries; \
320label##_iSeries: \
321 HMT_MEDIUM; \
b5bbeb23 322 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 323 EXCEPTION_PROLOG_ISERIES_1(area); \
324 EXCEPTION_PROLOG_ISERIES_2; \
325 b label##_common
326
327#define MASKABLE_EXCEPTION_ISERIES(n, label) \
328 .globl label##_iSeries; \
329label##_iSeries: \
330 HMT_MEDIUM; \
b5bbeb23 331 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 332 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
333 lbz r10,PACAPROCENABLED(r13); \
334 cmpwi 0,r10,0; \
335 beq- label##_iSeries_masked; \
336 EXCEPTION_PROLOG_ISERIES_2; \
337 b label##_common; \
338
339#ifdef DO_SOFT_DISABLE
340#define DISABLE_INTS \
341 lbz r10,PACAPROCENABLED(r13); \
342 li r11,0; \
343 std r10,SOFTE(r1); \
344 mfmsr r10; \
345 stb r11,PACAPROCENABLED(r13); \
346 ori r10,r10,MSR_EE; \
347 mtmsrd r10,1
348
349#define ENABLE_INTS \
350 lbz r10,PACAPROCENABLED(r13); \
351 mfmsr r11; \
352 std r10,SOFTE(r1); \
353 ori r11,r11,MSR_EE; \
354 mtmsrd r11,1
355
356#else /* hard enable/disable interrupts */
357#define DISABLE_INTS
358
359#define ENABLE_INTS \
360 ld r12,_MSR(r1); \
361 mfmsr r11; \
362 rlwimi r11,r12,0,MSR_EE; \
363 mtmsrd r11,1
364
365#endif
366
367#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
368 .align 7; \
369 .globl label##_common; \
370label##_common: \
371 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
372 DISABLE_INTS; \
373 bl .save_nvgprs; \
374 addi r3,r1,STACK_FRAME_OVERHEAD; \
375 bl hdlr; \
376 b .ret_from_except
377
378#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
379 .align 7; \
380 .globl label##_common; \
381label##_common: \
382 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
383 DISABLE_INTS; \
cb2c9b27 384 bl .ppc64_runlatch_on; \
14cf11af
PM		 385 addi r3,r1,STACK_FRAME_OVERHEAD; \
386 bl hdlr; \
387 b .ret_from_except_lite
388
389/*
390 * Start of pSeries system interrupt routines
391 */
392 . = 0x100
393 .globl __start_interrupts
394__start_interrupts:
395
396 STD_EXCEPTION_PSERIES(0x100, system_reset)
397
398 . = 0x200
399_machine_check_pSeries:
400 HMT_MEDIUM
b5bbeb23 401 mtspr SPRN_SPRG1,r13 /* save r13 */
14cf11af
PM		 402 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
403
404 . = 0x300
405 .globl data_access_pSeries
406data_access_pSeries:
407 HMT_MEDIUM
b5bbeb23 408 mtspr SPRN_SPRG1,r13
14cf11af 409BEGIN_FTR_SECTION
b5bbeb23
PM		 410 mtspr SPRN_SPRG2,r12
411 mfspr r13,SPRN_DAR
412 mfspr r12,SPRN_DSISR
14cf11af
PM		 413 srdi r13,r13,60
414 rlwimi r13,r12,16,0x20
415 mfcr r12
416 cmpwi r13,0x2c
417 beq .do_stab_bolted_pSeries
418 mtcrf 0x80,r12
b5bbeb23 419 mfspr r12,SPRN_SPRG2
14cf11af
PM		 420END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
421 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
422
423 . = 0x380
424 .globl data_access_slb_pSeries
425data_access_slb_pSeries:
426 HMT_MEDIUM
b5bbeb23 427 mtspr SPRN_SPRG1,r13
b5bbeb23 428 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
3c726f8d
BH		 429 std r3,PACA_EXSLB+EX_R3(r13)
430 mfspr r3,SPRN_DAR
14cf11af 431 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
3c726f8d
BH		 432 mfcr r9
433#ifdef __DISABLED__
434 /* Keep that around for when we re-implement dynamic VSIDs */
435 cmpdi r3,0
436 bge slb_miss_user_pseries
437#endif /* __DISABLED__ */
14cf11af
PM		 438 std r10,PACA_EXSLB+EX_R10(r13)
439 std r11,PACA_EXSLB+EX_R11(r13)
440 std r12,PACA_EXSLB+EX_R12(r13)
3c726f8d
BH		 441 mfspr r10,SPRN_SPRG1
442 std r10,PACA_EXSLB+EX_R13(r13)
b5bbeb23 443 mfspr r12,SPRN_SRR1 /* and SRR1 */
3c726f8d 444 b .slb_miss_realmode /* Rel. branch works in real mode */
14cf11af
PM		 445
446 STD_EXCEPTION_PSERIES(0x400, instruction_access)
447
448 . = 0x480
449 .globl instruction_access_slb_pSeries
450instruction_access_slb_pSeries:
451 HMT_MEDIUM
b5bbeb23 452 mtspr SPRN_SPRG1,r13
b5bbeb23 453 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
3c726f8d
BH		 454 std r3,PACA_EXSLB+EX_R3(r13)
455 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
14cf11af 456 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
3c726f8d
BH		 457 mfcr r9
458#ifdef __DISABLED__
459 /* Keep that around for when we re-implement dynamic VSIDs */
460 cmpdi r3,0
461 bge slb_miss_user_pseries
462#endif /* __DISABLED__ */
14cf11af
PM		 463 std r10,PACA_EXSLB+EX_R10(r13)
464 std r11,PACA_EXSLB+EX_R11(r13)
465 std r12,PACA_EXSLB+EX_R12(r13)
3c726f8d
BH		 466 mfspr r10,SPRN_SPRG1
467 std r10,PACA_EXSLB+EX_R13(r13)
b5bbeb23 468 mfspr r12,SPRN_SRR1 /* and SRR1 */
3c726f8d 469 b .slb_miss_realmode /* Rel. branch works in real mode */
14cf11af
PM		 470
471 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
472 STD_EXCEPTION_PSERIES(0x600, alignment)
473 STD_EXCEPTION_PSERIES(0x700, program_check)
474 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
475 STD_EXCEPTION_PSERIES(0x900, decrementer)
476 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
477 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
478
479 . = 0xc00
480 .globl system_call_pSeries
481system_call_pSeries:
482 HMT_MEDIUM
14cf11af
PM		 483 mr r9,r13
484 mfmsr r10
b5bbeb23
PM		 485 mfspr r13,SPRN_SPRG3
486 mfspr r11,SPRN_SRR0
14cf11af
PM		 487 clrrdi r12,r13,32
488 oris r12,r12,system_call_common@h
489 ori r12,r12,system_call_common@l
b5bbeb23 490 mtspr SPRN_SRR0,r12
14cf11af 491 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
b5bbeb23
PM		 492 mfspr r12,SPRN_SRR1
493 mtspr SPRN_SRR1,r10
14cf11af
PM		 494 rfid
495 b . /* prevent speculative execution */
496
497 STD_EXCEPTION_PSERIES(0xd00, single_step)
498 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
499
500 /* We need to deal with the Altivec unavailable exception
501 * here which is at 0xf20, thus in the middle of the
502 * prolog code of the PerformanceMonitor one. A little
503 * trickery is thus necessary
504 */
505 . = 0xf00
506 b performance_monitor_pSeries
507
508 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
509
510 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
511 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
512
513 . = 0x3000
514
515/*** pSeries interrupt support ***/
516
517 /* moved from 0xf00 */
518 STD_EXCEPTION_PSERIES(., performance_monitor)
519
520 .align 7
521_GLOBAL(do_stab_bolted_pSeries)
522 mtcrf 0x80,r12
b5bbeb23 523 mfspr r12,SPRN_SPRG2
14cf11af
PM		 524 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
525
3c726f8d
BH		 526/*
527 * We have some room here we use that to put
528 * the peries slb miss user trampoline code so it's reasonably
529 * away from slb_miss_user_common to avoid problems with rfid
530 *
531 * This is used for when the SLB miss handler has to go virtual,
532 * which doesn't happen for now anymore but will once we re-implement
533 * dynamic VSIDs for shared page tables
534 */
535#ifdef __DISABLED__
536slb_miss_user_pseries:
537 std r10,PACA_EXGEN+EX_R10(r13)
538 std r11,PACA_EXGEN+EX_R11(r13)
539 std r12,PACA_EXGEN+EX_R12(r13)
540 mfspr r10,SPRG1
541 ld r11,PACA_EXSLB+EX_R9(r13)
542 ld r12,PACA_EXSLB+EX_R3(r13)
543 std r10,PACA_EXGEN+EX_R13(r13)
544 std r11,PACA_EXGEN+EX_R9(r13)
545 std r12,PACA_EXGEN+EX_R3(r13)
546 clrrdi r12,r13,32
547 mfmsr r10
548 mfspr r11,SRR0 /* save SRR0 */
549 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
550 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
551 mtspr SRR0,r12
552 mfspr r12,SRR1 /* and SRR1 */
553 mtspr SRR1,r10
554 rfid
555 b . /* prevent spec. execution */
556#endif /* __DISABLED__ */
557
14cf11af
PM		 558/*
559 * Vectors for the FWNMI option. Share common code.
560 */
b5bbeb23 561 .globl system_reset_fwnmi
8c4f1f29 562 .align 7
14cf11af 563system_reset_fwnmi:
b5bbeb23
PM		 564 HMT_MEDIUM
565 mtspr SPRN_SPRG1,r13 /* save r13 */
b5bbeb23 566 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
14cf11af 567
b5bbeb23 568 .globl machine_check_fwnmi
8c4f1f29 569 .align 7
14cf11af 570machine_check_fwnmi:
b5bbeb23
PM		 571 HMT_MEDIUM
572 mtspr SPRN_SPRG1,r13 /* save r13 */
b5bbeb23 573 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
14cf11af
PM		 574
575#ifdef CONFIG_PPC_ISERIES
576/*** ISeries-LPAR interrupt handlers ***/
577
578 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
579
580 .globl data_access_iSeries
581data_access_iSeries:
b5bbeb23 582 mtspr SPRN_SPRG1,r13
14cf11af 583BEGIN_FTR_SECTION
b5bbeb23
PM		 584 mtspr SPRN_SPRG2,r12
585 mfspr r13,SPRN_DAR
586 mfspr r12,SPRN_DSISR
14cf11af
PM		 587 srdi r13,r13,60
588 rlwimi r13,r12,16,0x20
589 mfcr r12
590 cmpwi r13,0x2c
591 beq .do_stab_bolted_iSeries
592 mtcrf 0x80,r12
b5bbeb23 593 mfspr r12,SPRN_SPRG2
14cf11af
PM		 594END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
595 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
596 EXCEPTION_PROLOG_ISERIES_2
597 b data_access_common
598
599.do_stab_bolted_iSeries:
600 mtcrf 0x80,r12
b5bbeb23 601 mfspr r12,SPRN_SPRG2
14cf11af
PM		 602 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
603 EXCEPTION_PROLOG_ISERIES_2
604 b .do_stab_bolted
605
606 .globl data_access_slb_iSeries
607data_access_slb_iSeries:
b5bbeb23 608 mtspr SPRN_SPRG1,r13 /* save r13 */
3c726f8d 609 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
14cf11af 610 std r3,PACA_EXSLB+EX_R3(r13)
b5bbeb23 611 mfspr r3,SPRN_DAR
3c726f8d
BH		 612 std r9,PACA_EXSLB+EX_R9(r13)
613 mfcr r9
614#ifdef __DISABLED__
615 cmpdi r3,0
616 bge slb_miss_user_iseries
617#endif
618 std r10,PACA_EXSLB+EX_R10(r13)
619 std r11,PACA_EXSLB+EX_R11(r13)
620 std r12,PACA_EXSLB+EX_R12(r13)
621 mfspr r10,SPRN_SPRG1
622 std r10,PACA_EXSLB+EX_R13(r13)
3356bb9f
DG		 623 ld r12,PACALPPACAPTR(r13)
624 ld r12,LPPACASRR1(r12)
3c726f8d 625 b .slb_miss_realmode
14cf11af
PM		 626
627 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
628
629 .globl instruction_access_slb_iSeries
630instruction_access_slb_iSeries:
b5bbeb23 631 mtspr SPRN_SPRG1,r13 /* save r13 */
3c726f8d 632 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
14cf11af 633 std r3,PACA_EXSLB+EX_R3(r13)
3356bb9f
DG		 634 ld r3,PACALPPACAPTR(r13)
635 ld r3,LPPACASRR0(r3) /* get SRR0 value */
3c726f8d
BH		 636 std r9,PACA_EXSLB+EX_R9(r13)
637 mfcr r9
638#ifdef __DISABLED__
639 cmpdi r3,0
640 bge .slb_miss_user_iseries
641#endif
642 std r10,PACA_EXSLB+EX_R10(r13)
643 std r11,PACA_EXSLB+EX_R11(r13)
644 std r12,PACA_EXSLB+EX_R12(r13)
645 mfspr r10,SPRN_SPRG1
646 std r10,PACA_EXSLB+EX_R13(r13)
3356bb9f
DG		 647 ld r12,PACALPPACAPTR(r13)
648 ld r12,LPPACASRR1(r12)
3c726f8d
BH		 649 b .slb_miss_realmode
650
651#ifdef __DISABLED__
652slb_miss_user_iseries:
653 std r10,PACA_EXGEN+EX_R10(r13)
654 std r11,PACA_EXGEN+EX_R11(r13)
655 std r12,PACA_EXGEN+EX_R12(r13)
656 mfspr r10,SPRG1
657 ld r11,PACA_EXSLB+EX_R9(r13)
658 ld r12,PACA_EXSLB+EX_R3(r13)
659 std r10,PACA_EXGEN+EX_R13(r13)
660 std r11,PACA_EXGEN+EX_R9(r13)
661 std r12,PACA_EXGEN+EX_R3(r13)
662 EXCEPTION_PROLOG_ISERIES_2
663 b slb_miss_user_common
664#endif
14cf11af
PM		 665
666 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
667 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
668 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
669 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
670 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
671 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
672 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
673
674 .globl system_call_iSeries
675system_call_iSeries:
676 mr r9,r13
b5bbeb23 677 mfspr r13,SPRN_SPRG3
14cf11af
PM		 678 EXCEPTION_PROLOG_ISERIES_2
679 b system_call_common
680
681 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
682 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
683 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
684
685 .globl system_reset_iSeries
686system_reset_iSeries:
b5bbeb23 687 mfspr r13,SPRN_SPRG3 /* Get paca address */
14cf11af
PM		 688 mfmsr r24
689 ori r24,r24,MSR_RI
690 mtmsrd r24 /* RI on */
691 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
692 cmpwi 0,r24,0 /* Are we processor 0? */
693 beq .__start_initialization_iSeries /* Start up the first processor */
694 mfspr r4,SPRN_CTRLF
695 li r5,CTRL_RUNLATCH /* Turn off the run light */
696 andc r4,r4,r5
697 mtspr SPRN_CTRLT,r4
698
6991:
700 HMT_LOW
701#ifdef CONFIG_SMP
702 lbz r23,PACAPROCSTART(r13) /* Test if this processor
703 * should start */
704 sync
e58c3495 705 LOAD_REG_IMMEDIATE(r3,current_set)
14cf11af
PM		 706 sldi r28,r24,3 /* get current_set[cpu#] */
707 ldx r3,r3,r28
708 addi r1,r3,THREAD_SIZE
709 subi r1,r1,STACK_FRAME_OVERHEAD
710
711 cmpwi 0,r23,0
712 beq iSeries_secondary_smp_loop /* Loop until told to go */
713 bne .__secondary_start /* Loop until told to go */
714iSeries_secondary_smp_loop:
715 /* Let the Hypervisor know we are alive */
716 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
717 lis r3,0x8002
718 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
719#else /* CONFIG_SMP */
720 /* Yield the processor. This is required for non-SMP kernels
721 which are running on multi-threaded machines. */
722 lis r3,0x8000
723 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
724 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
725 li r4,0 /* "yield timed" */
726 li r5,-1 /* "yield forever" */
727#endif /* CONFIG_SMP */
728 li r0,-1 /* r0=-1 indicates a Hypervisor call */
729 sc /* Invoke the hypervisor via a system call */
b5bbeb23 730 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
14cf11af
PM		 731 b 1b /* If SMP not configured, secondaries
732 * loop forever */
733
734 .globl decrementer_iSeries_masked
735decrementer_iSeries_masked:
f9b4045d 736 /* We may not have a valid TOC pointer in here. */
14cf11af 737 li r11,1
3356bb9f
DG		 738 ld r12,PACALPPACAPTR(r13)
739 stb r11,LPPACADECRINT(r12)
f9b4045d
ME		 740 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
741 lwz r12,0(r12)
14cf11af
PM		 742 mtspr SPRN_DEC,r12
743 /* fall through */
744
745 .globl hardware_interrupt_iSeries_masked
746hardware_interrupt_iSeries_masked:
747 mtcrf 0x80,r9 /* Restore regs */
3356bb9f
DG		 748 ld r12,PACALPPACAPTR(r13)
749 ld r11,LPPACASRR0(r12)
750 ld r12,LPPACASRR1(r12)
b5bbeb23
PM		 751 mtspr SPRN_SRR0,r11
752 mtspr SPRN_SRR1,r12
14cf11af
PM		 753 ld r9,PACA_EXGEN+EX_R9(r13)
754 ld r10,PACA_EXGEN+EX_R10(r13)
755 ld r11,PACA_EXGEN+EX_R11(r13)
756 ld r12,PACA_EXGEN+EX_R12(r13)
757 ld r13,PACA_EXGEN+EX_R13(r13)
758 rfid
759 b . /* prevent speculative execution */
760#endif /* CONFIG_PPC_ISERIES */
761
762/*** Common interrupt handlers ***/
763
764 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
765
766 /*
767 * Machine check is different because we use a different
768 * save area: PACA_EXMC instead of PACA_EXGEN.
769 */
770 .align 7
771 .globl machine_check_common
772machine_check_common:
773 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
774 DISABLE_INTS
775 bl .save_nvgprs
776 addi r3,r1,STACK_FRAME_OVERHEAD
777 bl .machine_check_exception
778 b .ret_from_except
779
780 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
781 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
782 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
783 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
784 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
785 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
786 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
787#ifdef CONFIG_ALTIVEC
788 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
789#else
790 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
791#endif
792
793/*
794 * Here we have detected that the kernel stack pointer is bad.
795 * R9 contains the saved CR, r13 points to the paca,
796 * r10 contains the (bad) kernel stack pointer,
797 * r11 and r12 contain the saved SRR0 and SRR1.
798 * We switch to using an emergency stack, save the registers there,
799 * and call kernel_bad_stack(), which panics.
800 */
801bad_stack:
802 ld r1,PACAEMERGSP(r13)
803 subi r1,r1,64+INT_FRAME_SIZE
804 std r9,_CCR(r1)
805 std r10,GPR1(r1)
806 std r11,_NIP(r1)
807 std r12,_MSR(r1)
b5bbeb23
PM		 808 mfspr r11,SPRN_DAR
809 mfspr r12,SPRN_DSISR
14cf11af
PM		 810 std r11,_DAR(r1)
811 std r12,_DSISR(r1)
812 mflr r10
813 mfctr r11
814 mfxer r12
815 std r10,_LINK(r1)
816 std r11,_CTR(r1)
817 std r12,_XER(r1)
818 SAVE_GPR(0,r1)
819 SAVE_GPR(2,r1)
820 SAVE_4GPRS(3,r1)
821 SAVE_2GPRS(7,r1)
822 SAVE_10GPRS(12,r1)
823 SAVE_10GPRS(22,r1)
824 addi r11,r1,INT_FRAME_SIZE
825 std r11,0(r1)
826 li r12,0
827 std r12,0(r11)
828 ld r2,PACATOC(r13)
8291: addi r3,r1,STACK_FRAME_OVERHEAD
830 bl .kernel_bad_stack
831 b 1b
832
833/*
834 * Return from an exception with minimal checks.
835 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
836 * If interrupts have been enabled, or anything has been
837 * done that might have changed the scheduling status of
838 * any task or sent any task a signal, you should use
839 * ret_from_except or ret_from_except_lite instead of this.
840 */
40ef8cbc 841 .globl fast_exception_return
14cf11af
PM		 842fast_exception_return:
843 ld r12,_MSR(r1)
844 ld r11,_NIP(r1)
845 andi. r3,r12,MSR_RI /* check if RI is set */
846 beq- unrecov_fer
847 ld r3,_CCR(r1)
848 ld r4,_LINK(r1)
849 ld r5,_CTR(r1)
850 ld r6,_XER(r1)
851 mtcr r3
852 mtlr r4
853 mtctr r5
854 mtxer r6
855 REST_GPR(0, r1)
856 REST_8GPRS(2, r1)
857
858 mfmsr r10
859 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
860 mtmsrd r10,1
861
b5bbeb23
PM		 862 mtspr SPRN_SRR1,r12
863 mtspr SPRN_SRR0,r11
14cf11af
PM		 864 REST_4GPRS(10, r1)
865 ld r1,GPR1(r1)
866 rfid
867 b . /* prevent speculative execution */
868
869unrecov_fer:
870 bl .save_nvgprs
8711: addi r3,r1,STACK_FRAME_OVERHEAD
872 bl .unrecoverable_exception
873 b 1b
874
875/*
876 * Here r13 points to the paca, r9 contains the saved CR,
877 * SRR0 and SRR1 are saved in r11 and r12,
878 * r9 - r13 are saved in paca->exgen.
879 */
880 .align 7
881 .globl data_access_common
882data_access_common:
b5bbeb23 883 mfspr r10,SPRN_DAR
14cf11af 884 std r10,PACA_EXGEN+EX_DAR(r13)
b5bbeb23 885 mfspr r10,SPRN_DSISR
14cf11af
PM		 886 stw r10,PACA_EXGEN+EX_DSISR(r13)
887 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
888 ld r3,PACA_EXGEN+EX_DAR(r13)
889 lwz r4,PACA_EXGEN+EX_DSISR(r13)
890 li r5,0x300
891 b .do_hash_page /* Try to handle as hpte fault */
892
893 .align 7
894 .globl instruction_access_common
895instruction_access_common:
896 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
897 ld r3,_NIP(r1)
898 andis. r4,r12,0x5820
899 li r5,0x400
900 b .do_hash_page /* Try to handle as hpte fault */
901
3c726f8d
BH		 902/*
903 * Here is the common SLB miss user that is used when going to virtual
904 * mode for SLB misses, that is currently not used
905 */
906#ifdef __DISABLED__
907 .align 7
908 .globl slb_miss_user_common
909slb_miss_user_common:
910 mflr r10
911 std r3,PACA_EXGEN+EX_DAR(r13)
912 stw r9,PACA_EXGEN+EX_CCR(r13)
913 std r10,PACA_EXGEN+EX_LR(r13)
914 std r11,PACA_EXGEN+EX_SRR0(r13)
915 bl .slb_allocate_user
916
917 ld r10,PACA_EXGEN+EX_LR(r13)
918 ld r3,PACA_EXGEN+EX_R3(r13)
919 lwz r9,PACA_EXGEN+EX_CCR(r13)
920 ld r11,PACA_EXGEN+EX_SRR0(r13)
921 mtlr r10
922 beq- slb_miss_fault
923
924 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
925 beq- unrecov_user_slb
926 mfmsr r10
927
928.machine push
929.machine "power4"
930 mtcrf 0x80,r9
931.machine pop
932
933 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
934 mtmsrd r10,1
935
936 mtspr SRR0,r11
937 mtspr SRR1,r12
938
939 ld r9,PACA_EXGEN+EX_R9(r13)
940 ld r10,PACA_EXGEN+EX_R10(r13)
941 ld r11,PACA_EXGEN+EX_R11(r13)
942 ld r12,PACA_EXGEN+EX_R12(r13)
943 ld r13,PACA_EXGEN+EX_R13(r13)
944 rfid
945 b .
946
947slb_miss_fault:
948 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
949 ld r4,PACA_EXGEN+EX_DAR(r13)
950 li r5,0
951 std r4,_DAR(r1)
952 std r5,_DSISR(r1)
953 b .handle_page_fault
954
955unrecov_user_slb:
956 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
957 DISABLE_INTS
958 bl .save_nvgprs
9591: addi r3,r1,STACK_FRAME_OVERHEAD
960 bl .unrecoverable_exception
961 b 1b
962
963#endif /* __DISABLED__ */
964
965
966/*
967 * r13 points to the PACA, r9 contains the saved CR,
968 * r12 contain the saved SRR1, SRR0 is still ready for return
969 * r3 has the faulting address
970 * r9 - r13 are saved in paca->exslb.
971 * r3 is saved in paca->slb_r3
972 * We assume we aren't going to take any exceptions during this procedure.
973 */
974_GLOBAL(slb_miss_realmode)
975 mflr r10
976
977 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
978 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
979
980 bl .slb_allocate_realmode
981
982 /* All done -- return from exception. */
983
984 ld r10,PACA_EXSLB+EX_LR(r13)
985 ld r3,PACA_EXSLB+EX_R3(r13)
986 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
987#ifdef CONFIG_PPC_ISERIES
3356bb9f
DG		 988 ld r11,PACALPPACAPTR(r13)
989 ld r11,LPPACASRR0(r11) /* get SRR0 value */
3c726f8d
BH		 990#endif /* CONFIG_PPC_ISERIES */
991
992 mtlr r10
993
994 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
995 beq- unrecov_slb
996
997.machine push
998.machine "power4"
999 mtcrf 0x80,r9
1000 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1001.machine pop
1002
1003#ifdef CONFIG_PPC_ISERIES
1004 mtspr SPRN_SRR0,r11
1005 mtspr SPRN_SRR1,r12
1006#endif /* CONFIG_PPC_ISERIES */
1007 ld r9,PACA_EXSLB+EX_R9(r13)
1008 ld r10,PACA_EXSLB+EX_R10(r13)
1009 ld r11,PACA_EXSLB+EX_R11(r13)
1010 ld r12,PACA_EXSLB+EX_R12(r13)
1011 ld r13,PACA_EXSLB+EX_R13(r13)
1012 rfid
1013 b . /* prevent speculative execution */
1014
1015unrecov_slb:
1016 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1017 DISABLE_INTS
1018 bl .save_nvgprs
10191: addi r3,r1,STACK_FRAME_OVERHEAD
1020 bl .unrecoverable_exception
1021 b 1b
1022
14cf11af
PM		 1023 .align 7
1024 .globl hardware_interrupt_common
1025 .globl hardware_interrupt_entry
1026hardware_interrupt_common:
1027 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1028hardware_interrupt_entry:
1029 DISABLE_INTS
cb2c9b27 1030 bl .ppc64_runlatch_on
14cf11af
PM		 1031 addi r3,r1,STACK_FRAME_OVERHEAD
1032 bl .do_IRQ
1033 b .ret_from_except_lite
1034
1035 .align 7
1036 .globl alignment_common
1037alignment_common:
b5bbeb23 1038 mfspr r10,SPRN_DAR
14cf11af 1039 std r10,PACA_EXGEN+EX_DAR(r13)
b5bbeb23 1040 mfspr r10,SPRN_DSISR
14cf11af
PM		 1041 stw r10,PACA_EXGEN+EX_DSISR(r13)
1042 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1043 ld r3,PACA_EXGEN+EX_DAR(r13)
1044 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1045 std r3,_DAR(r1)
1046 std r4,_DSISR(r1)
1047 bl .save_nvgprs
1048 addi r3,r1,STACK_FRAME_OVERHEAD
1049 ENABLE_INTS
1050 bl .alignment_exception
1051 b .ret_from_except
1052
1053 .align 7
1054 .globl program_check_common
1055program_check_common:
1056 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1057 bl .save_nvgprs
1058 addi r3,r1,STACK_FRAME_OVERHEAD
1059 ENABLE_INTS
1060 bl .program_check_exception
1061 b .ret_from_except
1062
1063 .align 7
1064 .globl fp_unavailable_common
1065fp_unavailable_common:
1066 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1067 bne .load_up_fpu /* if from user, just load it up */
1068 bl .save_nvgprs
1069 addi r3,r1,STACK_FRAME_OVERHEAD
1070 ENABLE_INTS
1071 bl .kernel_fp_unavailable_exception
1072 BUG_OPCODE
1073
14cf11af
PM		 1074 .align 7
1075 .globl altivec_unavailable_common
1076altivec_unavailable_common:
1077 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1078#ifdef CONFIG_ALTIVEC
1079BEGIN_FTR_SECTION
1080 bne .load_up_altivec /* if from user, just load it up */
1081END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1082#endif
1083 bl .save_nvgprs
1084 addi r3,r1,STACK_FRAME_OVERHEAD
1085 ENABLE_INTS
1086 bl .altivec_unavailable_exception
1087 b .ret_from_except
1088
1089#ifdef CONFIG_ALTIVEC
1090/*
1091 * load_up_altivec(unused, unused, tsk)
1092 * Disable VMX for the task which had it previously,
1093 * and save its vector registers in its thread_struct.
1094 * Enables the VMX for use in the kernel on return.
1095 * On SMP we know the VMX is free, since we give it up every
1096 * switch (ie, no lazy save of the vector registers).
1097 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1098 */
1099_STATIC(load_up_altivec)
1100 mfmsr r5 /* grab the current MSR */
1101 oris r5,r5,MSR_VEC@h
1102 mtmsrd r5 /* enable use of VMX now */
1103 isync
1104
1105/*
1106 * For SMP, we don't do lazy VMX switching because it just gets too
1107 * horrendously complex, especially when a task switches from one CPU
1108 * to another. Instead we call giveup_altvec in switch_to.
1109 * VRSAVE isn't dealt with here, that is done in the normal context
1110 * switch code. Note that we could rely on vrsave value to eventually
1111 * avoid saving all of the VREGs here...
1112 */
1113#ifndef CONFIG_SMP
1114 ld r3,last_task_used_altivec@got(r2)
1115 ld r4,0(r3)
1116 cmpdi 0,r4,0
1117 beq 1f
1118 /* Save VMX state to last_task_used_altivec's THREAD struct */
1119 addi r4,r4,THREAD
1120 SAVE_32VRS(0,r5,r4)
1121 mfvscr vr0
1122 li r10,THREAD_VSCR
1123 stvx vr0,r10,r4
1124 /* Disable VMX for last_task_used_altivec */
1125 ld r5,PT_REGS(r4)
1126 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1127 lis r6,MSR_VEC@h
1128 andc r4,r4,r6
1129 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
11301:
1131#endif /* CONFIG_SMP */
1132 /* Hack: if we get an altivec unavailable trap with VRSAVE
1133 * set to all zeros, we assume this is a broken application
1134 * that fails to set it properly, and thus we switch it to
1135 * all 1's
1136 */
1137 mfspr r4,SPRN_VRSAVE
1138 cmpdi 0,r4,0
1139 bne+ 1f
1140 li r4,-1
1141 mtspr SPRN_VRSAVE,r4
11421:
1143 /* enable use of VMX after return */
1144 ld r4,PACACURRENT(r13)
1145 addi r5,r4,THREAD /* Get THREAD */
1146 oris r12,r12,MSR_VEC@h
1147 std r12,_MSR(r1)
1148 li r4,1
1149 li r10,THREAD_VSCR
1150 stw r4,THREAD_USED_VR(r5)
1151 lvx vr0,r10,r5
1152 mtvscr vr0
1153 REST_32VRS(0,r4,r5)
1154#ifndef CONFIG_SMP
1155 /* Update last_task_used_math to 'current' */
1156 subi r4,r5,THREAD /* Back to 'current' */
1157 std r4,0(r3)
1158#endif /* CONFIG_SMP */
1159 /* restore registers and return */
1160 b fast_exception_return
1161#endif /* CONFIG_ALTIVEC */
1162
1163/*
1164 * Hash table stuff
1165 */
1166 .align 7
1167_GLOBAL(do_hash_page)
1168 std r3,_DAR(r1)
1169 std r4,_DSISR(r1)
1170
1171 andis. r0,r4,0xa450 /* weird error? */
1172 bne- .handle_page_fault /* if not, try to insert a HPTE */
1173BEGIN_FTR_SECTION
1174 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1175 bne- .do_ste_alloc /* If so handle it */
1176END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1177
1178 /*
1179 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1180 * accessing a userspace segment (even from the kernel). We assume
1181 * kernel addresses always have the high bit set.
1182 */
1183 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1184 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1185 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1186 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1187 ori r4,r4,1 /* add _PAGE_PRESENT */
1188 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1189
1190 /*
1191 * On iSeries, we soft-disable interrupts here, then
1192 * hard-enable interrupts so that the hash_page code can spin on
1193 * the hash_table_lock without problems on a shared processor.
1194 */
1195 DISABLE_INTS
1196
1197 /*
1198 * r3 contains the faulting address
1199 * r4 contains the required access permissions
1200 * r5 contains the trap number
1201 *
1202 * at return r3 = 0 for success
1203 */
1204 bl .hash_page /* build HPTE if possible */
1205 cmpdi r3,0 /* see if hash_page succeeded */
1206
1207#ifdef DO_SOFT_DISABLE
1208 /*
1209 * If we had interrupts soft-enabled at the point where the
1210 * DSI/ISI occurred, and an interrupt came in during hash_page,
1211 * handle it now.
1212 * We jump to ret_from_except_lite rather than fast_exception_return
1213 * because ret_from_except_lite will check for and handle pending
1214 * interrupts if necessary.
1215 */
1216 beq .ret_from_except_lite
1217 /* For a hash failure, we don't bother re-enabling interrupts */
1218 ble- 12f
1219
1220 /*
1221 * hash_page couldn't handle it, set soft interrupt enable back
1222 * to what it was before the trap. Note that .local_irq_restore
1223 * handles any interrupts pending at this point.
1224 */
1225 ld r3,SOFTE(r1)
1226 bl .local_irq_restore
1227 b 11f
1228#else
1229 beq fast_exception_return /* Return from exception on success */
1230 ble- 12f /* Failure return from hash_page */
1231
1232 /* fall through */
1233#endif
1234
1235/* Here we have a page fault that hash_page can't handle. */
1236_GLOBAL(handle_page_fault)
1237 ENABLE_INTS
123811: ld r4,_DAR(r1)
1239 ld r5,_DSISR(r1)
1240 addi r3,r1,STACK_FRAME_OVERHEAD
1241 bl .do_page_fault
1242 cmpdi r3,0
1243 beq+ .ret_from_except_lite
1244 bl .save_nvgprs
1245 mr r5,r3
1246 addi r3,r1,STACK_FRAME_OVERHEAD
1247 lwz r4,_DAR(r1)
1248 bl .bad_page_fault
1249 b .ret_from_except
1250
1251/* We have a page fault that hash_page could handle but HV refused
1252 * the PTE insertion
1253 */
125412: bl .save_nvgprs
1255 addi r3,r1,STACK_FRAME_OVERHEAD
1256 lwz r4,_DAR(r1)
1257 bl .low_hash_fault
1258 b .ret_from_except
1259
1260 /* here we have a segment miss */
1261_GLOBAL(do_ste_alloc)
1262 bl .ste_allocate /* try to insert stab entry */
1263 cmpdi r3,0
1264 beq+ fast_exception_return
1265 b .handle_page_fault
1266
1267/*
1268 * r13 points to the PACA, r9 contains the saved CR,
1269 * r11 and r12 contain the saved SRR0 and SRR1.
1270 * r9 - r13 are saved in paca->exslb.
1271 * We assume we aren't going to take any exceptions during this procedure.
1272 * We assume (DAR >> 60) == 0xc.
1273 */
1274 .align 7
1275_GLOBAL(do_stab_bolted)
1276 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1277 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1278
1279 /* Hash to the primary group */
1280 ld r10,PACASTABVIRT(r13)
b5bbeb23 1281 mfspr r11,SPRN_DAR
14cf11af
PM		 1282 srdi r11,r11,28
1283 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1284
1285 /* Calculate VSID */
1286 /* This is a kernel address, so protovsid = ESID */
1287 ASM_VSID_SCRAMBLE(r11, r9)
1288 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1289
1290 /* Search the primary group for a free entry */
12911: ld r11,0(r10) /* Test valid bit of the current ste */
1292 andi. r11,r11,0x80
1293 beq 2f
1294 addi r10,r10,16
1295 andi. r11,r10,0x70
1296 bne 1b
1297
1298 /* Stick for only searching the primary group for now. */
1299 /* At least for now, we use a very simple random castout scheme */
1300 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1301 mftb r11
1302 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1303 ori r11,r11,0x10
1304
1305 /* r10 currently points to an ste one past the group of interest */
1306 /* make it point to the randomly selected entry */
1307 subi r10,r10,128
1308 or r10,r10,r11 /* r10 is the entry to invalidate */
1309
1310 isync /* mark the entry invalid */
1311 ld r11,0(r10)
1312 rldicl r11,r11,56,1 /* clear the valid bit */
1313 rotldi r11,r11,8
1314 std r11,0(r10)
1315 sync
1316
1317 clrrdi r11,r11,28 /* Get the esid part of the ste */
1318 slbie r11
1319
13202: std r9,8(r10) /* Store the vsid part of the ste */
1321 eieio
1322
b5bbeb23 1323 mfspr r11,SPRN_DAR /* Get the new esid */
14cf11af
PM		 1324 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1325 ori r11,r11,0x90 /* Turn on valid and kp */
1326 std r11,0(r10) /* Put new entry back into the stab */
1327
1328 sync
1329
1330 /* All done -- return from exception. */
1331 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1332 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1333
1334 andi. r10,r12,MSR_RI
1335 beq- unrecov_slb
1336
1337 mtcrf 0x80,r9 /* restore CR */
1338
1339 mfmsr r10
1340 clrrdi r10,r10,2
1341 mtmsrd r10,1
1342
b5bbeb23
PM		 1343 mtspr SPRN_SRR0,r11
1344 mtspr SPRN_SRR1,r12
14cf11af
PM		 1345 ld r9,PACA_EXSLB+EX_R9(r13)
1346 ld r10,PACA_EXSLB+EX_R10(r13)
1347 ld r11,PACA_EXSLB+EX_R11(r13)
1348 ld r12,PACA_EXSLB+EX_R12(r13)
1349 ld r13,PACA_EXSLB+EX_R13(r13)
1350 rfid
1351 b . /* prevent speculative execution */
1352
14cf11af
PM		 1353/*
1354 * Space for CPU0's segment table.
1355 *
1356 * On iSeries, the hypervisor must fill in at least one entry before
1357 * we get control (with relocate on). The address is give to the hv
ee400b63 1358 * as a page number (see xLparMap in lpardata.c), so this must be at a
14cf11af
PM		 1359 * fixed address (the linker can't compute (u64)&initial_stab >>
1360 * PAGE_SHIFT).
1361 */
758438a7 1362 . = STAB0_OFFSET /* 0x6000 */
14cf11af
PM		 1363 .globl initial_stab
1364initial_stab:
1365 .space 4096
1366
1367/*
1368 * Data area reserved for FWNMI option.
1369 * This address (0x7000) is fixed by the RPA.
1370 */
1371 .= 0x7000
1372 .globl fwnmi_data_area
1373fwnmi_data_area:
1374
1375 /* iSeries does not use the FWNMI stuff, so it is safe to put
1376 * this here, even if we later allow kernels that will boot on
1377 * both pSeries and iSeries */
1378#ifdef CONFIG_PPC_ISERIES
1379 . = LPARMAP_PHYS
1380#include "lparmap.s"
1381/*
1382 * This ".text" is here for old compilers that generate a trailing
1383 * .note section when compiling .c files to .s
1384 */
1385 .text
1386#endif /* CONFIG_PPC_ISERIES */
1387
1388 . = 0x8000
1389
1390/*
1391 * On pSeries, secondary processors spin in the following code.
1392 * At entry, r3 = this processor's number (physical cpu id)
1393 */
1394_GLOBAL(pSeries_secondary_smp_init)
1395 mr r24,r3
1396
1397 /* turn on 64-bit mode */
1398 bl .enable_64b_mode
1399 isync
1400
1401 /* Copy some CPU settings from CPU 0 */
1402 bl .__restore_cpu_setup
1403
1404 /* Set up a paca value for this processor. Since we have the
1405 * physical cpu id in r24, we need to search the pacas to find
1406 * which logical id maps to our physical one.
1407 */
e58c3495 1408 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1409 li r5,0 /* logical cpu id */
14101: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1411 cmpw r6,r24 /* Compare to our id */
1412 beq 2f
1413 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1414 addi r5,r5,1
1415 cmpwi r5,NR_CPUS
1416 blt 1b
1417
1418 mr r3,r24 /* not found, copy phys to r3 */
1419 b .kexec_wait /* next kernel might do better */
1420
b5bbeb23 14212: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
14cf11af
PM		 1422 /* From now on, r24 is expected to be logical cpuid */
1423 mr r24,r5
14243: HMT_LOW
1425 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1426 /* start. */
1427 sync
1428
1429 /* Create a temp kernel stack for use before relocation is on. */
1430 ld r1,PACAEMERGSP(r13)
1431 subi r1,r1,STACK_FRAME_OVERHEAD
1432
1433 cmpwi 0,r23,0
1434#ifdef CONFIG_SMP
1435 bne .__secondary_start
1436#endif
1437 b 3b /* Loop until told to go */
1438
1439#ifdef CONFIG_PPC_ISERIES
1440_STATIC(__start_initialization_iSeries)
1441 /* Clear out the BSS */
e58c3495
DG		 1442 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1443 LOAD_REG_IMMEDIATE(r8,__bss_start)
14cf11af
PM		 1444 sub r11,r11,r8 /* bss size */
1445 addi r11,r11,7 /* round up to an even double word */
1446 rldicl. r11,r11,61,3 /* shift right by 3 */
1447 beq 4f
1448 addi r8,r8,-8
1449 li r0,0
1450 mtctr r11 /* zero this many doublewords */
14513: stdu r0,8(r8)
1452 bdnz 3b
14534:
e58c3495 1454 LOAD_REG_IMMEDIATE(r1,init_thread_union)
14cf11af
PM		 1455 addi r1,r1,THREAD_SIZE
1456 li r0,0
1457 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1458
e58c3495
DG		 1459 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1460 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
14cf11af
PM		 1461 li r5,0
1462 bl .identify_cpu
1463
e58c3495 1464 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1465 addi r2,r2,0x4000
1466 addi r2,r2,0x4000
1467
1468 bl .iSeries_early_setup
ee400b63 1469 bl .early_setup
14cf11af
PM		 1470
1471 /* relocation is on at this point */
1472
1473 b .start_here_common
1474#endif /* CONFIG_PPC_ISERIES */
1475
1476#ifdef CONFIG_PPC_MULTIPLATFORM
1477
1478_STATIC(__mmu_off)
1479 mfmsr r3
1480 andi. r0,r3,MSR_IR|MSR_DR
1481 beqlr
1482 andc r3,r3,r0
1483 mtspr SPRN_SRR0,r4
1484 mtspr SPRN_SRR1,r3
1485 sync
1486 rfid
1487 b . /* prevent speculative execution */
1488
1489
1490/*
1491 * Here is our main kernel entry point. We support currently 2 kind of entries
1492 * depending on the value of r5.
1493 *
1494 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1495 * in r3...r7
1496 *
1497 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1498 * DT block, r4 is a physical pointer to the kernel itself
1499 *
1500 */
1501_GLOBAL(__start_initialization_multiplatform)
be42d5fa 1502#ifdef CONFIG_PPC_MULTIPLATFORM
14cf11af
PM		 1503 /*
1504 * Are we booted from a PROM Of-type client-interface ?
1505 */
1506 cmpldi cr0,r5,0
1507 bne .__boot_from_prom /* yes -> prom */
be42d5fa 1508#endif
14cf11af
PM		 1509
1510 /* Save parameters */
1511 mr r31,r3
1512 mr r30,r4
1513
1514 /* Make sure we are running in 64 bits mode */
1515 bl .enable_64b_mode
1516
1517 /* Setup some critical 970 SPRs before switching MMU off */
1518 bl .__970_cpu_preinit
1519
1520 /* cpu # */
1521 li r24,0
1522
1523 /* Switch off MMU if not already */
e58c3495 1524 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
14cf11af
PM		 1525 add r4,r4,r30
1526 bl .__mmu_off
1527 b .__after_prom_start
1528
be42d5fa 1529#ifdef CONFIG_PPC_MULTIPLATFORM
14cf11af
PM		 1530_STATIC(__boot_from_prom)
1531 /* Save parameters */
1532 mr r31,r3
1533 mr r30,r4
1534 mr r29,r5
1535 mr r28,r6
1536 mr r27,r7
1537
1538 /* Make sure we are running in 64 bits mode */
1539 bl .enable_64b_mode
1540
1541 /* put a relocation offset into r3 */
1542 bl .reloc_offset
1543
e58c3495 1544 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1545 addi r2,r2,0x4000
1546 addi r2,r2,0x4000
1547
1548 /* Relocate the TOC from a virt addr to a real addr */
5a408329 1549 add r2,r2,r3
14cf11af
PM		 1550
1551 /* Restore parameters */
1552 mr r3,r31
1553 mr r4,r30
1554 mr r5,r29
1555 mr r6,r28
1556 mr r7,r27
1557
1558 /* Do all of the interaction with OF client interface */
1559 bl .prom_init
1560 /* We never return */
1561 trap
be42d5fa 1562#endif
14cf11af
PM		 1563
1564/*
1565 * At this point, r3 contains the physical address we are running at,
1566 * returned by prom_init()
1567 */
1568_STATIC(__after_prom_start)
1569
1570/*
758438a7 1571 * We need to run with __start at physical address PHYSICAL_START.
14cf11af
PM		 1572 * This will leave some code in the first 256B of
1573 * real memory, which are reserved for software use.
1574 * The remainder of the first page is loaded with the fixed
1575 * interrupt vectors. The next two pages are filled with
1576 * unknown exception placeholders.
1577 *
1578 * Note: This process overwrites the OF exception vectors.
1579 * r26 == relocation offset
1580 * r27 == KERNELBASE
1581 */
1582 bl .reloc_offset
1583 mr r26,r3
e58c3495 1584 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
14cf11af 1585
e58c3495 1586 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
14cf11af
PM		 1587
1588 // XXX FIXME: Use phys returned by OF (r30)
5a408329 1589 add r4,r27,r26 /* source addr */
14cf11af
PM		 1590 /* current address of _start */
1591 /* i.e. where we are running */
1592 /* the source addr */
1593
e58c3495 1594 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
14cf11af
PM		 1595 sub r5,r5,r27
1596
1597 li r6,0x100 /* Start offset, the first 0x100 */
1598 /* bytes were copied earlier. */
1599
1600 bl .copy_and_flush /* copy the first n bytes */
1601 /* this includes the code being */
1602 /* executed here. */
1603
e58c3495 1604 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
14cf11af
PM		 1605 mtctr r0 /* that we just made/relocated */
1606 bctr
1607
e58c3495 16084: LOAD_REG_IMMEDIATE(r5,klimit)
5a408329 1609 add r5,r5,r26
14cf11af
PM		 1610 ld r5,0(r5) /* get the value of klimit */
1611 sub r5,r5,r27
1612 bl .copy_and_flush /* copy the rest */
1613 b .start_here_multiplatform
1614
1615#endif /* CONFIG_PPC_MULTIPLATFORM */
1616
1617/*
1618 * Copy routine used to copy the kernel to start at physical address 0
1619 * and flush and invalidate the caches as needed.
1620 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1621 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1622 *
1623 * Note: this routine *only* clobbers r0, r6 and lr
1624 */
1625_GLOBAL(copy_and_flush)
1626 addi r5,r5,-8
1627 addi r6,r6,-8
16284: li r0,16 /* Use the least common */
1629 /* denominator cache line */
1630 /* size. This results in */
1631 /* extra cache line flushes */
1632 /* but operation is correct. */
1633 /* Can't get cache line size */
1634 /* from NACA as it is being */
1635 /* moved too. */
1636
1637 mtctr r0 /* put # words/line in ctr */
16383: addi r6,r6,8 /* copy a cache line */
1639 ldx r0,r6,r4
1640 stdx r0,r6,r3
1641 bdnz 3b
1642 dcbst r6,r3 /* write it to memory */
1643 sync
1644 icbi r6,r3 /* flush the icache line */
1645 cmpld 0,r6,r5
1646 blt 4b
1647 sync
1648 addi r5,r5,8
1649 addi r6,r6,8
1650 blr
1651
1652.align 8
1653copy_to_here:
1654
1655#ifdef CONFIG_SMP
1656#ifdef CONFIG_PPC_PMAC
1657/*
1658 * On PowerMac, secondary processors starts from the reset vector, which
1659 * is temporarily turned into a call to one of the functions below.
1660 */
1661 .section ".text";
1662 .align 2 ;
1663
35499c01
PM		 1664 .globl __secondary_start_pmac_0
1665__secondary_start_pmac_0:
1666 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1667 li r24,0
1668 b 1f
1669 li r24,1
1670 b 1f
1671 li r24,2
1672 b 1f
1673 li r24,3
16741:
14cf11af
PM		 1675
1676_GLOBAL(pmac_secondary_start)
1677 /* turn on 64-bit mode */
1678 bl .enable_64b_mode
1679 isync
1680
1681 /* Copy some CPU settings from CPU 0 */
1682 bl .__restore_cpu_setup
1683
1684 /* pSeries do that early though I don't think we really need it */
1685 mfmsr r3
1686 ori r3,r3,MSR_RI
1687 mtmsrd r3 /* RI on */
1688
1689 /* Set up a paca value for this processor. */
e58c3495 1690 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1691 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1692 add r13,r13,r4 /* for this processor. */
b5bbeb23 1693 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
14cf11af
PM		 1694
1695 /* Create a temp kernel stack for use before relocation is on. */
1696 ld r1,PACAEMERGSP(r13)
1697 subi r1,r1,STACK_FRAME_OVERHEAD
1698
1699 b .__secondary_start
1700
1701#endif /* CONFIG_PPC_PMAC */
1702
1703/*
1704 * This function is called after the master CPU has released the
1705 * secondary processors. The execution environment is relocation off.
1706 * The paca for this processor has the following fields initialized at
1707 * this point:
1708 * 1. Processor number
1709 * 2. Segment table pointer (virtual address)
1710 * On entry the following are set:
1711 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1712 * r24 = cpu# (in Linux terms)
1713 * r13 = paca virtual address
1714 * SPRG3 = paca virtual address
1715 */
1716_GLOBAL(__secondary_start)
799d6046
PM		 1717 /* Set thread priority to MEDIUM */
1718 HMT_MEDIUM
14cf11af 1719
799d6046 1720 /* Load TOC */
14cf11af 1721 ld r2,PACATOC(r13)
799d6046
PM		 1722
1723 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1724 bl .early_setup_secondary
14cf11af
PM		 1725
1726 /* Initialize the kernel stack. Just a repeat for iSeries. */
e58c3495 1727 LOAD_REG_ADDR(r3, current_set)
14cf11af
PM		 1728 sldi r28,r24,3 /* get current_set[cpu#] */
1729 ldx r1,r3,r28
1730 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1731 std r1,PACAKSAVE(r13)
1732
799d6046 1733 /* Clear backchain so we get nice backtraces */
14cf11af
PM		 1734 li r7,0
1735 mtlr r7
1736
1737 /* enable MMU and jump to start_secondary */
e58c3495
DG		 1738 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1739 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
14cf11af
PM		 1740#ifdef DO_SOFT_DISABLE
1741 ori r4,r4,MSR_EE
1742#endif
b5bbeb23
PM		 1743 mtspr SPRN_SRR0,r3
1744 mtspr SPRN_SRR1,r4
14cf11af
PM		 1745 rfid
1746 b . /* prevent speculative execution */
1747
1748/*
1749 * Running with relocation on at this point. All we want to do is
1750 * zero the stack back-chain pointer before going into C code.
1751 */
1752_GLOBAL(start_secondary_prolog)
1753 li r3,0
1754 std r3,0(r1) /* Zero the stack frame pointer */
1755 bl .start_secondary
799d6046 1756 b .
14cf11af
PM		 1757#endif
1758
1759/*
1760 * This subroutine clobbers r11 and r12
1761 */
1762_GLOBAL(enable_64b_mode)
1763 mfmsr r11 /* grab the current MSR */
1764 li r12,1
1765 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1766 or r11,r11,r12
1767 li r12,1
1768 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1769 or r11,r11,r12
1770 mtmsrd r11
1771 isync
1772 blr
1773
1774#ifdef CONFIG_PPC_MULTIPLATFORM
1775/*
1776 * This is where the main kernel code starts.
1777 */
1778_STATIC(start_here_multiplatform)
1779 /* get a new offset, now that the kernel has moved. */
1780 bl .reloc_offset
1781 mr r26,r3
1782
1783 /* Clear out the BSS. It may have been done in prom_init,
1784 * already but that's irrelevant since prom_init will soon
1785 * be detached from the kernel completely. Besides, we need
1786 * to clear it now for kexec-style entry.
1787 */
e58c3495
DG		 1788 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1789 LOAD_REG_IMMEDIATE(r8,__bss_start)
14cf11af
PM		 1790 sub r11,r11,r8 /* bss size */
1791 addi r11,r11,7 /* round up to an even double word */
1792 rldicl. r11,r11,61,3 /* shift right by 3 */
1793 beq 4f
1794 addi r8,r8,-8
1795 li r0,0
1796 mtctr r11 /* zero this many doublewords */
17973: stdu r0,8(r8)
1798 bdnz 3b
17994:
1800
1801 mfmsr r6
1802 ori r6,r6,MSR_RI
1803 mtmsrd r6 /* RI on */
1804
14cf11af
PM		 1805 /* The following gets the stack and TOC set up with the regs */
1806 /* pointing to the real addr of the kernel stack. This is */
1807 /* all done to support the C function call below which sets */
1808 /* up the htab. This is done because we have relocated the */
1809 /* kernel but are still running in real mode. */
1810
e58c3495 1811 LOAD_REG_IMMEDIATE(r3,init_thread_union)
5a408329 1812 add r3,r3,r26
14cf11af
PM		 1813
1814 /* set up a stack pointer (physical address) */
1815 addi r1,r3,THREAD_SIZE
1816 li r0,0
1817 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1818
1819 /* set up the TOC (physical address) */
e58c3495 1820 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1821 addi r2,r2,0x4000
1822 addi r2,r2,0x4000
5a408329 1823 add r2,r2,r26
14cf11af 1824
e58c3495 1825 LOAD_REG_IMMEDIATE(r3, cpu_specs)
5a408329 1826 add r3,r3,r26
e58c3495 1827 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
5a408329 1828 add r4,r4,r26
14cf11af
PM		 1829 mr r5,r26
1830 bl .identify_cpu
1831
1832 /* Save some low level config HIDs of CPU0 to be copied to
1833 * other CPUs later on, or used for suspend/resume
1834 */
1835 bl .__save_cpu_setup
1836 sync
1837
1838 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1839 * note that boot_cpuid can always be 0 nowadays since there is
1840 * nowhere it can be initialized differently before we reach this
1841 * code
1842 */
e58c3495 1843 LOAD_REG_IMMEDIATE(r27, boot_cpuid)
5a408329 1844 add r27,r27,r26
14cf11af
PM		 1845 lwz r27,0(r27)
1846
e58c3495 1847 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1848 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1849 add r13,r13,r24 /* for this processor. */
5a408329 1850 add r13,r13,r26 /* convert to physical addr */
448b2719 1851 mtspr SPRN_SPRG3,r13
14cf11af
PM		 1852
1853 /* Do very early kernel initializations, including initial hash table,
1854 * stab and slb setup before we turn on relocation. */
1855
1856 /* Restore parameters passed from prom_init/kexec */
1857 mr r3,r31
1858 bl .early_setup
1859
e58c3495
DG		 1860 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1861 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
b5bbeb23
PM		 1862 mtspr SPRN_SRR0,r3
1863 mtspr SPRN_SRR1,r4
14cf11af
PM		 1864 rfid
1865 b . /* prevent speculative execution */
1866#endif /* CONFIG_PPC_MULTIPLATFORM */
1867
1868 /* This is where all platforms converge execution */
1869_STATIC(start_here_common)
1870 /* relocation is on at this point */
1871
1872 /* The following code sets up the SP and TOC now that we are */
1873 /* running with translation enabled. */
1874
e58c3495 1875 LOAD_REG_IMMEDIATE(r3,init_thread_union)
14cf11af
PM		 1876
1877 /* set up the stack */
1878 addi r1,r3,THREAD_SIZE
1879 li r0,0
1880 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1881
1882 /* Apply the CPUs-specific fixups (nop out sections not relevant
1883 * to this CPU
1884 */
1885 li r3,0
1886 bl .do_cpu_ftr_fixups
1887
e58c3495 1888 LOAD_REG_IMMEDIATE(r26, boot_cpuid)
14cf11af
PM		 1889 lwz r26,0(r26)
1890
e58c3495 1891 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1892 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1893 add r13,r13,r24 /* for this processor. */
b5bbeb23 1894 mtspr SPRN_SPRG3,r13
14cf11af
PM		 1895
1896 /* ptr to current */
e58c3495 1897 LOAD_REG_IMMEDIATE(r4, init_task)
14cf11af
PM		 1898 std r4,PACACURRENT(r13)
1899
1900 /* Load the TOC */
1901 ld r2,PACATOC(r13)
1902 std r1,PACAKSAVE(r13)
1903
1904 bl .setup_system
1905
1906 /* Load up the kernel context */
19075:
1908#ifdef DO_SOFT_DISABLE
1909 li r5,0
1910 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1911 mfmsr r5
1912 ori r5,r5,MSR_EE /* Hard Enabled */
1913 mtmsrd r5
1914#endif
1915
1916 bl .start_kernel
1917
f1870f77
AB		 1918 /* Not reached */
1919 BUG_OPCODE
14cf11af 1920
14cf11af
PM		 1921/*
1922 * We put a few things here that have to be page-aligned.
1923 * This stuff goes at the beginning of the bss, which is page-aligned.
1924 */
1925 .section ".bss"
1926
1927 .align PAGE_SHIFT
1928
1929 .globl empty_zero_page
1930empty_zero_page:
1931 .space PAGE_SIZE
1932
1933 .globl swapper_pg_dir
1934swapper_pg_dir:
1935 .space PAGE_SIZE
1936
1937/*
1938 * This space gets a copy of optional info passed to us by the bootstrap
1939 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1940 */
1941 .globl cmd_line
1942cmd_line:
1943 .space COMMAND_LINE_SIZE
kernel source for telekom puls (alcatel/mediatek)