Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
b5bbeb23 | 26 | #include <asm/reg.h> |
14cf11af PM |
27 | #include <asm/page.h> |
28 | #include <asm/mmu.h> | |
14cf11af PM |
29 | #include <asm/ppc_asm.h> |
30 | #include <asm/asm-offsets.h> | |
31 | #include <asm/bug.h> | |
32 | #include <asm/cputable.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/hvcall.h> | |
c43a55ff | 35 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 36 | #include <asm/thread_info.h> |
3f639ee8 | 37 | #include <asm/firmware.h> |
16a15a30 | 38 | #include <asm/page_64.h> |
945feb17 | 39 | #include <asm/irqflags.h> |
14cf11af | 40 | |
0ebc4cda BH |
41 | /* The physical memory is layed out such that the secondary processor |
42 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow | |
43 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
44 | */ |
45 | ||
46 | /* | |
47 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
48 | * |
49 | * For pSeries or server processors: | |
14cf11af PM |
50 | * 1. The MMU is off & open firmware is running in real mode. |
51 | * 2. The kernel is entered at __start | |
52 | * | |
53 | * For iSeries: | |
54 | * 1. The MMU is on (as it always is for iSeries) | |
55 | * 2. The kernel is entered at system_reset_iSeries | |
0ebc4cda BH |
56 | * |
57 | * For Book3E processors: | |
58 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
59 | * 2. The kernel is entered at __start | |
14cf11af PM |
60 | */ |
61 | ||
62 | .text | |
63 | .globl _stext | |
64 | _stext: | |
14cf11af PM |
65 | _GLOBAL(__start) |
66 | /* NOP this out unconditionally */ | |
67 | BEGIN_FTR_SECTION | |
b85a046a | 68 | b .__start_initialization_multiplatform |
14cf11af | 69 | END_FTR_SECTION(0, 1) |
14cf11af PM |
70 | |
71 | /* Catch branch to 0 in real mode */ | |
72 | trap | |
73 | ||
1f6a93e4 PM |
74 | /* Secondary processors spin on this value until it becomes nonzero. |
75 | * When it does it contains the real address of the descriptor | |
76 | * of the function that the cpu should jump to to continue | |
77 | * initialization. | |
78 | */ | |
14cf11af PM |
79 | .globl __secondary_hold_spinloop |
80 | __secondary_hold_spinloop: | |
81 | .llong 0x0 | |
82 | ||
83 | /* Secondary processors write this value with their cpu # */ | |
84 | /* after they enter the spin loop immediately below. */ | |
85 | .globl __secondary_hold_acknowledge | |
86 | __secondary_hold_acknowledge: | |
87 | .llong 0x0 | |
88 | ||
1dce0e30 ME |
89 | #ifdef CONFIG_PPC_ISERIES |
90 | /* | |
91 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
92 | * This is required by the hypervisor | |
93 | */ | |
94 | . = 0x20 | |
95 | .llong hvReleaseData-KERNELBASE | |
96 | #endif /* CONFIG_PPC_ISERIES */ | |
97 | ||
8b8b0cc1 MM |
98 | #ifdef CONFIG_CRASH_DUMP |
99 | /* This flag is set to 1 by a loader if the kernel should run | |
100 | * at the loaded address instead of the linked address. This | |
101 | * is used by kexec-tools to keep the the kdump kernel in the | |
102 | * crash_kernel region. The loader is responsible for | |
103 | * observing the alignment requirement. | |
104 | */ | |
105 | /* Do not move this variable as kexec-tools knows about it. */ | |
106 | . = 0x5c | |
107 | .globl __run_at_load | |
108 | __run_at_load: | |
109 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
110 | #endif | |
111 | ||
14cf11af PM |
112 | . = 0x60 |
113 | /* | |
75423b7b GL |
114 | * The following code is used to hold secondary processors |
115 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
116 | * before the bulk of the kernel has been relocated. This code |
117 | * is relocated to physical address 0x60 before prom_init is run. | |
118 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
119 | * Use .globl here not _GLOBAL because we want __secondary_hold |
120 | * to be the actual text address, not a descriptor. | |
14cf11af | 121 | */ |
1f6a93e4 PM |
122 | .globl __secondary_hold |
123 | __secondary_hold: | |
2d27cfd3 | 124 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
125 | mfmsr r24 |
126 | ori r24,r24,MSR_RI | |
127 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 128 | #endif |
f1870f77 | 129 | /* Grab our physical cpu number */ |
14cf11af PM |
130 | mr r24,r3 |
131 | ||
132 | /* Tell the master cpu we're here */ | |
133 | /* Relocation is off & we are located at an address less */ | |
134 | /* than 0x100, so only need to grab low order offset. */ | |
e31aa453 | 135 | std r24,__secondary_hold_acknowledge-_stext(0) |
14cf11af PM |
136 | sync |
137 | ||
138 | /* All secondary cpus wait here until told to start. */ | |
e31aa453 | 139 | 100: ld r4,__secondary_hold_spinloop-_stext(0) |
1f6a93e4 PM |
140 | cmpdi 0,r4,0 |
141 | beq 100b | |
14cf11af | 142 | |
f1870f77 | 143 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
1f6a93e4 | 144 | ld r4,0(r4) /* deref function descriptor */ |
758438a7 | 145 | mtctr r4 |
14cf11af | 146 | mr r3,r24 |
2d27cfd3 | 147 | li r4,0 |
758438a7 | 148 | bctr |
14cf11af PM |
149 | #else |
150 | BUG_OPCODE | |
151 | #endif | |
14cf11af PM |
152 | |
153 | /* This value is used to mark exception frames on the stack. */ | |
154 | .section ".toc","aw" | |
155 | exception_marker: | |
156 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
157 | .text | |
158 | ||
14cf11af | 159 | /* |
0ebc4cda BH |
160 | * On server, we include the exception vectors code here as it |
161 | * relies on absolute addressing which is only possible within | |
162 | * this compilation unit | |
3c726f8d | 163 | */ |
0ebc4cda BH |
164 | #ifdef CONFIG_PPC_BOOK3S |
165 | #include "exceptions-64s.S" | |
1f6a93e4 | 166 | #endif |
3c726f8d | 167 | |
2d27cfd3 BH |
168 | _GLOBAL(generic_secondary_thread_init) |
169 | mr r24,r3 | |
170 | ||
171 | /* turn on 64-bit mode */ | |
172 | bl .enable_64b_mode | |
173 | ||
174 | /* get a valid TOC pointer, wherever we're mapped at */ | |
175 | bl .relative_toc | |
176 | ||
177 | #ifdef CONFIG_PPC_BOOK3E | |
178 | /* Book3E initialization */ | |
179 | mr r3,r24 | |
180 | bl .book3e_secondary_thread_init | |
181 | #endif | |
182 | b generic_secondary_common_init | |
14cf11af PM |
183 | |
184 | /* | |
f39b7a55 OJ |
185 | * On pSeries and most other platforms, secondary processors spin |
186 | * in the following code. | |
14cf11af | 187 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
188 | * |
189 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
190 | * this core already exists (setup via some other mechanism such | |
191 | * as SCOM before entry). | |
14cf11af | 192 | */ |
f39b7a55 | 193 | _GLOBAL(generic_secondary_smp_init) |
14cf11af | 194 | mr r24,r3 |
2d27cfd3 BH |
195 | mr r25,r4 |
196 | ||
14cf11af PM |
197 | /* turn on 64-bit mode */ |
198 | bl .enable_64b_mode | |
14cf11af | 199 | |
2d27cfd3 | 200 | /* get a valid TOC pointer, wherever we're mapped at */ |
e31aa453 PM |
201 | bl .relative_toc |
202 | ||
2d27cfd3 BH |
203 | #ifdef CONFIG_PPC_BOOK3E |
204 | /* Book3E initialization */ | |
205 | mr r3,r24 | |
206 | mr r4,r25 | |
207 | bl .book3e_secondary_core_init | |
208 | #endif | |
209 | ||
210 | generic_secondary_common_init: | |
14cf11af PM |
211 | /* Set up a paca value for this processor. Since we have the |
212 | * physical cpu id in r24, we need to search the pacas to find | |
213 | * which logical id maps to our physical one. | |
214 | */ | |
e31aa453 | 215 | LOAD_REG_ADDR(r13, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
216 | li r5,0 /* logical cpu id */ |
217 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
218 | cmpw r6,r24 /* Compare to our id */ | |
219 | beq 2f | |
220 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
221 | addi r5,r5,1 | |
222 | cmpwi r5,NR_CPUS | |
223 | blt 1b | |
224 | ||
225 | mr r3,r24 /* not found, copy phys to r3 */ | |
226 | b .kexec_wait /* next kernel might do better */ | |
227 | ||
ee43eb78 | 228 | 2: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */ |
2d27cfd3 BH |
229 | #ifdef CONFIG_PPC_BOOK3E |
230 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
231 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
232 | #endif | |
233 | ||
14cf11af PM |
234 | /* From now on, r24 is expected to be logical cpuid */ |
235 | mr r24,r5 | |
236 | 3: HMT_LOW | |
237 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
238 | /* start. */ | |
14cf11af | 239 | |
f39b7a55 OJ |
240 | #ifndef CONFIG_SMP |
241 | b 3b /* Never go on non-SMP */ | |
242 | #else | |
243 | cmpwi 0,r23,0 | |
244 | beq 3b /* Loop until told to go */ | |
245 | ||
b6f6b98a SR |
246 | sync /* order paca.run and cur_cpu_spec */ |
247 | ||
f39b7a55 | 248 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 249 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 OJ |
250 | ld r23,0(r23) |
251 | ld r23,CPU_SPEC_RESTORE(r23) | |
252 | cmpdi 0,r23,0 | |
253 | beq 4f | |
254 | ld r23,0(r23) | |
255 | mtctr r23 | |
256 | bctrl | |
257 | ||
258 | 4: /* Create a temp kernel stack for use before relocation is on. */ | |
14cf11af PM |
259 | ld r1,PACAEMERGSP(r13) |
260 | subi r1,r1,STACK_FRAME_OVERHEAD | |
261 | ||
c705677e | 262 | b __secondary_start |
14cf11af | 263 | #endif |
14cf11af | 264 | |
e31aa453 PM |
265 | /* |
266 | * Turn the MMU off. | |
267 | * Assumes we're mapped EA == RA if the MMU is on. | |
268 | */ | |
2d27cfd3 | 269 | #ifdef CONFIG_PPC_BOOK3S |
14cf11af PM |
270 | _STATIC(__mmu_off) |
271 | mfmsr r3 | |
272 | andi. r0,r3,MSR_IR|MSR_DR | |
273 | beqlr | |
e31aa453 | 274 | mflr r4 |
14cf11af PM |
275 | andc r3,r3,r0 |
276 | mtspr SPRN_SRR0,r4 | |
277 | mtspr SPRN_SRR1,r3 | |
278 | sync | |
279 | rfid | |
280 | b . /* prevent speculative execution */ | |
2d27cfd3 | 281 | #endif |
14cf11af PM |
282 | |
283 | ||
284 | /* | |
285 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
286 | * depending on the value of r5. | |
287 | * | |
288 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
289 | * in r3...r7 | |
290 | * | |
291 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
292 | * DT block, r4 is a physical pointer to the kernel itself | |
293 | * | |
294 | */ | |
295 | _GLOBAL(__start_initialization_multiplatform) | |
e31aa453 PM |
296 | /* Make sure we are running in 64 bits mode */ |
297 | bl .enable_64b_mode | |
298 | ||
299 | /* Get TOC pointer (current runtime address) */ | |
300 | bl .relative_toc | |
301 | ||
302 | /* find out where we are now */ | |
303 | bcl 20,31,$+4 | |
304 | 0: mflr r26 /* r26 = runtime addr here */ | |
305 | addis r26,r26,(_stext - 0b)@ha | |
306 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
307 | ||
14cf11af PM |
308 | /* |
309 | * Are we booted from a PROM Of-type client-interface ? | |
310 | */ | |
311 | cmpldi cr0,r5,0 | |
939e60f6 SR |
312 | beq 1f |
313 | b .__boot_from_prom /* yes -> prom */ | |
314 | 1: | |
14cf11af PM |
315 | /* Save parameters */ |
316 | mr r31,r3 | |
317 | mr r30,r4 | |
318 | ||
2d27cfd3 BH |
319 | #ifdef CONFIG_PPC_BOOK3E |
320 | bl .start_initialization_book3e | |
321 | b .__after_prom_start | |
322 | #else | |
14cf11af | 323 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
324 | mfspr r0,SPRN_PVR |
325 | srwi r0,r0,16 | |
326 | cmpwi r0,0x39 /* 970 */ | |
327 | beq 1f | |
328 | cmpwi r0,0x3c /* 970FX */ | |
329 | beq 1f | |
330 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
331 | beq 1f |
332 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 OJ |
333 | bne 2f |
334 | 1: bl .__cpu_preinit_ppc970 | |
335 | 2: | |
14cf11af | 336 | |
e31aa453 | 337 | /* Switch off MMU if not already off */ |
14cf11af PM |
338 | bl .__mmu_off |
339 | b .__after_prom_start | |
2d27cfd3 | 340 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 341 | |
939e60f6 | 342 | _INIT_STATIC(__boot_from_prom) |
28794d34 | 343 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
344 | /* Save parameters */ |
345 | mr r31,r3 | |
346 | mr r30,r4 | |
347 | mr r29,r5 | |
348 | mr r28,r6 | |
349 | mr r27,r7 | |
350 | ||
6088857b OH |
351 | /* |
352 | * Align the stack to 16-byte boundary | |
353 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 354 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 355 | */ |
c05b4770 LT |
356 | rldicr r1,r1,0,59 |
357 | ||
549e8152 PM |
358 | #ifdef CONFIG_RELOCATABLE |
359 | /* Relocate code for where we are now */ | |
360 | mr r3,r26 | |
361 | bl .relocate | |
362 | #endif | |
363 | ||
14cf11af PM |
364 | /* Restore parameters */ |
365 | mr r3,r31 | |
366 | mr r4,r30 | |
367 | mr r5,r29 | |
368 | mr r6,r28 | |
369 | mr r7,r27 | |
370 | ||
371 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 372 | mr r8,r26 |
14cf11af | 373 | bl .prom_init |
28794d34 BH |
374 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
375 | ||
376 | /* We never return. We also hit that trap if trying to boot | |
377 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
378 | trap |
379 | ||
14cf11af | 380 | _STATIC(__after_prom_start) |
549e8152 PM |
381 | #ifdef CONFIG_RELOCATABLE |
382 | /* process relocations for the final address of the kernel */ | |
383 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
384 | sldi r25,r25,32 | |
54622f10 | 385 | #ifdef CONFIG_CRASH_DUMP |
8b8b0cc1 MM |
386 | lwz r7,__run_at_load-_stext(r26) |
387 | cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ | |
54622f10 MK |
388 | bne 1f |
389 | add r25,r25,r26 | |
390 | #endif | |
391 | 1: mr r3,r25 | |
549e8152 PM |
392 | bl .relocate |
393 | #endif | |
14cf11af PM |
394 | |
395 | /* | |
e31aa453 | 396 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
397 | * This will leave some code in the first 256B of |
398 | * real memory, which are reserved for software use. | |
14cf11af PM |
399 | * |
400 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 401 | */ |
549e8152 | 402 | li r3,0 /* target addr */ |
2d27cfd3 BH |
403 | #ifdef CONFIG_PPC_BOOK3E |
404 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ | |
405 | #endif | |
549e8152 | 406 | mr. r4,r26 /* In some cases the loader may */ |
e31aa453 | 407 | beq 9f /* have already put us at zero */ |
14cf11af PM |
408 | li r6,0x100 /* Start offset, the first 0x100 */ |
409 | /* bytes were copied earlier. */ | |
2d27cfd3 BH |
410 | #ifdef CONFIG_PPC_BOOK3E |
411 | tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ | |
412 | #endif | |
14cf11af | 413 | |
54622f10 MK |
414 | #ifdef CONFIG_CRASH_DUMP |
415 | /* | |
416 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 417 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
418 | * kernel, otherwise it will be moved to PHYSICAL_START |
419 | */ | |
8b8b0cc1 MM |
420 | lwz r7,__run_at_load-_stext(r26) |
421 | cmplwi cr0,r7,1 | |
54622f10 MK |
422 | bne 3f |
423 | ||
424 | li r5,__end_interrupts - _stext /* just copy interrupts */ | |
425 | b 5f | |
426 | 3: | |
427 | #endif | |
428 | lis r5,(copy_to_here - _stext)@ha | |
429 | addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ | |
430 | ||
14cf11af PM |
431 | bl .copy_and_flush /* copy the first n bytes */ |
432 | /* this includes the code being */ | |
433 | /* executed here. */ | |
e31aa453 PM |
434 | addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ |
435 | addi r8,r8,(4f - _stext)@l /* that we just made */ | |
436 | mtctr r8 | |
14cf11af PM |
437 | bctr |
438 | ||
54622f10 MK |
439 | p_end: .llong _end - _stext |
440 | ||
e31aa453 PM |
441 | 4: /* Now copy the rest of the kernel up to _end */ |
442 | addis r5,r26,(p_end - _stext)@ha | |
443 | ld r5,(p_end - _stext)@l(r5) /* get _end */ | |
54622f10 | 444 | 5: bl .copy_and_flush /* copy the rest */ |
e31aa453 PM |
445 | |
446 | 9: b .start_here_multiplatform | |
447 | ||
14cf11af PM |
448 | /* |
449 | * Copy routine used to copy the kernel to start at physical address 0 | |
450 | * and flush and invalidate the caches as needed. | |
451 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
452 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
453 | * | |
454 | * Note: this routine *only* clobbers r0, r6 and lr | |
455 | */ | |
456 | _GLOBAL(copy_and_flush) | |
457 | addi r5,r5,-8 | |
458 | addi r6,r6,-8 | |
5a2fe38d | 459 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
460 | /* denominator cache line */ |
461 | /* size. This results in */ | |
462 | /* extra cache line flushes */ | |
463 | /* but operation is correct. */ | |
464 | /* Can't get cache line size */ | |
465 | /* from NACA as it is being */ | |
466 | /* moved too. */ | |
467 | ||
468 | mtctr r0 /* put # words/line in ctr */ | |
469 | 3: addi r6,r6,8 /* copy a cache line */ | |
470 | ldx r0,r6,r4 | |
471 | stdx r0,r6,r3 | |
472 | bdnz 3b | |
473 | dcbst r6,r3 /* write it to memory */ | |
474 | sync | |
475 | icbi r6,r3 /* flush the icache line */ | |
476 | cmpld 0,r6,r5 | |
477 | blt 4b | |
478 | sync | |
479 | addi r5,r5,8 | |
480 | addi r6,r6,8 | |
481 | blr | |
482 | ||
483 | .align 8 | |
484 | copy_to_here: | |
485 | ||
486 | #ifdef CONFIG_SMP | |
487 | #ifdef CONFIG_PPC_PMAC | |
488 | /* | |
489 | * On PowerMac, secondary processors starts from the reset vector, which | |
490 | * is temporarily turned into a call to one of the functions below. | |
491 | */ | |
492 | .section ".text"; | |
493 | .align 2 ; | |
494 | ||
35499c01 PM |
495 | .globl __secondary_start_pmac_0 |
496 | __secondary_start_pmac_0: | |
497 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
498 | li r24,0 | |
499 | b 1f | |
500 | li r24,1 | |
501 | b 1f | |
502 | li r24,2 | |
503 | b 1f | |
504 | li r24,3 | |
505 | 1: | |
14cf11af PM |
506 | |
507 | _GLOBAL(pmac_secondary_start) | |
508 | /* turn on 64-bit mode */ | |
509 | bl .enable_64b_mode | |
14cf11af | 510 | |
c478b581 BH |
511 | li r0,0 |
512 | mfspr r3,SPRN_HID4 | |
513 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
514 | sync | |
515 | mtspr SPRN_HID4,r3 | |
516 | isync | |
517 | sync | |
518 | slbia | |
519 | ||
e31aa453 PM |
520 | /* get TOC pointer (real address) */ |
521 | bl .relative_toc | |
522 | ||
14cf11af | 523 | /* Copy some CPU settings from CPU 0 */ |
f39b7a55 | 524 | bl .__restore_cpu_ppc970 |
14cf11af PM |
525 | |
526 | /* pSeries do that early though I don't think we really need it */ | |
527 | mfmsr r3 | |
528 | ori r3,r3,MSR_RI | |
529 | mtmsrd r3 /* RI on */ | |
530 | ||
531 | /* Set up a paca value for this processor. */ | |
e31aa453 PM |
532 | LOAD_REG_ADDR(r4,paca) /* Get base vaddr of paca array */ |
533 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ | |
14cf11af | 534 | add r13,r13,r4 /* for this processor. */ |
ee43eb78 | 535 | mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ |
14cf11af PM |
536 | |
537 | /* Create a temp kernel stack for use before relocation is on. */ | |
538 | ld r1,PACAEMERGSP(r13) | |
539 | subi r1,r1,STACK_FRAME_OVERHEAD | |
540 | ||
c705677e | 541 | b __secondary_start |
14cf11af PM |
542 | |
543 | #endif /* CONFIG_PPC_PMAC */ | |
544 | ||
545 | /* | |
546 | * This function is called after the master CPU has released the | |
547 | * secondary processors. The execution environment is relocation off. | |
548 | * The paca for this processor has the following fields initialized at | |
549 | * this point: | |
550 | * 1. Processor number | |
551 | * 2. Segment table pointer (virtual address) | |
552 | * On entry the following are set: | |
ee43eb78 BH |
553 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries |
554 | * r24 = cpu# (in Linux terms) | |
555 | * r13 = paca virtual address | |
556 | * SPRG_PACA = paca virtual address | |
14cf11af | 557 | */ |
2d27cfd3 BH |
558 | .section ".text"; |
559 | .align 2 ; | |
560 | ||
fc68e869 | 561 | .globl __secondary_start |
c705677e | 562 | __secondary_start: |
799d6046 PM |
563 | /* Set thread priority to MEDIUM */ |
564 | HMT_MEDIUM | |
14cf11af | 565 | |
799d6046 PM |
566 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ |
567 | bl .early_setup_secondary | |
14cf11af PM |
568 | |
569 | /* Initialize the kernel stack. Just a repeat for iSeries. */ | |
e58c3495 | 570 | LOAD_REG_ADDR(r3, current_set) |
14cf11af PM |
571 | sldi r28,r24,3 /* get current_set[cpu#] */ |
572 | ldx r1,r3,r28 | |
573 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
574 | std r1,PACAKSAVE(r13) | |
575 | ||
799d6046 | 576 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
577 | li r7,0 |
578 | mtlr r7 | |
579 | ||
580 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
581 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
582 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
d04c56f7 | 583 | #ifdef CONFIG_PPC_ISERIES |
3f639ee8 | 584 | BEGIN_FW_FTR_SECTION |
14cf11af | 585 | ori r4,r4,MSR_EE |
ff3da2e0 BH |
586 | li r8,1 |
587 | stb r8,PACAHARDIRQEN(r13) | |
3f639ee8 | 588 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 589 | #endif |
d04c56f7 | 590 | BEGIN_FW_FTR_SECTION |
d04c56f7 PM |
591 | stb r7,PACAHARDIRQEN(r13) |
592 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
ff3da2e0 | 593 | stb r7,PACASOFTIRQEN(r13) |
d04c56f7 | 594 | |
b5bbeb23 PM |
595 | mtspr SPRN_SRR0,r3 |
596 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 597 | RFI |
14cf11af PM |
598 | b . /* prevent speculative execution */ |
599 | ||
600 | /* | |
601 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
602 | * zero the stack back-chain pointer and get the TOC virtual address |
603 | * before going into C code. | |
14cf11af PM |
604 | */ |
605 | _GLOBAL(start_secondary_prolog) | |
e31aa453 | 606 | ld r2,PACATOC(r13) |
14cf11af PM |
607 | li r3,0 |
608 | std r3,0(r1) /* Zero the stack frame pointer */ | |
609 | bl .start_secondary | |
799d6046 | 610 | b . |
14cf11af PM |
611 | #endif |
612 | ||
613 | /* | |
614 | * This subroutine clobbers r11 and r12 | |
615 | */ | |
616 | _GLOBAL(enable_64b_mode) | |
617 | mfmsr r11 /* grab the current MSR */ | |
2d27cfd3 BH |
618 | #ifdef CONFIG_PPC_BOOK3E |
619 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
620 | mtmsr r11 | |
621 | #else /* CONFIG_PPC_BOOK3E */ | |
e31aa453 PM |
622 | li r12,(MSR_SF | MSR_ISF)@highest |
623 | sldi r12,r12,48 | |
14cf11af PM |
624 | or r11,r11,r12 |
625 | mtmsrd r11 | |
626 | isync | |
2d27cfd3 | 627 | #endif |
14cf11af PM |
628 | blr |
629 | ||
e31aa453 PM |
630 | /* |
631 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
632 | * by the toolchain). It computes the correct value for wherever we | |
633 | * are running at the moment, using position-independent code. | |
634 | */ | |
635 | _GLOBAL(relative_toc) | |
636 | mflr r0 | |
637 | bcl 20,31,$+4 | |
638 | 0: mflr r9 | |
639 | ld r2,(p_toc - 0b)(r9) | |
640 | add r2,r2,r9 | |
641 | mtlr r0 | |
642 | blr | |
643 | ||
644 | p_toc: .llong __toc_start + 0x8000 - 0b | |
645 | ||
14cf11af PM |
646 | /* |
647 | * This is where the main kernel code starts. | |
648 | */ | |
939e60f6 | 649 | _INIT_STATIC(start_here_multiplatform) |
e31aa453 PM |
650 | /* set up the TOC (real address) */ |
651 | bl .relative_toc | |
14cf11af PM |
652 | |
653 | /* Clear out the BSS. It may have been done in prom_init, | |
654 | * already but that's irrelevant since prom_init will soon | |
655 | * be detached from the kernel completely. Besides, we need | |
656 | * to clear it now for kexec-style entry. | |
657 | */ | |
e31aa453 PM |
658 | LOAD_REG_ADDR(r11,__bss_stop) |
659 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
660 | sub r11,r11,r8 /* bss size */ |
661 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 662 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
663 | beq 4f |
664 | addi r8,r8,-8 | |
665 | li r0,0 | |
666 | mtctr r11 /* zero this many doublewords */ | |
667 | 3: stdu r0,8(r8) | |
668 | bdnz 3b | |
669 | 4: | |
670 | ||
2d27cfd3 | 671 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
672 | mfmsr r6 |
673 | ori r6,r6,MSR_RI | |
674 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 675 | #endif |
14cf11af | 676 | |
549e8152 PM |
677 | #ifdef CONFIG_RELOCATABLE |
678 | /* Save the physical address we're running at in kernstart_addr */ | |
679 | LOAD_REG_ADDR(r4, kernstart_addr) | |
680 | clrldi r0,r25,2 | |
681 | std r0,0(r4) | |
682 | #endif | |
683 | ||
e31aa453 | 684 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
685 | /* pointing to the real addr of the kernel stack. This is */ |
686 | /* all done to support the C function call below which sets */ | |
687 | /* up the htab. This is done because we have relocated the */ | |
688 | /* kernel but are still running in real mode. */ | |
689 | ||
e31aa453 | 690 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 691 | |
e31aa453 | 692 | /* set up a stack pointer */ |
14cf11af PM |
693 | addi r1,r3,THREAD_SIZE |
694 | li r0,0 | |
695 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
696 | ||
14cf11af PM |
697 | /* Do very early kernel initializations, including initial hash table, |
698 | * stab and slb setup before we turn on relocation. */ | |
699 | ||
700 | /* Restore parameters passed from prom_init/kexec */ | |
701 | mr r3,r31 | |
ee43eb78 | 702 | bl .early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 703 | |
e31aa453 PM |
704 | LOAD_REG_ADDR(r3, .start_here_common) |
705 | ld r4,PACAKMSR(r13) | |
b5bbeb23 PM |
706 | mtspr SPRN_SRR0,r3 |
707 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 708 | RFI |
14cf11af | 709 | b . /* prevent speculative execution */ |
14cf11af PM |
710 | |
711 | /* This is where all platforms converge execution */ | |
fc68e869 | 712 | _INIT_GLOBAL(start_here_common) |
14cf11af | 713 | /* relocation is on at this point */ |
e31aa453 | 714 | std r1,PACAKSAVE(r13) |
14cf11af | 715 | |
e31aa453 | 716 | /* Load the TOC (virtual address) */ |
14cf11af | 717 | ld r2,PACATOC(r13) |
14cf11af PM |
718 | |
719 | bl .setup_system | |
720 | ||
721 | /* Load up the kernel context */ | |
722 | 5: | |
14cf11af | 723 | li r5,0 |
d04c56f7 PM |
724 | stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ |
725 | #ifdef CONFIG_PPC_ISERIES | |
726 | BEGIN_FW_FTR_SECTION | |
14cf11af | 727 | mfmsr r5 |
ff3da2e0 | 728 | ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ |
14cf11af | 729 | mtmsrd r5 |
ff3da2e0 | 730 | li r5,1 |
3f639ee8 | 731 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 732 | #endif |
ff3da2e0 | 733 | stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ |
14cf11af | 734 | |
ff3da2e0 | 735 | bl .start_kernel |
14cf11af | 736 | |
f1870f77 AB |
737 | /* Not reached */ |
738 | BUG_OPCODE | |
14cf11af | 739 | |
14cf11af PM |
740 | /* |
741 | * We put a few things here that have to be page-aligned. | |
742 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
743 | */ | |
744 | .section ".bss" | |
745 | ||
746 | .align PAGE_SHIFT | |
747 | ||
748 | .globl empty_zero_page | |
749 | empty_zero_page: | |
750 | .space PAGE_SIZE | |
751 | ||
752 | .globl swapper_pg_dir | |
753 | swapper_pg_dir: | |
ee7a76da | 754 | .space PGD_TABLE_SIZE |