Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
5 | * Initial PowerPC version. | |
6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Rewritten for PReP | |
8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
9 | * Low-level exception handers, MMU support, and rewrite. | |
10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> | |
11 | * PowerPC 8xx modifications. | |
12 | * Copyright (c) 1998-1999 TiVo, Inc. | |
13 | * PowerPC 403GCX modifications. | |
14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
15 | * PowerPC 403GCX/405GP modifications. | |
16 | * Copyright 2000 MontaVista Software Inc. | |
17 | * PPC405 modifications | |
18 | * PowerPC 403GCX/405GP modifications. | |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
22 | * Copyright 2002-2005 MontaVista Software, Inc. | |
23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> | |
24 | * | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License as published by the | |
27 | * Free Software Foundation; either version 2 of the License, or (at your | |
28 | * option) any later version. | |
29 | */ | |
30 | ||
14cf11af PM |
31 | #include <asm/processor.h> |
32 | #include <asm/page.h> | |
33 | #include <asm/mmu.h> | |
34 | #include <asm/pgtable.h> | |
14cf11af PM |
35 | #include <asm/cputable.h> |
36 | #include <asm/thread_info.h> | |
37 | #include <asm/ppc_asm.h> | |
38 | #include <asm/asm-offsets.h> | |
39 | #include "head_booke.h" | |
40 | ||
41 | ||
42 | /* As with the other PowerPC ports, it is expected that when code | |
43 | * execution begins here, the following registers contain valid, yet | |
44 | * optional, information: | |
45 | * | |
46 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
47 | * r4 - Starting address of the init RAM disk | |
48 | * r5 - Ending address of the init RAM disk | |
49 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
50 | * r7 - End of kernel command line string | |
51 | * | |
52 | */ | |
748a7683 KG |
53 | .section .text.head, "ax" |
54 | _ENTRY(_stext); | |
55 | _ENTRY(_start); | |
14cf11af PM |
56 | /* |
57 | * Reserve a word at a fixed location to store the address | |
58 | * of abatron_pteptrs | |
59 | */ | |
60 | nop | |
61 | /* | |
62 | * Save parameters we are passed | |
63 | */ | |
64 | mr r31,r3 | |
65 | mr r30,r4 | |
66 | mr r29,r5 | |
67 | mr r28,r6 | |
68 | mr r27,r7 | |
69 | li r24,0 /* CPU number */ | |
70 | ||
9dce3ce5 BH |
71 | /* |
72 | * In case the firmware didn't do it, we apply some workarounds | |
73 | * that are good for all 440 core variants here | |
74 | */ | |
75 | mfspr r3,SPRN_CCR0 | |
76 | rlwinm r3,r3,0,0,27 /* disable icache prefetch */ | |
77 | isync | |
78 | mtspr SPRN_CCR0,r3 | |
79 | isync | |
80 | sync | |
81 | ||
14cf11af PM |
82 | /* |
83 | * Set up the initial MMU state | |
84 | * | |
85 | * We are still executing code at the virtual address | |
86 | * mappings set by the firmware for the base of RAM. | |
87 | * | |
88 | * We first invalidate all TLB entries but the one | |
89 | * we are running from. We then load the KERNELBASE | |
90 | * mappings so we can begin to use kernel addresses | |
91 | * natively and so the interrupt vector locations are | |
92 | * permanently pinned (necessary since Book E | |
93 | * implementations always have translation enabled). | |
94 | * | |
95 | * TODO: Use the known TLB entry we are running from to | |
96 | * determine which physical region we are located | |
97 | * in. This can be used to determine where in RAM | |
98 | * (on a shared CPU system) or PCI memory space | |
99 | * (on a DRAMless system) we are located. | |
100 | * For now, we assume a perfect world which means | |
101 | * we are located at the base of DRAM (physical 0). | |
102 | */ | |
103 | ||
104 | /* | |
105 | * Search TLB for entry that we are currently using. | |
106 | * Invalidate all entries but the one we are using. | |
107 | */ | |
108 | /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ | |
109 | mfspr r3,SPRN_PID /* Get PID */ | |
110 | mfmsr r4 /* Get MSR */ | |
111 | andi. r4,r4,MSR_IS@l /* TS=1? */ | |
112 | beq wmmucr /* If not, leave STS=0 */ | |
113 | oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ | |
114 | wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ | |
115 | sync | |
116 | ||
117 | bl invstr /* Find our address */ | |
118 | invstr: mflr r5 /* Make it accessible */ | |
119 | tlbsx r23,0,r5 /* Find entry we are in */ | |
120 | li r4,0 /* Start at TLB entry 0 */ | |
121 | li r3,0 /* Set PAGEID inval value */ | |
122 | 1: cmpw r23,r4 /* Is this our entry? */ | |
123 | beq skpinv /* If so, skip the inval */ | |
124 | tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ | |
125 | skpinv: addi r4,r4,1 /* Increment */ | |
126 | cmpwi r4,64 /* Are we done? */ | |
127 | bne 1b /* If not, repeat */ | |
128 | isync /* If so, context change */ | |
129 | ||
130 | /* | |
131 | * Configure and load pinned entry into TLB slot 63. | |
132 | */ | |
133 | ||
57d7909e DG |
134 | lis r3,PAGE_OFFSET@h |
135 | ori r3,r3,PAGE_OFFSET@l | |
14cf11af PM |
136 | |
137 | /* Kernel is at the base of RAM */ | |
138 | li r4, 0 /* Load the kernel physical address */ | |
139 | ||
140 | /* Load the kernel PID = 0 */ | |
141 | li r0,0 | |
142 | mtspr SPRN_PID,r0 | |
143 | sync | |
144 | ||
145 | /* Initialize MMUCR */ | |
146 | li r5,0 | |
147 | mtspr SPRN_MMUCR,r5 | |
148 | sync | |
149 | ||
150 | /* pageid fields */ | |
151 | clrrwi r3,r3,10 /* Mask off the effective page number */ | |
152 | ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M | |
153 | ||
154 | /* xlat fields */ | |
155 | clrrwi r4,r4,10 /* Mask off the real page number */ | |
156 | /* ERPN is 0 for first 4GB page */ | |
157 | ||
158 | /* attrib fields */ | |
159 | /* Added guarded bit to protect against speculative loads/stores */ | |
160 | li r5,0 | |
161 | ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) | |
162 | ||
163 | li r0,63 /* TLB slot 63 */ | |
164 | ||
165 | tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ | |
166 | tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ | |
167 | tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ | |
168 | ||
169 | /* Force context change */ | |
170 | mfmsr r0 | |
171 | mtspr SPRN_SRR1, r0 | |
172 | lis r0,3f@h | |
173 | ori r0,r0,3f@l | |
174 | mtspr SPRN_SRR0,r0 | |
175 | sync | |
176 | rfi | |
177 | ||
178 | /* If necessary, invalidate original entry we used */ | |
179 | 3: cmpwi r23,63 | |
180 | beq 4f | |
181 | li r6,0 | |
182 | tlbwe r6,r23,PPC44x_TLB_PAGEID | |
183 | isync | |
184 | ||
185 | 4: | |
d9b55a03 DG |
186 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x |
187 | /* Add UART mapping for early debug. */ | |
188 | ||
14cf11af | 189 | /* pageid fields */ |
d9b55a03 DG |
190 | lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h |
191 | ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K | |
14cf11af PM |
192 | |
193 | /* xlat fields */ | |
d9b55a03 DG |
194 | lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h |
195 | ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH | |
14cf11af PM |
196 | |
197 | /* attrib fields */ | |
d9b55a03 DG |
198 | li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G) |
199 | li r0,62 /* TLB slot 0 */ | |
14cf11af | 200 | |
d9b55a03 DG |
201 | tlbwe r3,r0,PPC44x_TLB_PAGEID |
202 | tlbwe r4,r0,PPC44x_TLB_XLAT | |
203 | tlbwe r5,r0,PPC44x_TLB_ATTRIB | |
14cf11af PM |
204 | |
205 | /* Force context change */ | |
206 | isync | |
d9b55a03 | 207 | #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ |
14cf11af PM |
208 | |
209 | /* Establish the interrupt vector offsets */ | |
210 | SET_IVOR(0, CriticalInput); | |
211 | SET_IVOR(1, MachineCheck); | |
212 | SET_IVOR(2, DataStorage); | |
213 | SET_IVOR(3, InstructionStorage); | |
214 | SET_IVOR(4, ExternalInput); | |
215 | SET_IVOR(5, Alignment); | |
216 | SET_IVOR(6, Program); | |
217 | SET_IVOR(7, FloatingPointUnavailable); | |
218 | SET_IVOR(8, SystemCall); | |
219 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
220 | SET_IVOR(10, Decrementer); | |
221 | SET_IVOR(11, FixedIntervalTimer); | |
222 | SET_IVOR(12, WatchdogTimer); | |
223 | SET_IVOR(13, DataTLBError); | |
224 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 225 | SET_IVOR(15, DebugCrit); |
14cf11af PM |
226 | |
227 | /* Establish the interrupt vector base */ | |
228 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
229 | mtspr SPRN_IVPR,r4 | |
230 | ||
14cf11af PM |
231 | /* |
232 | * This is where the main kernel code starts. | |
233 | */ | |
234 | ||
235 | /* ptr to current */ | |
236 | lis r2,init_task@h | |
237 | ori r2,r2,init_task@l | |
238 | ||
239 | /* ptr to current thread */ | |
240 | addi r4,r2,THREAD /* init task's THREAD */ | |
241 | mtspr SPRN_SPRG3,r4 | |
242 | ||
243 | /* stack */ | |
244 | lis r1,init_thread_union@h | |
245 | ori r1,r1,init_thread_union@l | |
246 | li r0,0 | |
247 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
248 | ||
249 | bl early_init | |
250 | ||
251 | /* | |
252 | * Decide what sort of machine this is and initialize the MMU. | |
253 | */ | |
254 | mr r3,r31 | |
255 | mr r4,r30 | |
256 | mr r5,r29 | |
257 | mr r6,r28 | |
258 | mr r7,r27 | |
259 | bl machine_init | |
260 | bl MMU_init | |
261 | ||
262 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
263 | lis r6, swapper_pg_dir@h | |
264 | ori r6, r6, swapper_pg_dir@l | |
265 | lis r5, abatron_pteptrs@h | |
266 | ori r5, r5, abatron_pteptrs@l | |
267 | lis r4, KERNELBASE@h | |
268 | ori r4, r4, KERNELBASE@l | |
269 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
270 | stw r6, 0(r5) | |
271 | ||
272 | /* Let's move on */ | |
273 | lis r4,start_kernel@h | |
274 | ori r4,r4,start_kernel@l | |
275 | lis r3,MSR_KERNEL@h | |
276 | ori r3,r3,MSR_KERNEL@l | |
277 | mtspr SPRN_SRR0,r4 | |
278 | mtspr SPRN_SRR1,r3 | |
279 | rfi /* change context and jump to start_kernel */ | |
280 | ||
281 | /* | |
282 | * Interrupt vector entry code | |
283 | * | |
284 | * The Book E MMUs are always on so we don't need to handle | |
285 | * interrupts in real mode as with previous PPC processors. In | |
286 | * this case we handle interrupts in the kernel virtual address | |
287 | * space. | |
288 | * | |
289 | * Interrupt vectors are dynamically placed relative to the | |
290 | * interrupt prefix as determined by the address of interrupt_base. | |
291 | * The interrupt vectors offsets are programmed using the labels | |
292 | * for each interrupt vector entry. | |
293 | * | |
294 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
295 | * We align on a 32 byte cache line boundary for good measure. | |
296 | */ | |
297 | ||
298 | interrupt_base: | |
299 | /* Critical Input Interrupt */ | |
dc1c1ca3 | 300 | CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) |
14cf11af PM |
301 | |
302 | /* Machine Check Interrupt */ | |
dc1c1ca3 | 303 | CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
47c0bd1a | 304 | MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception) |
14cf11af PM |
305 | |
306 | /* Data Storage Interrupt */ | |
1bc54c03 | 307 | DATA_STORAGE_EXCEPTION |
14cf11af | 308 | |
1bc54c03 | 309 | /* Instruction Storage Interrupt */ |
14cf11af PM |
310 | INSTRUCTION_STORAGE_EXCEPTION |
311 | ||
312 | /* External Input Interrupt */ | |
313 | EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) | |
314 | ||
315 | /* Alignment Interrupt */ | |
316 | ALIGNMENT_EXCEPTION | |
317 | ||
318 | /* Program Interrupt */ | |
319 | PROGRAM_EXCEPTION | |
320 | ||
321 | /* Floating Point Unavailable Interrupt */ | |
322 | #ifdef CONFIG_PPC_FPU | |
323 | FP_UNAVAILABLE_EXCEPTION | |
324 | #else | |
dc1c1ca3 | 325 | EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af | 326 | #endif |
14cf11af PM |
327 | /* System Call Interrupt */ |
328 | START_EXCEPTION(SystemCall) | |
329 | NORMAL_EXCEPTION_PROLOG | |
330 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) | |
331 | ||
332 | /* Auxillary Processor Unavailable Interrupt */ | |
dc1c1ca3 | 333 | EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
334 | |
335 | /* Decrementer Interrupt */ | |
336 | DECREMENTER_EXCEPTION | |
337 | ||
338 | /* Fixed Internal Timer Interrupt */ | |
339 | /* TODO: Add FIT support */ | |
dc1c1ca3 | 340 | EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
341 | |
342 | /* Watchdog Timer Interrupt */ | |
343 | /* TODO: Add watchdog support */ | |
344 | #ifdef CONFIG_BOOKE_WDT | |
345 | CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException) | |
346 | #else | |
dc1c1ca3 | 347 | CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception) |
14cf11af PM |
348 | #endif |
349 | ||
350 | /* Data TLB Error Interrupt */ | |
351 | START_EXCEPTION(DataTLBError) | |
352 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
353 | mtspr SPRN_SPRG1, r11 | |
354 | mtspr SPRN_SPRG4W, r12 | |
355 | mtspr SPRN_SPRG5W, r13 | |
356 | mfcr r11 | |
357 | mtspr SPRN_SPRG7W, r11 | |
358 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
359 | ||
360 | /* If we are faulting a kernel address, we have to use the | |
361 | * kernel page tables. | |
362 | */ | |
8a13c4f9 | 363 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
364 | cmplw r10, r11 |
365 | blt+ 3f | |
366 | lis r11, swapper_pg_dir@h | |
367 | ori r11, r11, swapper_pg_dir@l | |
368 | ||
369 | mfspr r12,SPRN_MMUCR | |
370 | rlwinm r12,r12,0,0,23 /* Clear TID */ | |
371 | ||
372 | b 4f | |
373 | ||
374 | /* Get the PGD for the current thread */ | |
375 | 3: | |
376 | mfspr r11,SPRN_SPRG3 | |
377 | lwz r11,PGDIR(r11) | |
378 | ||
379 | /* Load PID into MMUCR TID */ | |
380 | mfspr r12,SPRN_MMUCR | |
381 | mfspr r13,SPRN_PID /* Get PID */ | |
382 | rlwimi r12,r13,0,24,31 /* Set TID */ | |
383 | ||
384 | 4: | |
385 | mtspr SPRN_MMUCR,r12 | |
386 | ||
1bc54c03 BH |
387 | /* Mask of required permission bits. Note that while we |
388 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
389 | * to an RO page is pretty common, we don't do it with | |
390 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
391 | * event so I'd rather take the overhead when it happens | |
392 | * rather than adding an instruction here. We should measure | |
393 | * whether the whole thing is worth it in the first place | |
394 | * as we could avoid loading SPRN_ESR completely in the first | |
395 | * place... | |
396 | * | |
397 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
398 | * place or can we save a couple of instructions here ? | |
399 | */ | |
400 | mfspr r12,SPRN_ESR | |
401 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED | |
402 | rlwimi r13,r12,10,30,30 | |
403 | ||
404 | /* Load the PTE */ | |
14cf11af PM |
405 | rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ |
406 | lwzx r11, r12, r11 /* Get pgd/pmd entry */ | |
407 | rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ | |
408 | beq 2f /* Bail if no table */ | |
409 | ||
410 | rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ | |
1bc54c03 BH |
411 | lwz r11, 0(r12) /* Get high word of pte entry */ |
412 | lwz r12, 4(r12) /* Get low word of pte entry */ | |
14cf11af | 413 | |
1bc54c03 BH |
414 | lis r10,tlb_44x_index@ha |
415 | ||
416 | andc. r13,r13,r12 /* Check permission */ | |
417 | ||
418 | /* Load the next available TLB index */ | |
419 | lwz r13,tlb_44x_index@l(r10) | |
420 | ||
421 | bne 2f /* Bail if permission mismach */ | |
422 | ||
423 | /* Increment, rollover, and store TLB index */ | |
424 | addi r13,r13,1 | |
425 | ||
426 | /* Compare with watermark (instruction gets patched) */ | |
427 | .globl tlb_44x_patch_hwater_D | |
428 | tlb_44x_patch_hwater_D: | |
429 | cmpwi 0,r13,1 /* reserve entries */ | |
430 | ble 5f | |
431 | li r13,0 | |
432 | 5: | |
433 | /* Store the next available TLB index */ | |
434 | stw r13,tlb_44x_index@l(r10) | |
435 | ||
436 | /* Re-load the faulting address */ | |
437 | mfspr r10,SPRN_DEAR | |
14cf11af PM |
438 | |
439 | /* Jump to common tlb load */ | |
440 | b finish_tlb_load | |
441 | ||
442 | 2: | |
443 | /* The bailout. Restore registers to pre-exception conditions | |
444 | * and call the heavyweights to help us out. | |
445 | */ | |
446 | mfspr r11, SPRN_SPRG7R | |
447 | mtcr r11 | |
448 | mfspr r13, SPRN_SPRG5R | |
449 | mfspr r12, SPRN_SPRG4R | |
450 | mfspr r11, SPRN_SPRG1 | |
451 | mfspr r10, SPRN_SPRG0 | |
1bc54c03 | 452 | b DataStorage |
14cf11af PM |
453 | |
454 | /* Instruction TLB Error Interrupt */ | |
455 | /* | |
456 | * Nearly the same as above, except we get our | |
457 | * information from different registers and bailout | |
458 | * to a different point. | |
459 | */ | |
460 | START_EXCEPTION(InstructionTLBError) | |
461 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
462 | mtspr SPRN_SPRG1, r11 | |
463 | mtspr SPRN_SPRG4W, r12 | |
464 | mtspr SPRN_SPRG5W, r13 | |
465 | mfcr r11 | |
466 | mtspr SPRN_SPRG7W, r11 | |
467 | mfspr r10, SPRN_SRR0 /* Get faulting address */ | |
468 | ||
469 | /* If we are faulting a kernel address, we have to use the | |
470 | * kernel page tables. | |
471 | */ | |
8a13c4f9 | 472 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
473 | cmplw r10, r11 |
474 | blt+ 3f | |
475 | lis r11, swapper_pg_dir@h | |
476 | ori r11, r11, swapper_pg_dir@l | |
477 | ||
478 | mfspr r12,SPRN_MMUCR | |
479 | rlwinm r12,r12,0,0,23 /* Clear TID */ | |
480 | ||
481 | b 4f | |
482 | ||
483 | /* Get the PGD for the current thread */ | |
484 | 3: | |
485 | mfspr r11,SPRN_SPRG3 | |
486 | lwz r11,PGDIR(r11) | |
487 | ||
488 | /* Load PID into MMUCR TID */ | |
489 | mfspr r12,SPRN_MMUCR | |
490 | mfspr r13,SPRN_PID /* Get PID */ | |
491 | rlwimi r12,r13,0,24,31 /* Set TID */ | |
492 | ||
493 | 4: | |
494 | mtspr SPRN_MMUCR,r12 | |
495 | ||
1bc54c03 BH |
496 | /* Make up the required permissions */ |
497 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC | |
498 | ||
14cf11af PM |
499 | rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ |
500 | lwzx r11, r12, r11 /* Get pgd/pmd entry */ | |
501 | rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ | |
502 | beq 2f /* Bail if no table */ | |
503 | ||
504 | rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ | |
1bc54c03 BH |
505 | lwz r11, 0(r12) /* Get high word of pte entry */ |
506 | lwz r12, 4(r12) /* Get low word of pte entry */ | |
14cf11af | 507 | |
1bc54c03 BH |
508 | lis r10,tlb_44x_index@ha |
509 | ||
510 | andc. r13,r13,r12 /* Check permission */ | |
511 | ||
512 | /* Load the next available TLB index */ | |
513 | lwz r13,tlb_44x_index@l(r10) | |
514 | ||
515 | bne 2f /* Bail if permission mismach */ | |
516 | ||
517 | /* Increment, rollover, and store TLB index */ | |
518 | addi r13,r13,1 | |
519 | ||
520 | /* Compare with watermark (instruction gets patched) */ | |
521 | .globl tlb_44x_patch_hwater_I | |
522 | tlb_44x_patch_hwater_I: | |
523 | cmpwi 0,r13,1 /* reserve entries */ | |
524 | ble 5f | |
525 | li r13,0 | |
526 | 5: | |
527 | /* Store the next available TLB index */ | |
528 | stw r13,tlb_44x_index@l(r10) | |
529 | ||
530 | /* Re-load the faulting address */ | |
531 | mfspr r10,SPRN_SRR0 | |
14cf11af PM |
532 | |
533 | /* Jump to common TLB load point */ | |
534 | b finish_tlb_load | |
535 | ||
536 | 2: | |
537 | /* The bailout. Restore registers to pre-exception conditions | |
538 | * and call the heavyweights to help us out. | |
539 | */ | |
540 | mfspr r11, SPRN_SPRG7R | |
541 | mtcr r11 | |
542 | mfspr r13, SPRN_SPRG5R | |
543 | mfspr r12, SPRN_SPRG4R | |
544 | mfspr r11, SPRN_SPRG1 | |
545 | mfspr r10, SPRN_SPRG0 | |
546 | b InstructionStorage | |
547 | ||
548 | /* Debug Interrupt */ | |
eb0cd5fd | 549 | DEBUG_CRIT_EXCEPTION |
14cf11af PM |
550 | |
551 | /* | |
552 | * Local functions | |
1bc54c03 | 553 | */ |
14cf11af PM |
554 | |
555 | /* | |
556 | ||
557 | * Both the instruction and data TLB miss get to this | |
558 | * point to load the TLB. | |
559 | * r10 - EA of fault | |
1bc54c03 BH |
560 | * r11 - PTE high word value |
561 | * r12 - PTE low word value | |
562 | * r13 - TLB index | |
14cf11af PM |
563 | * MMUCR - loaded with proper value when we get here |
564 | * Upon exit, we reload everything and RFI. | |
565 | */ | |
566 | finish_tlb_load: | |
1bc54c03 BH |
567 | /* Combine RPN & ERPN an write WS 0 */ |
568 | rlwimi r11,r12,0,0,19 | |
569 | tlbwe r11,r13,PPC44x_TLB_XLAT | |
14cf11af PM |
570 | |
571 | /* | |
1bc54c03 | 572 | * Create WS1. This is the faulting address (EPN), |
14cf11af PM |
573 | * page size, and valid flag. |
574 | */ | |
1bc54c03 BH |
575 | li r11,PPC44x_TLB_VALID | PPC44x_TLB_4K |
576 | rlwimi r10,r11,0,20,31 /* Insert valid and page size*/ | |
577 | tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */ | |
578 | ||
579 | /* And WS 2 */ | |
580 | li r10,0xf85 /* Mask to apply from PTE */ | |
581 | rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ | |
582 | and r11,r12,r10 /* Mask PTE bits to keep */ | |
583 | andi. r10,r12,_PAGE_USER /* User page ? */ | |
584 | beq 1f /* nope, leave U bits empty */ | |
585 | rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ | |
586 | 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ | |
14cf11af PM |
587 | |
588 | /* Done...restore registers and get out of here. | |
589 | */ | |
590 | mfspr r11, SPRN_SPRG7R | |
591 | mtcr r11 | |
592 | mfspr r13, SPRN_SPRG5R | |
593 | mfspr r12, SPRN_SPRG4R | |
594 | mfspr r11, SPRN_SPRG1 | |
595 | mfspr r10, SPRN_SPRG0 | |
596 | rfi /* Force context change */ | |
597 | ||
598 | /* | |
599 | * Global functions | |
600 | */ | |
601 | ||
47c0bd1a BH |
602 | /* |
603 | * Adjust the machine check IVOR on 440A cores | |
604 | */ | |
605 | _GLOBAL(__fixup_440A_mcheck) | |
606 | li r3,MachineCheckA@l | |
607 | mtspr SPRN_IVOR1,r3 | |
608 | sync | |
609 | blr | |
610 | ||
14cf11af PM |
611 | /* |
612 | * extern void giveup_altivec(struct task_struct *prev) | |
613 | * | |
614 | * The 44x core does not have an AltiVec unit. | |
615 | */ | |
616 | _GLOBAL(giveup_altivec) | |
617 | blr | |
618 | ||
619 | /* | |
620 | * extern void giveup_fpu(struct task_struct *prev) | |
621 | * | |
622 | * The 44x core does not have an FPU. | |
623 | */ | |
624 | #ifndef CONFIG_PPC_FPU | |
625 | _GLOBAL(giveup_fpu) | |
626 | blr | |
627 | #endif | |
628 | ||
14cf11af PM |
629 | _GLOBAL(set_context) |
630 | ||
631 | #ifdef CONFIG_BDI_SWITCH | |
632 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
633 | * The PGDIR is the second parameter. | |
634 | */ | |
635 | lis r5, abatron_pteptrs@h | |
636 | ori r5, r5, abatron_pteptrs@l | |
637 | stw r4, 0x4(r5) | |
638 | #endif | |
639 | mtspr SPRN_PID,r3 | |
640 | isync /* Force context change */ | |
641 | blr | |
642 | ||
643 | /* | |
644 | * We put a few things here that have to be page-aligned. This stuff | |
645 | * goes at the beginning of the data segment, which is page-aligned. | |
646 | */ | |
647 | .data | |
ea703ce2 KG |
648 | .align 12 |
649 | .globl sdata | |
650 | sdata: | |
651 | .globl empty_zero_page | |
652 | empty_zero_page: | |
14cf11af PM |
653 | .space 4096 |
654 | ||
655 | /* | |
656 | * To support >32-bit physical addresses, we use an 8KB pgdir. | |
657 | */ | |
ea703ce2 KG |
658 | .globl swapper_pg_dir |
659 | swapper_pg_dir: | |
bee86f14 | 660 | .space PGD_TABLE_SIZE |
14cf11af | 661 | |
14cf11af PM |
662 | /* |
663 | * Room for two PTE pointers, usually the kernel and current user pointers | |
664 | * to their respective root page table. | |
665 | */ | |
666 | abatron_pteptrs: | |
667 | .space 8 |